1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @vdiv_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
6; CHECK-LABEL: vdiv_vv_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
9; CHECK-NEXT:    vdiv.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %vc = sdiv <vscale x 1 x i8> %va, %vb
12  ret <vscale x 1 x i8> %vc
13}
14
15define <vscale x 1 x i8> @vdiv_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
16; CHECK-LABEL: vdiv_vx_nxv1i8:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
19; CHECK-NEXT:    vdiv.vx v8, v8, a0
20; CHECK-NEXT:    ret
21  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
22  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
23  %vc = sdiv <vscale x 1 x i8> %va, %splat
24  ret <vscale x 1 x i8> %vc
25}
26
27define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
28; CHECK-LABEL: vdiv_vi_nxv1i8_0:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    li a0, 109
31; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
32; CHECK-NEXT:    vmulh.vx v9, v8, a0
33; CHECK-NEXT:    vsub.vv v8, v9, v8
34; CHECK-NEXT:    vsra.vi v8, v8, 2
35; CHECK-NEXT:    vsrl.vi v9, v8, 7
36; CHECK-NEXT:    vadd.vv v8, v8, v9
37; CHECK-NEXT:    ret
38  %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
39  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
40  %vc = sdiv <vscale x 1 x i8> %va, %splat
41  ret <vscale x 1 x i8> %vc
42}
43
44; Test V/1 to see if we can optimize it away for scalable vectors.
45define <vscale x 1 x i8> @vdiv_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
46; CHECK-LABEL: vdiv_vi_nxv1i8_1:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    ret
49  %head = insertelement <vscale x 1 x i8> undef, i8 1, i32 0
50  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
51  %vc = sdiv <vscale x 1 x i8> %va, %splat
52  ret <vscale x 1 x i8> %vc
53}
54
55; Test 0/V to see if we can optimize it away for scalable vectors.
56define <vscale x 1 x i8> @vdiv_iv_nxv1i8_0(<vscale x 1 x i8> %va) {
57; CHECK-LABEL: vdiv_iv_nxv1i8_0:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
60; CHECK-NEXT:    vmv.v.i v8, 0
61; CHECK-NEXT:    ret
62  %head = insertelement <vscale x 1 x i8> undef, i8 0, i32 0
63  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
64  %vc = sdiv <vscale x 1 x i8> %splat, %va
65  ret <vscale x 1 x i8> %vc
66}
67
68define <vscale x 2 x i8> @vdiv_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
69; CHECK-LABEL: vdiv_vv_nxv2i8:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
72; CHECK-NEXT:    vdiv.vv v8, v8, v9
73; CHECK-NEXT:    ret
74  %vc = sdiv <vscale x 2 x i8> %va, %vb
75  ret <vscale x 2 x i8> %vc
76}
77
78define <vscale x 2 x i8> @vdiv_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
79; CHECK-LABEL: vdiv_vx_nxv2i8:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
82; CHECK-NEXT:    vdiv.vx v8, v8, a0
83; CHECK-NEXT:    ret
84  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
85  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
86  %vc = sdiv <vscale x 2 x i8> %va, %splat
87  ret <vscale x 2 x i8> %vc
88}
89
90define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
91; CHECK-LABEL: vdiv_vi_nxv2i8_0:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    li a0, 109
94; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
95; CHECK-NEXT:    vmulh.vx v9, v8, a0
96; CHECK-NEXT:    vsub.vv v8, v9, v8
97; CHECK-NEXT:    vsra.vi v8, v8, 2
98; CHECK-NEXT:    vsrl.vi v9, v8, 7
99; CHECK-NEXT:    vadd.vv v8, v8, v9
100; CHECK-NEXT:    ret
101  %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
102  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
103  %vc = sdiv <vscale x 2 x i8> %va, %splat
104  ret <vscale x 2 x i8> %vc
105}
106
107define <vscale x 4 x i8> @vdiv_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
108; CHECK-LABEL: vdiv_vv_nxv4i8:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
111; CHECK-NEXT:    vdiv.vv v8, v8, v9
112; CHECK-NEXT:    ret
113  %vc = sdiv <vscale x 4 x i8> %va, %vb
114  ret <vscale x 4 x i8> %vc
115}
116
117define <vscale x 4 x i8> @vdiv_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
118; CHECK-LABEL: vdiv_vx_nxv4i8:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
121; CHECK-NEXT:    vdiv.vx v8, v8, a0
122; CHECK-NEXT:    ret
123  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
124  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
125  %vc = sdiv <vscale x 4 x i8> %va, %splat
126  ret <vscale x 4 x i8> %vc
127}
128
129define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
130; CHECK-LABEL: vdiv_vi_nxv4i8_0:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    li a0, 109
133; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
134; CHECK-NEXT:    vmulh.vx v9, v8, a0
135; CHECK-NEXT:    vsub.vv v8, v9, v8
136; CHECK-NEXT:    vsra.vi v8, v8, 2
137; CHECK-NEXT:    vsrl.vi v9, v8, 7
138; CHECK-NEXT:    vadd.vv v8, v8, v9
139; CHECK-NEXT:    ret
140  %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
141  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
142  %vc = sdiv <vscale x 4 x i8> %va, %splat
143  ret <vscale x 4 x i8> %vc
144}
145
146define <vscale x 8 x i8> @vdiv_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
147; CHECK-LABEL: vdiv_vv_nxv8i8:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
150; CHECK-NEXT:    vdiv.vv v8, v8, v9
151; CHECK-NEXT:    ret
152  %vc = sdiv <vscale x 8 x i8> %va, %vb
153  ret <vscale x 8 x i8> %vc
154}
155
156define <vscale x 8 x i8> @vdiv_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
157; CHECK-LABEL: vdiv_vx_nxv8i8:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
160; CHECK-NEXT:    vdiv.vx v8, v8, a0
161; CHECK-NEXT:    ret
162  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
163  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
164  %vc = sdiv <vscale x 8 x i8> %va, %splat
165  ret <vscale x 8 x i8> %vc
166}
167
168define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
169; CHECK-LABEL: vdiv_vi_nxv8i8_0:
170; CHECK:       # %bb.0:
171; CHECK-NEXT:    li a0, 109
172; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
173; CHECK-NEXT:    vmulh.vx v9, v8, a0
174; CHECK-NEXT:    vsub.vv v8, v9, v8
175; CHECK-NEXT:    vsra.vi v8, v8, 2
176; CHECK-NEXT:    vsrl.vi v9, v8, 7
177; CHECK-NEXT:    vadd.vv v8, v8, v9
178; CHECK-NEXT:    ret
179  %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
180  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
181  %vc = sdiv <vscale x 8 x i8> %va, %splat
182  ret <vscale x 8 x i8> %vc
183}
184
185define <vscale x 16 x i8> @vdiv_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
186; CHECK-LABEL: vdiv_vv_nxv16i8:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
189; CHECK-NEXT:    vdiv.vv v8, v8, v10
190; CHECK-NEXT:    ret
191  %vc = sdiv <vscale x 16 x i8> %va, %vb
192  ret <vscale x 16 x i8> %vc
193}
194
195define <vscale x 16 x i8> @vdiv_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
196; CHECK-LABEL: vdiv_vx_nxv16i8:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
199; CHECK-NEXT:    vdiv.vx v8, v8, a0
200; CHECK-NEXT:    ret
201  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
202  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
203  %vc = sdiv <vscale x 16 x i8> %va, %splat
204  ret <vscale x 16 x i8> %vc
205}
206
207define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
208; CHECK-LABEL: vdiv_vi_nxv16i8_0:
209; CHECK:       # %bb.0:
210; CHECK-NEXT:    li a0, 109
211; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
212; CHECK-NEXT:    vmulh.vx v10, v8, a0
213; CHECK-NEXT:    vsub.vv v8, v10, v8
214; CHECK-NEXT:    vsra.vi v8, v8, 2
215; CHECK-NEXT:    vsrl.vi v10, v8, 7
216; CHECK-NEXT:    vadd.vv v8, v8, v10
217; CHECK-NEXT:    ret
218  %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
219  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
220  %vc = sdiv <vscale x 16 x i8> %va, %splat
221  ret <vscale x 16 x i8> %vc
222}
223
224define <vscale x 32 x i8> @vdiv_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
225; CHECK-LABEL: vdiv_vv_nxv32i8:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
228; CHECK-NEXT:    vdiv.vv v8, v8, v12
229; CHECK-NEXT:    ret
230  %vc = sdiv <vscale x 32 x i8> %va, %vb
231  ret <vscale x 32 x i8> %vc
232}
233
234define <vscale x 32 x i8> @vdiv_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
235; CHECK-LABEL: vdiv_vx_nxv32i8:
236; CHECK:       # %bb.0:
237; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
238; CHECK-NEXT:    vdiv.vx v8, v8, a0
239; CHECK-NEXT:    ret
240  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
241  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
242  %vc = sdiv <vscale x 32 x i8> %va, %splat
243  ret <vscale x 32 x i8> %vc
244}
245
246define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
247; CHECK-LABEL: vdiv_vi_nxv32i8_0:
248; CHECK:       # %bb.0:
249; CHECK-NEXT:    li a0, 109
250; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
251; CHECK-NEXT:    vmulh.vx v12, v8, a0
252; CHECK-NEXT:    vsub.vv v8, v12, v8
253; CHECK-NEXT:    vsra.vi v8, v8, 2
254; CHECK-NEXT:    vsrl.vi v12, v8, 7
255; CHECK-NEXT:    vadd.vv v8, v8, v12
256; CHECK-NEXT:    ret
257  %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
258  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
259  %vc = sdiv <vscale x 32 x i8> %va, %splat
260  ret <vscale x 32 x i8> %vc
261}
262
263define <vscale x 64 x i8> @vdiv_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
264; CHECK-LABEL: vdiv_vv_nxv64i8:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
267; CHECK-NEXT:    vdiv.vv v8, v8, v16
268; CHECK-NEXT:    ret
269  %vc = sdiv <vscale x 64 x i8> %va, %vb
270  ret <vscale x 64 x i8> %vc
271}
272
273define <vscale x 64 x i8> @vdiv_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
274; CHECK-LABEL: vdiv_vx_nxv64i8:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
277; CHECK-NEXT:    vdiv.vx v8, v8, a0
278; CHECK-NEXT:    ret
279  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
280  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
281  %vc = sdiv <vscale x 64 x i8> %va, %splat
282  ret <vscale x 64 x i8> %vc
283}
284
285define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
286; CHECK-LABEL: vdiv_vi_nxv64i8_0:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    li a0, 109
289; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
290; CHECK-NEXT:    vmulh.vx v16, v8, a0
291; CHECK-NEXT:    vsub.vv v8, v16, v8
292; CHECK-NEXT:    vsra.vi v8, v8, 2
293; CHECK-NEXT:    vsrl.vi v16, v8, 7
294; CHECK-NEXT:    vadd.vv v8, v8, v16
295; CHECK-NEXT:    ret
296  %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
297  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
298  %vc = sdiv <vscale x 64 x i8> %va, %splat
299  ret <vscale x 64 x i8> %vc
300}
301
302define <vscale x 1 x i16> @vdiv_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
303; CHECK-LABEL: vdiv_vv_nxv1i16:
304; CHECK:       # %bb.0:
305; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
306; CHECK-NEXT:    vdiv.vv v8, v8, v9
307; CHECK-NEXT:    ret
308  %vc = sdiv <vscale x 1 x i16> %va, %vb
309  ret <vscale x 1 x i16> %vc
310}
311
312define <vscale x 1 x i16> @vdiv_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
313; CHECK-LABEL: vdiv_vx_nxv1i16:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
316; CHECK-NEXT:    vdiv.vx v8, v8, a0
317; CHECK-NEXT:    ret
318  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
319  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
320  %vc = sdiv <vscale x 1 x i16> %va, %splat
321  ret <vscale x 1 x i16> %vc
322}
323
324define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
325; RV32-LABEL: vdiv_vi_nxv1i16_0:
326; RV32:       # %bb.0:
327; RV32-NEXT:    lui a0, 1048571
328; RV32-NEXT:    addi a0, a0, 1755
329; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
330; RV32-NEXT:    vmulh.vx v8, v8, a0
331; RV32-NEXT:    vsra.vi v8, v8, 1
332; RV32-NEXT:    vsrl.vi v9, v8, 15
333; RV32-NEXT:    vadd.vv v8, v8, v9
334; RV32-NEXT:    ret
335;
336; RV64-LABEL: vdiv_vi_nxv1i16_0:
337; RV64:       # %bb.0:
338; RV64-NEXT:    lui a0, 1048571
339; RV64-NEXT:    addiw a0, a0, 1755
340; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
341; RV64-NEXT:    vmulh.vx v8, v8, a0
342; RV64-NEXT:    vsra.vi v8, v8, 1
343; RV64-NEXT:    vsrl.vi v9, v8, 15
344; RV64-NEXT:    vadd.vv v8, v8, v9
345; RV64-NEXT:    ret
346  %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
347  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
348  %vc = sdiv <vscale x 1 x i16> %va, %splat
349  ret <vscale x 1 x i16> %vc
350}
351
352define <vscale x 2 x i16> @vdiv_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
353; CHECK-LABEL: vdiv_vv_nxv2i16:
354; CHECK:       # %bb.0:
355; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
356; CHECK-NEXT:    vdiv.vv v8, v8, v9
357; CHECK-NEXT:    ret
358  %vc = sdiv <vscale x 2 x i16> %va, %vb
359  ret <vscale x 2 x i16> %vc
360}
361
362define <vscale x 2 x i16> @vdiv_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
363; CHECK-LABEL: vdiv_vx_nxv2i16:
364; CHECK:       # %bb.0:
365; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
366; CHECK-NEXT:    vdiv.vx v8, v8, a0
367; CHECK-NEXT:    ret
368  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
369  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
370  %vc = sdiv <vscale x 2 x i16> %va, %splat
371  ret <vscale x 2 x i16> %vc
372}
373
374define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
375; RV32-LABEL: vdiv_vi_nxv2i16_0:
376; RV32:       # %bb.0:
377; RV32-NEXT:    lui a0, 1048571
378; RV32-NEXT:    addi a0, a0, 1755
379; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
380; RV32-NEXT:    vmulh.vx v8, v8, a0
381; RV32-NEXT:    vsra.vi v8, v8, 1
382; RV32-NEXT:    vsrl.vi v9, v8, 15
383; RV32-NEXT:    vadd.vv v8, v8, v9
384; RV32-NEXT:    ret
385;
386; RV64-LABEL: vdiv_vi_nxv2i16_0:
387; RV64:       # %bb.0:
388; RV64-NEXT:    lui a0, 1048571
389; RV64-NEXT:    addiw a0, a0, 1755
390; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
391; RV64-NEXT:    vmulh.vx v8, v8, a0
392; RV64-NEXT:    vsra.vi v8, v8, 1
393; RV64-NEXT:    vsrl.vi v9, v8, 15
394; RV64-NEXT:    vadd.vv v8, v8, v9
395; RV64-NEXT:    ret
396  %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
397  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
398  %vc = sdiv <vscale x 2 x i16> %va, %splat
399  ret <vscale x 2 x i16> %vc
400}
401
402define <vscale x 4 x i16> @vdiv_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
403; CHECK-LABEL: vdiv_vv_nxv4i16:
404; CHECK:       # %bb.0:
405; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
406; CHECK-NEXT:    vdiv.vv v8, v8, v9
407; CHECK-NEXT:    ret
408  %vc = sdiv <vscale x 4 x i16> %va, %vb
409  ret <vscale x 4 x i16> %vc
410}
411
412define <vscale x 4 x i16> @vdiv_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
413; CHECK-LABEL: vdiv_vx_nxv4i16:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
416; CHECK-NEXT:    vdiv.vx v8, v8, a0
417; CHECK-NEXT:    ret
418  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
419  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
420  %vc = sdiv <vscale x 4 x i16> %va, %splat
421  ret <vscale x 4 x i16> %vc
422}
423
424define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
425; RV32-LABEL: vdiv_vi_nxv4i16_0:
426; RV32:       # %bb.0:
427; RV32-NEXT:    lui a0, 1048571
428; RV32-NEXT:    addi a0, a0, 1755
429; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
430; RV32-NEXT:    vmulh.vx v8, v8, a0
431; RV32-NEXT:    vsra.vi v8, v8, 1
432; RV32-NEXT:    vsrl.vi v9, v8, 15
433; RV32-NEXT:    vadd.vv v8, v8, v9
434; RV32-NEXT:    ret
435;
436; RV64-LABEL: vdiv_vi_nxv4i16_0:
437; RV64:       # %bb.0:
438; RV64-NEXT:    lui a0, 1048571
439; RV64-NEXT:    addiw a0, a0, 1755
440; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
441; RV64-NEXT:    vmulh.vx v8, v8, a0
442; RV64-NEXT:    vsra.vi v8, v8, 1
443; RV64-NEXT:    vsrl.vi v9, v8, 15
444; RV64-NEXT:    vadd.vv v8, v8, v9
445; RV64-NEXT:    ret
446  %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
447  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
448  %vc = sdiv <vscale x 4 x i16> %va, %splat
449  ret <vscale x 4 x i16> %vc
450}
451
452define <vscale x 8 x i16> @vdiv_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
453; CHECK-LABEL: vdiv_vv_nxv8i16:
454; CHECK:       # %bb.0:
455; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
456; CHECK-NEXT:    vdiv.vv v8, v8, v10
457; CHECK-NEXT:    ret
458  %vc = sdiv <vscale x 8 x i16> %va, %vb
459  ret <vscale x 8 x i16> %vc
460}
461
462define <vscale x 8 x i16> @vdiv_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
463; CHECK-LABEL: vdiv_vx_nxv8i16:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
466; CHECK-NEXT:    vdiv.vx v8, v8, a0
467; CHECK-NEXT:    ret
468  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
469  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
470  %vc = sdiv <vscale x 8 x i16> %va, %splat
471  ret <vscale x 8 x i16> %vc
472}
473
474define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
475; RV32-LABEL: vdiv_vi_nxv8i16_0:
476; RV32:       # %bb.0:
477; RV32-NEXT:    lui a0, 1048571
478; RV32-NEXT:    addi a0, a0, 1755
479; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
480; RV32-NEXT:    vmulh.vx v8, v8, a0
481; RV32-NEXT:    vsra.vi v8, v8, 1
482; RV32-NEXT:    vsrl.vi v10, v8, 15
483; RV32-NEXT:    vadd.vv v8, v8, v10
484; RV32-NEXT:    ret
485;
486; RV64-LABEL: vdiv_vi_nxv8i16_0:
487; RV64:       # %bb.0:
488; RV64-NEXT:    lui a0, 1048571
489; RV64-NEXT:    addiw a0, a0, 1755
490; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
491; RV64-NEXT:    vmulh.vx v8, v8, a0
492; RV64-NEXT:    vsra.vi v8, v8, 1
493; RV64-NEXT:    vsrl.vi v10, v8, 15
494; RV64-NEXT:    vadd.vv v8, v8, v10
495; RV64-NEXT:    ret
496  %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
497  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
498  %vc = sdiv <vscale x 8 x i16> %va, %splat
499  ret <vscale x 8 x i16> %vc
500}
501
502define <vscale x 16 x i16> @vdiv_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
503; CHECK-LABEL: vdiv_vv_nxv16i16:
504; CHECK:       # %bb.0:
505; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
506; CHECK-NEXT:    vdiv.vv v8, v8, v12
507; CHECK-NEXT:    ret
508  %vc = sdiv <vscale x 16 x i16> %va, %vb
509  ret <vscale x 16 x i16> %vc
510}
511
512define <vscale x 16 x i16> @vdiv_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
513; CHECK-LABEL: vdiv_vx_nxv16i16:
514; CHECK:       # %bb.0:
515; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
516; CHECK-NEXT:    vdiv.vx v8, v8, a0
517; CHECK-NEXT:    ret
518  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
519  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
520  %vc = sdiv <vscale x 16 x i16> %va, %splat
521  ret <vscale x 16 x i16> %vc
522}
523
524define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
525; RV32-LABEL: vdiv_vi_nxv16i16_0:
526; RV32:       # %bb.0:
527; RV32-NEXT:    lui a0, 1048571
528; RV32-NEXT:    addi a0, a0, 1755
529; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
530; RV32-NEXT:    vmulh.vx v8, v8, a0
531; RV32-NEXT:    vsra.vi v8, v8, 1
532; RV32-NEXT:    vsrl.vi v12, v8, 15
533; RV32-NEXT:    vadd.vv v8, v8, v12
534; RV32-NEXT:    ret
535;
536; RV64-LABEL: vdiv_vi_nxv16i16_0:
537; RV64:       # %bb.0:
538; RV64-NEXT:    lui a0, 1048571
539; RV64-NEXT:    addiw a0, a0, 1755
540; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
541; RV64-NEXT:    vmulh.vx v8, v8, a0
542; RV64-NEXT:    vsra.vi v8, v8, 1
543; RV64-NEXT:    vsrl.vi v12, v8, 15
544; RV64-NEXT:    vadd.vv v8, v8, v12
545; RV64-NEXT:    ret
546  %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
547  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
548  %vc = sdiv <vscale x 16 x i16> %va, %splat
549  ret <vscale x 16 x i16> %vc
550}
551
552define <vscale x 32 x i16> @vdiv_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
553; CHECK-LABEL: vdiv_vv_nxv32i16:
554; CHECK:       # %bb.0:
555; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
556; CHECK-NEXT:    vdiv.vv v8, v8, v16
557; CHECK-NEXT:    ret
558  %vc = sdiv <vscale x 32 x i16> %va, %vb
559  ret <vscale x 32 x i16> %vc
560}
561
562define <vscale x 32 x i16> @vdiv_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
563; CHECK-LABEL: vdiv_vx_nxv32i16:
564; CHECK:       # %bb.0:
565; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
566; CHECK-NEXT:    vdiv.vx v8, v8, a0
567; CHECK-NEXT:    ret
568  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
569  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
570  %vc = sdiv <vscale x 32 x i16> %va, %splat
571  ret <vscale x 32 x i16> %vc
572}
573
574define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
575; RV32-LABEL: vdiv_vi_nxv32i16_0:
576; RV32:       # %bb.0:
577; RV32-NEXT:    lui a0, 1048571
578; RV32-NEXT:    addi a0, a0, 1755
579; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
580; RV32-NEXT:    vmulh.vx v8, v8, a0
581; RV32-NEXT:    vsra.vi v8, v8, 1
582; RV32-NEXT:    vsrl.vi v16, v8, 15
583; RV32-NEXT:    vadd.vv v8, v8, v16
584; RV32-NEXT:    ret
585;
586; RV64-LABEL: vdiv_vi_nxv32i16_0:
587; RV64:       # %bb.0:
588; RV64-NEXT:    lui a0, 1048571
589; RV64-NEXT:    addiw a0, a0, 1755
590; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
591; RV64-NEXT:    vmulh.vx v8, v8, a0
592; RV64-NEXT:    vsra.vi v8, v8, 1
593; RV64-NEXT:    vsrl.vi v16, v8, 15
594; RV64-NEXT:    vadd.vv v8, v8, v16
595; RV64-NEXT:    ret
596  %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
597  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
598  %vc = sdiv <vscale x 32 x i16> %va, %splat
599  ret <vscale x 32 x i16> %vc
600}
601
602define <vscale x 1 x i32> @vdiv_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
603; CHECK-LABEL: vdiv_vv_nxv1i32:
604; CHECK:       # %bb.0:
605; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
606; CHECK-NEXT:    vdiv.vv v8, v8, v9
607; CHECK-NEXT:    ret
608  %vc = sdiv <vscale x 1 x i32> %va, %vb
609  ret <vscale x 1 x i32> %vc
610}
611
612define <vscale x 1 x i32> @vdiv_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
613; CHECK-LABEL: vdiv_vx_nxv1i32:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
616; CHECK-NEXT:    vdiv.vx v8, v8, a0
617; CHECK-NEXT:    ret
618  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
619  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
620  %vc = sdiv <vscale x 1 x i32> %va, %splat
621  ret <vscale x 1 x i32> %vc
622}
623
624define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
625; RV32-LABEL: vdiv_vi_nxv1i32_0:
626; RV32:       # %bb.0:
627; RV32-NEXT:    lui a0, 449390
628; RV32-NEXT:    addi a0, a0, -1171
629; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
630; RV32-NEXT:    vmulh.vx v9, v8, a0
631; RV32-NEXT:    vsub.vv v8, v9, v8
632; RV32-NEXT:    vsrl.vi v9, v8, 31
633; RV32-NEXT:    vsra.vi v8, v8, 2
634; RV32-NEXT:    vadd.vv v8, v8, v9
635; RV32-NEXT:    ret
636;
637; RV64-LABEL: vdiv_vi_nxv1i32_0:
638; RV64:       # %bb.0:
639; RV64-NEXT:    lui a0, 449390
640; RV64-NEXT:    addiw a0, a0, -1171
641; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
642; RV64-NEXT:    vmulh.vx v9, v8, a0
643; RV64-NEXT:    vsub.vv v8, v9, v8
644; RV64-NEXT:    vsra.vi v8, v8, 2
645; RV64-NEXT:    vsrl.vi v9, v8, 31
646; RV64-NEXT:    vadd.vv v8, v8, v9
647; RV64-NEXT:    ret
648  %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
649  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
650  %vc = sdiv <vscale x 1 x i32> %va, %splat
651  ret <vscale x 1 x i32> %vc
652}
653
654define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
655; CHECK-LABEL: vdiv_vv_nxv2i32:
656; CHECK:       # %bb.0:
657; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
658; CHECK-NEXT:    vdiv.vv v8, v8, v9
659; CHECK-NEXT:    ret
660  %vc = sdiv <vscale x 2 x i32> %va, %vb
661  ret <vscale x 2 x i32> %vc
662}
663
664define <vscale x 2 x i32> @vdiv_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
665; CHECK-LABEL: vdiv_vx_nxv2i32:
666; CHECK:       # %bb.0:
667; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
668; CHECK-NEXT:    vdiv.vx v8, v8, a0
669; CHECK-NEXT:    ret
670  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
671  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
672  %vc = sdiv <vscale x 2 x i32> %va, %splat
673  ret <vscale x 2 x i32> %vc
674}
675
676define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
677; RV32-LABEL: vdiv_vi_nxv2i32_0:
678; RV32:       # %bb.0:
679; RV32-NEXT:    lui a0, 449390
680; RV32-NEXT:    addi a0, a0, -1171
681; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
682; RV32-NEXT:    vmulh.vx v9, v8, a0
683; RV32-NEXT:    vsub.vv v8, v9, v8
684; RV32-NEXT:    vsrl.vi v9, v8, 31
685; RV32-NEXT:    vsra.vi v8, v8, 2
686; RV32-NEXT:    vadd.vv v8, v8, v9
687; RV32-NEXT:    ret
688;
689; RV64-LABEL: vdiv_vi_nxv2i32_0:
690; RV64:       # %bb.0:
691; RV64-NEXT:    lui a0, 449390
692; RV64-NEXT:    addiw a0, a0, -1171
693; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
694; RV64-NEXT:    vmulh.vx v9, v8, a0
695; RV64-NEXT:    vsub.vv v8, v9, v8
696; RV64-NEXT:    vsra.vi v8, v8, 2
697; RV64-NEXT:    vsrl.vi v9, v8, 31
698; RV64-NEXT:    vadd.vv v8, v8, v9
699; RV64-NEXT:    ret
700  %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
701  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
702  %vc = sdiv <vscale x 2 x i32> %va, %splat
703  ret <vscale x 2 x i32> %vc
704}
705
706define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
707; CHECK-LABEL: vdiv_vv_nxv4i32:
708; CHECK:       # %bb.0:
709; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
710; CHECK-NEXT:    vdiv.vv v8, v8, v10
711; CHECK-NEXT:    ret
712  %vc = sdiv <vscale x 4 x i32> %va, %vb
713  ret <vscale x 4 x i32> %vc
714}
715
716define <vscale x 4 x i32> @vdiv_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
717; CHECK-LABEL: vdiv_vx_nxv4i32:
718; CHECK:       # %bb.0:
719; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
720; CHECK-NEXT:    vdiv.vx v8, v8, a0
721; CHECK-NEXT:    ret
722  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
723  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
724  %vc = sdiv <vscale x 4 x i32> %va, %splat
725  ret <vscale x 4 x i32> %vc
726}
727
728define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
729; RV32-LABEL: vdiv_vi_nxv4i32_0:
730; RV32:       # %bb.0:
731; RV32-NEXT:    lui a0, 449390
732; RV32-NEXT:    addi a0, a0, -1171
733; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
734; RV32-NEXT:    vmulh.vx v10, v8, a0
735; RV32-NEXT:    vsub.vv v8, v10, v8
736; RV32-NEXT:    vsrl.vi v10, v8, 31
737; RV32-NEXT:    vsra.vi v8, v8, 2
738; RV32-NEXT:    vadd.vv v8, v8, v10
739; RV32-NEXT:    ret
740;
741; RV64-LABEL: vdiv_vi_nxv4i32_0:
742; RV64:       # %bb.0:
743; RV64-NEXT:    lui a0, 449390
744; RV64-NEXT:    addiw a0, a0, -1171
745; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
746; RV64-NEXT:    vmulh.vx v10, v8, a0
747; RV64-NEXT:    vsub.vv v8, v10, v8
748; RV64-NEXT:    vsra.vi v8, v8, 2
749; RV64-NEXT:    vsrl.vi v10, v8, 31
750; RV64-NEXT:    vadd.vv v8, v8, v10
751; RV64-NEXT:    ret
752  %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
753  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
754  %vc = sdiv <vscale x 4 x i32> %va, %splat
755  ret <vscale x 4 x i32> %vc
756}
757
758define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
759; CHECK-LABEL: vdiv_vv_nxv8i32:
760; CHECK:       # %bb.0:
761; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
762; CHECK-NEXT:    vdiv.vv v8, v8, v12
763; CHECK-NEXT:    ret
764  %vc = sdiv <vscale x 8 x i32> %va, %vb
765  ret <vscale x 8 x i32> %vc
766}
767
768define <vscale x 8 x i32> @vdiv_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
769; CHECK-LABEL: vdiv_vx_nxv8i32:
770; CHECK:       # %bb.0:
771; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
772; CHECK-NEXT:    vdiv.vx v8, v8, a0
773; CHECK-NEXT:    ret
774  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
775  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
776  %vc = sdiv <vscale x 8 x i32> %va, %splat
777  ret <vscale x 8 x i32> %vc
778}
779
780define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
781; RV32-LABEL: vdiv_vi_nxv8i32_0:
782; RV32:       # %bb.0:
783; RV32-NEXT:    lui a0, 449390
784; RV32-NEXT:    addi a0, a0, -1171
785; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
786; RV32-NEXT:    vmulh.vx v12, v8, a0
787; RV32-NEXT:    vsub.vv v8, v12, v8
788; RV32-NEXT:    vsrl.vi v12, v8, 31
789; RV32-NEXT:    vsra.vi v8, v8, 2
790; RV32-NEXT:    vadd.vv v8, v8, v12
791; RV32-NEXT:    ret
792;
793; RV64-LABEL: vdiv_vi_nxv8i32_0:
794; RV64:       # %bb.0:
795; RV64-NEXT:    lui a0, 449390
796; RV64-NEXT:    addiw a0, a0, -1171
797; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
798; RV64-NEXT:    vmulh.vx v12, v8, a0
799; RV64-NEXT:    vsub.vv v8, v12, v8
800; RV64-NEXT:    vsra.vi v8, v8, 2
801; RV64-NEXT:    vsrl.vi v12, v8, 31
802; RV64-NEXT:    vadd.vv v8, v8, v12
803; RV64-NEXT:    ret
804  %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
805  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
806  %vc = sdiv <vscale x 8 x i32> %va, %splat
807  ret <vscale x 8 x i32> %vc
808}
809
810define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
811; CHECK-LABEL: vdiv_vv_nxv16i32:
812; CHECK:       # %bb.0:
813; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
814; CHECK-NEXT:    vdiv.vv v8, v8, v16
815; CHECK-NEXT:    ret
816  %vc = sdiv <vscale x 16 x i32> %va, %vb
817  ret <vscale x 16 x i32> %vc
818}
819
820define <vscale x 16 x i32> @vdiv_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
821; CHECK-LABEL: vdiv_vx_nxv16i32:
822; CHECK:       # %bb.0:
823; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
824; CHECK-NEXT:    vdiv.vx v8, v8, a0
825; CHECK-NEXT:    ret
826  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
827  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
828  %vc = sdiv <vscale x 16 x i32> %va, %splat
829  ret <vscale x 16 x i32> %vc
830}
831
832define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
833; RV32-LABEL: vdiv_vi_nxv16i32_0:
834; RV32:       # %bb.0:
835; RV32-NEXT:    lui a0, 449390
836; RV32-NEXT:    addi a0, a0, -1171
837; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
838; RV32-NEXT:    vmulh.vx v16, v8, a0
839; RV32-NEXT:    vsub.vv v8, v16, v8
840; RV32-NEXT:    vsrl.vi v16, v8, 31
841; RV32-NEXT:    vsra.vi v8, v8, 2
842; RV32-NEXT:    vadd.vv v8, v8, v16
843; RV32-NEXT:    ret
844;
845; RV64-LABEL: vdiv_vi_nxv16i32_0:
846; RV64:       # %bb.0:
847; RV64-NEXT:    lui a0, 449390
848; RV64-NEXT:    addiw a0, a0, -1171
849; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
850; RV64-NEXT:    vmulh.vx v16, v8, a0
851; RV64-NEXT:    vsub.vv v8, v16, v8
852; RV64-NEXT:    vsra.vi v8, v8, 2
853; RV64-NEXT:    vsrl.vi v16, v8, 31
854; RV64-NEXT:    vadd.vv v8, v8, v16
855; RV64-NEXT:    ret
856  %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
857  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
858  %vc = sdiv <vscale x 16 x i32> %va, %splat
859  ret <vscale x 16 x i32> %vc
860}
861
862define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
863; CHECK-LABEL: vdiv_vv_nxv1i64:
864; CHECK:       # %bb.0:
865; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
866; CHECK-NEXT:    vdiv.vv v8, v8, v9
867; CHECK-NEXT:    ret
868  %vc = sdiv <vscale x 1 x i64> %va, %vb
869  ret <vscale x 1 x i64> %vc
870}
871
872define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
873; RV32-LABEL: vdiv_vx_nxv1i64:
874; RV32:       # %bb.0:
875; RV32-NEXT:    addi sp, sp, -16
876; RV32-NEXT:    .cfi_def_cfa_offset 16
877; RV32-NEXT:    sw a1, 12(sp)
878; RV32-NEXT:    sw a0, 8(sp)
879; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
880; RV32-NEXT:    addi a0, sp, 8
881; RV32-NEXT:    vlse64.v v9, (a0), zero
882; RV32-NEXT:    vdiv.vv v8, v8, v9
883; RV32-NEXT:    addi sp, sp, 16
884; RV32-NEXT:    ret
885;
886; RV64-LABEL: vdiv_vx_nxv1i64:
887; RV64:       # %bb.0:
888; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
889; RV64-NEXT:    vdiv.vx v8, v8, a0
890; RV64-NEXT:    ret
891  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
892  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
893  %vc = sdiv <vscale x 1 x i64> %va, %splat
894  ret <vscale x 1 x i64> %vc
895}
896
897define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
898; RV32-LABEL: vdiv_vi_nxv1i64_0:
899; RV32:       # %bb.0:
900; RV32-NEXT:    addi sp, sp, -16
901; RV32-NEXT:    .cfi_def_cfa_offset 16
902; RV32-NEXT:    lui a0, 748983
903; RV32-NEXT:    addi a0, a0, -586
904; RV32-NEXT:    sw a0, 12(sp)
905; RV32-NEXT:    lui a0, 898779
906; RV32-NEXT:    addi a0, a0, 1755
907; RV32-NEXT:    sw a0, 8(sp)
908; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
909; RV32-NEXT:    addi a0, sp, 8
910; RV32-NEXT:    vlse64.v v9, (a0), zero
911; RV32-NEXT:    vmulh.vv v8, v8, v9
912; RV32-NEXT:    li a0, 63
913; RV32-NEXT:    vsrl.vx v9, v8, a0
914; RV32-NEXT:    vsra.vi v8, v8, 1
915; RV32-NEXT:    vadd.vv v8, v8, v9
916; RV32-NEXT:    addi sp, sp, 16
917; RV32-NEXT:    ret
918;
919; RV64-LABEL: vdiv_vi_nxv1i64_0:
920; RV64:       # %bb.0:
921; RV64-NEXT:    lui a0, %hi(.LCPI58_0)
922; RV64-NEXT:    ld a0, %lo(.LCPI58_0)(a0)
923; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
924; RV64-NEXT:    vmulh.vx v8, v8, a0
925; RV64-NEXT:    li a0, 63
926; RV64-NEXT:    vsrl.vx v9, v8, a0
927; RV64-NEXT:    vsra.vi v8, v8, 1
928; RV64-NEXT:    vadd.vv v8, v8, v9
929; RV64-NEXT:    ret
930  %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
931  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
932  %vc = sdiv <vscale x 1 x i64> %va, %splat
933  ret <vscale x 1 x i64> %vc
934}
935
936define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
937; CHECK-LABEL: vdiv_vv_nxv2i64:
938; CHECK:       # %bb.0:
939; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
940; CHECK-NEXT:    vdiv.vv v8, v8, v10
941; CHECK-NEXT:    ret
942  %vc = sdiv <vscale x 2 x i64> %va, %vb
943  ret <vscale x 2 x i64> %vc
944}
945
946define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
947; RV32-LABEL: vdiv_vx_nxv2i64:
948; RV32:       # %bb.0:
949; RV32-NEXT:    addi sp, sp, -16
950; RV32-NEXT:    .cfi_def_cfa_offset 16
951; RV32-NEXT:    sw a1, 12(sp)
952; RV32-NEXT:    sw a0, 8(sp)
953; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
954; RV32-NEXT:    addi a0, sp, 8
955; RV32-NEXT:    vlse64.v v10, (a0), zero
956; RV32-NEXT:    vdiv.vv v8, v8, v10
957; RV32-NEXT:    addi sp, sp, 16
958; RV32-NEXT:    ret
959;
960; RV64-LABEL: vdiv_vx_nxv2i64:
961; RV64:       # %bb.0:
962; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
963; RV64-NEXT:    vdiv.vx v8, v8, a0
964; RV64-NEXT:    ret
965  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
966  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
967  %vc = sdiv <vscale x 2 x i64> %va, %splat
968  ret <vscale x 2 x i64> %vc
969}
970
971define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
972; RV32-LABEL: vdiv_vi_nxv2i64_0:
973; RV32:       # %bb.0:
974; RV32-NEXT:    addi sp, sp, -16
975; RV32-NEXT:    .cfi_def_cfa_offset 16
976; RV32-NEXT:    lui a0, 748983
977; RV32-NEXT:    addi a0, a0, -586
978; RV32-NEXT:    sw a0, 12(sp)
979; RV32-NEXT:    lui a0, 898779
980; RV32-NEXT:    addi a0, a0, 1755
981; RV32-NEXT:    sw a0, 8(sp)
982; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
983; RV32-NEXT:    addi a0, sp, 8
984; RV32-NEXT:    vlse64.v v10, (a0), zero
985; RV32-NEXT:    vmulh.vv v8, v8, v10
986; RV32-NEXT:    li a0, 63
987; RV32-NEXT:    vsrl.vx v10, v8, a0
988; RV32-NEXT:    vsra.vi v8, v8, 1
989; RV32-NEXT:    vadd.vv v8, v8, v10
990; RV32-NEXT:    addi sp, sp, 16
991; RV32-NEXT:    ret
992;
993; RV64-LABEL: vdiv_vi_nxv2i64_0:
994; RV64:       # %bb.0:
995; RV64-NEXT:    lui a0, %hi(.LCPI61_0)
996; RV64-NEXT:    ld a0, %lo(.LCPI61_0)(a0)
997; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
998; RV64-NEXT:    vmulh.vx v8, v8, a0
999; RV64-NEXT:    li a0, 63
1000; RV64-NEXT:    vsrl.vx v10, v8, a0
1001; RV64-NEXT:    vsra.vi v8, v8, 1
1002; RV64-NEXT:    vadd.vv v8, v8, v10
1003; RV64-NEXT:    ret
1004  %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
1005  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
1006  %vc = sdiv <vscale x 2 x i64> %va, %splat
1007  ret <vscale x 2 x i64> %vc
1008}
1009
1010define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
1011; CHECK-LABEL: vdiv_vv_nxv4i64:
1012; CHECK:       # %bb.0:
1013; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1014; CHECK-NEXT:    vdiv.vv v8, v8, v12
1015; CHECK-NEXT:    ret
1016  %vc = sdiv <vscale x 4 x i64> %va, %vb
1017  ret <vscale x 4 x i64> %vc
1018}
1019
1020define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
1021; RV32-LABEL: vdiv_vx_nxv4i64:
1022; RV32:       # %bb.0:
1023; RV32-NEXT:    addi sp, sp, -16
1024; RV32-NEXT:    .cfi_def_cfa_offset 16
1025; RV32-NEXT:    sw a1, 12(sp)
1026; RV32-NEXT:    sw a0, 8(sp)
1027; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1028; RV32-NEXT:    addi a0, sp, 8
1029; RV32-NEXT:    vlse64.v v12, (a0), zero
1030; RV32-NEXT:    vdiv.vv v8, v8, v12
1031; RV32-NEXT:    addi sp, sp, 16
1032; RV32-NEXT:    ret
1033;
1034; RV64-LABEL: vdiv_vx_nxv4i64:
1035; RV64:       # %bb.0:
1036; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1037; RV64-NEXT:    vdiv.vx v8, v8, a0
1038; RV64-NEXT:    ret
1039  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
1040  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
1041  %vc = sdiv <vscale x 4 x i64> %va, %splat
1042  ret <vscale x 4 x i64> %vc
1043}
1044
1045define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
1046; RV32-LABEL: vdiv_vi_nxv4i64_0:
1047; RV32:       # %bb.0:
1048; RV32-NEXT:    addi sp, sp, -16
1049; RV32-NEXT:    .cfi_def_cfa_offset 16
1050; RV32-NEXT:    lui a0, 748983
1051; RV32-NEXT:    addi a0, a0, -586
1052; RV32-NEXT:    sw a0, 12(sp)
1053; RV32-NEXT:    lui a0, 898779
1054; RV32-NEXT:    addi a0, a0, 1755
1055; RV32-NEXT:    sw a0, 8(sp)
1056; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1057; RV32-NEXT:    addi a0, sp, 8
1058; RV32-NEXT:    vlse64.v v12, (a0), zero
1059; RV32-NEXT:    vmulh.vv v8, v8, v12
1060; RV32-NEXT:    li a0, 63
1061; RV32-NEXT:    vsrl.vx v12, v8, a0
1062; RV32-NEXT:    vsra.vi v8, v8, 1
1063; RV32-NEXT:    vadd.vv v8, v8, v12
1064; RV32-NEXT:    addi sp, sp, 16
1065; RV32-NEXT:    ret
1066;
1067; RV64-LABEL: vdiv_vi_nxv4i64_0:
1068; RV64:       # %bb.0:
1069; RV64-NEXT:    lui a0, %hi(.LCPI64_0)
1070; RV64-NEXT:    ld a0, %lo(.LCPI64_0)(a0)
1071; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1072; RV64-NEXT:    vmulh.vx v8, v8, a0
1073; RV64-NEXT:    li a0, 63
1074; RV64-NEXT:    vsrl.vx v12, v8, a0
1075; RV64-NEXT:    vsra.vi v8, v8, 1
1076; RV64-NEXT:    vadd.vv v8, v8, v12
1077; RV64-NEXT:    ret
1078  %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
1079  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
1080  %vc = sdiv <vscale x 4 x i64> %va, %splat
1081  ret <vscale x 4 x i64> %vc
1082}
1083
1084define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1085; CHECK-LABEL: vdiv_vv_nxv8i64:
1086; CHECK:       # %bb.0:
1087; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1088; CHECK-NEXT:    vdiv.vv v8, v8, v16
1089; CHECK-NEXT:    ret
1090  %vc = sdiv <vscale x 8 x i64> %va, %vb
1091  ret <vscale x 8 x i64> %vc
1092}
1093
1094define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
1095; RV32-LABEL: vdiv_vx_nxv8i64:
1096; RV32:       # %bb.0:
1097; RV32-NEXT:    addi sp, sp, -16
1098; RV32-NEXT:    .cfi_def_cfa_offset 16
1099; RV32-NEXT:    sw a1, 12(sp)
1100; RV32-NEXT:    sw a0, 8(sp)
1101; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1102; RV32-NEXT:    addi a0, sp, 8
1103; RV32-NEXT:    vlse64.v v16, (a0), zero
1104; RV32-NEXT:    vdiv.vv v8, v8, v16
1105; RV32-NEXT:    addi sp, sp, 16
1106; RV32-NEXT:    ret
1107;
1108; RV64-LABEL: vdiv_vx_nxv8i64:
1109; RV64:       # %bb.0:
1110; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1111; RV64-NEXT:    vdiv.vx v8, v8, a0
1112; RV64-NEXT:    ret
1113  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
1114  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
1115  %vc = sdiv <vscale x 8 x i64> %va, %splat
1116  ret <vscale x 8 x i64> %vc
1117}
1118
1119define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
1120; RV32-LABEL: vdiv_vi_nxv8i64_0:
1121; RV32:       # %bb.0:
1122; RV32-NEXT:    addi sp, sp, -16
1123; RV32-NEXT:    .cfi_def_cfa_offset 16
1124; RV32-NEXT:    lui a0, 748983
1125; RV32-NEXT:    addi a0, a0, -586
1126; RV32-NEXT:    sw a0, 12(sp)
1127; RV32-NEXT:    lui a0, 898779
1128; RV32-NEXT:    addi a0, a0, 1755
1129; RV32-NEXT:    sw a0, 8(sp)
1130; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1131; RV32-NEXT:    addi a0, sp, 8
1132; RV32-NEXT:    vlse64.v v16, (a0), zero
1133; RV32-NEXT:    vmulh.vv v8, v8, v16
1134; RV32-NEXT:    li a0, 63
1135; RV32-NEXT:    vsrl.vx v16, v8, a0
1136; RV32-NEXT:    vsra.vi v8, v8, 1
1137; RV32-NEXT:    vadd.vv v8, v8, v16
1138; RV32-NEXT:    addi sp, sp, 16
1139; RV32-NEXT:    ret
1140;
1141; RV64-LABEL: vdiv_vi_nxv8i64_0:
1142; RV64:       # %bb.0:
1143; RV64-NEXT:    lui a0, %hi(.LCPI67_0)
1144; RV64-NEXT:    ld a0, %lo(.LCPI67_0)(a0)
1145; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1146; RV64-NEXT:    vmulh.vx v8, v8, a0
1147; RV64-NEXT:    li a0, 63
1148; RV64-NEXT:    vsrl.vx v16, v8, a0
1149; RV64-NEXT:    vsra.vi v8, v8, 1
1150; RV64-NEXT:    vadd.vv v8, v8, v16
1151; RV64-NEXT:    ret
1152  %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
1153  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
1154  %vc = sdiv <vscale x 8 x i64> %va, %splat
1155  ret <vscale x 8 x i64> %vc
1156}
1157
1158