1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V
3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V
5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X
6
7define <vscale x 1 x i8> @vdiv_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
8; CHECK-LABEL: vdiv_vv_nxv1i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
11; CHECK-NEXT:    vdiv.vv v8, v8, v9
12; CHECK-NEXT:    ret
13  %vc = sdiv <vscale x 1 x i8> %va, %vb
14  ret <vscale x 1 x i8> %vc
15}
16
17define <vscale x 1 x i8> @vdiv_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
18; CHECK-LABEL: vdiv_vx_nxv1i8:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
21; CHECK-NEXT:    vdiv.vx v8, v8, a0
22; CHECK-NEXT:    ret
23  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
24  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
25  %vc = sdiv <vscale x 1 x i8> %va, %splat
26  ret <vscale x 1 x i8> %vc
27}
28
29define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
30; CHECK-LABEL: vdiv_vi_nxv1i8_0:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    li a0, 109
33; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
34; CHECK-NEXT:    vmulh.vx v9, v8, a0
35; CHECK-NEXT:    vsub.vv v8, v9, v8
36; CHECK-NEXT:    vsra.vi v8, v8, 2
37; CHECK-NEXT:    vsrl.vi v9, v8, 7
38; CHECK-NEXT:    vadd.vv v8, v8, v9
39; CHECK-NEXT:    ret
40  %head = insertelement <vscale x 1 x i8> poison, i8 -7, i32 0
41  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
42  %vc = sdiv <vscale x 1 x i8> %va, %splat
43  ret <vscale x 1 x i8> %vc
44}
45
46; Test V/1 to see if we can optimize it away for scalable vectors.
47define <vscale x 1 x i8> @vdiv_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
48; CHECK-LABEL: vdiv_vi_nxv1i8_1:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    ret
51  %head = insertelement <vscale x 1 x i8> poison, i8 1, i32 0
52  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
53  %vc = sdiv <vscale x 1 x i8> %va, %splat
54  ret <vscale x 1 x i8> %vc
55}
56
57; Test 0/V to see if we can optimize it away for scalable vectors.
58define <vscale x 1 x i8> @vdiv_iv_nxv1i8_0(<vscale x 1 x i8> %va) {
59; CHECK-LABEL: vdiv_iv_nxv1i8_0:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
62; CHECK-NEXT:    vmv.v.i v8, 0
63; CHECK-NEXT:    ret
64  %head = insertelement <vscale x 1 x i8> poison, i8 0, i32 0
65  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
66  %vc = sdiv <vscale x 1 x i8> %splat, %va
67  ret <vscale x 1 x i8> %vc
68}
69
70define <vscale x 2 x i8> @vdiv_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
71; CHECK-LABEL: vdiv_vv_nxv2i8:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
74; CHECK-NEXT:    vdiv.vv v8, v8, v9
75; CHECK-NEXT:    ret
76  %vc = sdiv <vscale x 2 x i8> %va, %vb
77  ret <vscale x 2 x i8> %vc
78}
79
80define <vscale x 2 x i8> @vdiv_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
81; CHECK-LABEL: vdiv_vx_nxv2i8:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
84; CHECK-NEXT:    vdiv.vx v8, v8, a0
85; CHECK-NEXT:    ret
86  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
87  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
88  %vc = sdiv <vscale x 2 x i8> %va, %splat
89  ret <vscale x 2 x i8> %vc
90}
91
92define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
93; CHECK-LABEL: vdiv_vi_nxv2i8_0:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    li a0, 109
96; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
97; CHECK-NEXT:    vmulh.vx v9, v8, a0
98; CHECK-NEXT:    vsub.vv v8, v9, v8
99; CHECK-NEXT:    vsra.vi v8, v8, 2
100; CHECK-NEXT:    vsrl.vi v9, v8, 7
101; CHECK-NEXT:    vadd.vv v8, v8, v9
102; CHECK-NEXT:    ret
103  %head = insertelement <vscale x 2 x i8> poison, i8 -7, i32 0
104  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
105  %vc = sdiv <vscale x 2 x i8> %va, %splat
106  ret <vscale x 2 x i8> %vc
107}
108
109define <vscale x 4 x i8> @vdiv_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
110; CHECK-LABEL: vdiv_vv_nxv4i8:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
113; CHECK-NEXT:    vdiv.vv v8, v8, v9
114; CHECK-NEXT:    ret
115  %vc = sdiv <vscale x 4 x i8> %va, %vb
116  ret <vscale x 4 x i8> %vc
117}
118
119define <vscale x 4 x i8> @vdiv_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
120; CHECK-LABEL: vdiv_vx_nxv4i8:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
123; CHECK-NEXT:    vdiv.vx v8, v8, a0
124; CHECK-NEXT:    ret
125  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
126  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
127  %vc = sdiv <vscale x 4 x i8> %va, %splat
128  ret <vscale x 4 x i8> %vc
129}
130
131define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
132; CHECK-LABEL: vdiv_vi_nxv4i8_0:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    li a0, 109
135; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
136; CHECK-NEXT:    vmulh.vx v9, v8, a0
137; CHECK-NEXT:    vsub.vv v8, v9, v8
138; CHECK-NEXT:    vsra.vi v8, v8, 2
139; CHECK-NEXT:    vsrl.vi v9, v8, 7
140; CHECK-NEXT:    vadd.vv v8, v8, v9
141; CHECK-NEXT:    ret
142  %head = insertelement <vscale x 4 x i8> poison, i8 -7, i32 0
143  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
144  %vc = sdiv <vscale x 4 x i8> %va, %splat
145  ret <vscale x 4 x i8> %vc
146}
147
148define <vscale x 8 x i8> @vdiv_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
149; CHECK-LABEL: vdiv_vv_nxv8i8:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
152; CHECK-NEXT:    vdiv.vv v8, v8, v9
153; CHECK-NEXT:    ret
154  %vc = sdiv <vscale x 8 x i8> %va, %vb
155  ret <vscale x 8 x i8> %vc
156}
157
158define <vscale x 8 x i8> @vdiv_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
159; CHECK-LABEL: vdiv_vx_nxv8i8:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
162; CHECK-NEXT:    vdiv.vx v8, v8, a0
163; CHECK-NEXT:    ret
164  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
165  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
166  %vc = sdiv <vscale x 8 x i8> %va, %splat
167  ret <vscale x 8 x i8> %vc
168}
169
170define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
171; CHECK-LABEL: vdiv_vi_nxv8i8_0:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    li a0, 109
174; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
175; CHECK-NEXT:    vmulh.vx v9, v8, a0
176; CHECK-NEXT:    vsub.vv v8, v9, v8
177; CHECK-NEXT:    vsra.vi v8, v8, 2
178; CHECK-NEXT:    vsrl.vi v9, v8, 7
179; CHECK-NEXT:    vadd.vv v8, v8, v9
180; CHECK-NEXT:    ret
181  %head = insertelement <vscale x 8 x i8> poison, i8 -7, i32 0
182  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
183  %vc = sdiv <vscale x 8 x i8> %va, %splat
184  ret <vscale x 8 x i8> %vc
185}
186
187define <vscale x 16 x i8> @vdiv_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
188; CHECK-LABEL: vdiv_vv_nxv16i8:
189; CHECK:       # %bb.0:
190; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
191; CHECK-NEXT:    vdiv.vv v8, v8, v10
192; CHECK-NEXT:    ret
193  %vc = sdiv <vscale x 16 x i8> %va, %vb
194  ret <vscale x 16 x i8> %vc
195}
196
197define <vscale x 16 x i8> @vdiv_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
198; CHECK-LABEL: vdiv_vx_nxv16i8:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
201; CHECK-NEXT:    vdiv.vx v8, v8, a0
202; CHECK-NEXT:    ret
203  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
204  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
205  %vc = sdiv <vscale x 16 x i8> %va, %splat
206  ret <vscale x 16 x i8> %vc
207}
208
209define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
210; CHECK-LABEL: vdiv_vi_nxv16i8_0:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    li a0, 109
213; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
214; CHECK-NEXT:    vmulh.vx v10, v8, a0
215; CHECK-NEXT:    vsub.vv v8, v10, v8
216; CHECK-NEXT:    vsra.vi v8, v8, 2
217; CHECK-NEXT:    vsrl.vi v10, v8, 7
218; CHECK-NEXT:    vadd.vv v8, v8, v10
219; CHECK-NEXT:    ret
220  %head = insertelement <vscale x 16 x i8> poison, i8 -7, i32 0
221  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
222  %vc = sdiv <vscale x 16 x i8> %va, %splat
223  ret <vscale x 16 x i8> %vc
224}
225
226define <vscale x 32 x i8> @vdiv_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
227; CHECK-LABEL: vdiv_vv_nxv32i8:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
230; CHECK-NEXT:    vdiv.vv v8, v8, v12
231; CHECK-NEXT:    ret
232  %vc = sdiv <vscale x 32 x i8> %va, %vb
233  ret <vscale x 32 x i8> %vc
234}
235
236define <vscale x 32 x i8> @vdiv_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
237; CHECK-LABEL: vdiv_vx_nxv32i8:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
240; CHECK-NEXT:    vdiv.vx v8, v8, a0
241; CHECK-NEXT:    ret
242  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
243  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
244  %vc = sdiv <vscale x 32 x i8> %va, %splat
245  ret <vscale x 32 x i8> %vc
246}
247
248define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
249; CHECK-LABEL: vdiv_vi_nxv32i8_0:
250; CHECK:       # %bb.0:
251; CHECK-NEXT:    li a0, 109
252; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
253; CHECK-NEXT:    vmulh.vx v12, v8, a0
254; CHECK-NEXT:    vsub.vv v8, v12, v8
255; CHECK-NEXT:    vsra.vi v8, v8, 2
256; CHECK-NEXT:    vsrl.vi v12, v8, 7
257; CHECK-NEXT:    vadd.vv v8, v8, v12
258; CHECK-NEXT:    ret
259  %head = insertelement <vscale x 32 x i8> poison, i8 -7, i32 0
260  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
261  %vc = sdiv <vscale x 32 x i8> %va, %splat
262  ret <vscale x 32 x i8> %vc
263}
264
265define <vscale x 64 x i8> @vdiv_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
266; CHECK-LABEL: vdiv_vv_nxv64i8:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
269; CHECK-NEXT:    vdiv.vv v8, v8, v16
270; CHECK-NEXT:    ret
271  %vc = sdiv <vscale x 64 x i8> %va, %vb
272  ret <vscale x 64 x i8> %vc
273}
274
275define <vscale x 64 x i8> @vdiv_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
276; CHECK-LABEL: vdiv_vx_nxv64i8:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
279; CHECK-NEXT:    vdiv.vx v8, v8, a0
280; CHECK-NEXT:    ret
281  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
282  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
283  %vc = sdiv <vscale x 64 x i8> %va, %splat
284  ret <vscale x 64 x i8> %vc
285}
286
287define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
288; CHECK-LABEL: vdiv_vi_nxv64i8_0:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    li a0, 109
291; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
292; CHECK-NEXT:    vmulh.vx v16, v8, a0
293; CHECK-NEXT:    vsub.vv v8, v16, v8
294; CHECK-NEXT:    vsra.vi v8, v8, 2
295; CHECK-NEXT:    vsrl.vi v16, v8, 7
296; CHECK-NEXT:    vadd.vv v8, v8, v16
297; CHECK-NEXT:    ret
298  %head = insertelement <vscale x 64 x i8> poison, i8 -7, i32 0
299  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
300  %vc = sdiv <vscale x 64 x i8> %va, %splat
301  ret <vscale x 64 x i8> %vc
302}
303
304define <vscale x 1 x i16> @vdiv_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
305; CHECK-LABEL: vdiv_vv_nxv1i16:
306; CHECK:       # %bb.0:
307; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
308; CHECK-NEXT:    vdiv.vv v8, v8, v9
309; CHECK-NEXT:    ret
310  %vc = sdiv <vscale x 1 x i16> %va, %vb
311  ret <vscale x 1 x i16> %vc
312}
313
314define <vscale x 1 x i16> @vdiv_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
315; CHECK-LABEL: vdiv_vx_nxv1i16:
316; CHECK:       # %bb.0:
317; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
318; CHECK-NEXT:    vdiv.vx v8, v8, a0
319; CHECK-NEXT:    ret
320  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
321  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
322  %vc = sdiv <vscale x 1 x i16> %va, %splat
323  ret <vscale x 1 x i16> %vc
324}
325
326define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
327; RV32-LABEL: vdiv_vi_nxv1i16_0:
328; RV32:       # %bb.0:
329; RV32-NEXT:    lui a0, 1048571
330; RV32-NEXT:    addi a0, a0, 1755
331; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
332; RV32-NEXT:    vmulh.vx v8, v8, a0
333; RV32-NEXT:    vsra.vi v8, v8, 1
334; RV32-NEXT:    vsrl.vi v9, v8, 15
335; RV32-NEXT:    vadd.vv v8, v8, v9
336; RV32-NEXT:    ret
337;
338; RV64-LABEL: vdiv_vi_nxv1i16_0:
339; RV64:       # %bb.0:
340; RV64-NEXT:    lui a0, 1048571
341; RV64-NEXT:    addiw a0, a0, 1755
342; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
343; RV64-NEXT:    vmulh.vx v8, v8, a0
344; RV64-NEXT:    vsra.vi v8, v8, 1
345; RV64-NEXT:    vsrl.vi v9, v8, 15
346; RV64-NEXT:    vadd.vv v8, v8, v9
347; RV64-NEXT:    ret
348  %head = insertelement <vscale x 1 x i16> poison, i16 -7, i32 0
349  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
350  %vc = sdiv <vscale x 1 x i16> %va, %splat
351  ret <vscale x 1 x i16> %vc
352}
353
354define <vscale x 2 x i16> @vdiv_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
355; CHECK-LABEL: vdiv_vv_nxv2i16:
356; CHECK:       # %bb.0:
357; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
358; CHECK-NEXT:    vdiv.vv v8, v8, v9
359; CHECK-NEXT:    ret
360  %vc = sdiv <vscale x 2 x i16> %va, %vb
361  ret <vscale x 2 x i16> %vc
362}
363
364define <vscale x 2 x i16> @vdiv_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
365; CHECK-LABEL: vdiv_vx_nxv2i16:
366; CHECK:       # %bb.0:
367; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
368; CHECK-NEXT:    vdiv.vx v8, v8, a0
369; CHECK-NEXT:    ret
370  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
371  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
372  %vc = sdiv <vscale x 2 x i16> %va, %splat
373  ret <vscale x 2 x i16> %vc
374}
375
376define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
377; RV32-LABEL: vdiv_vi_nxv2i16_0:
378; RV32:       # %bb.0:
379; RV32-NEXT:    lui a0, 1048571
380; RV32-NEXT:    addi a0, a0, 1755
381; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
382; RV32-NEXT:    vmulh.vx v8, v8, a0
383; RV32-NEXT:    vsra.vi v8, v8, 1
384; RV32-NEXT:    vsrl.vi v9, v8, 15
385; RV32-NEXT:    vadd.vv v8, v8, v9
386; RV32-NEXT:    ret
387;
388; RV64-LABEL: vdiv_vi_nxv2i16_0:
389; RV64:       # %bb.0:
390; RV64-NEXT:    lui a0, 1048571
391; RV64-NEXT:    addiw a0, a0, 1755
392; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
393; RV64-NEXT:    vmulh.vx v8, v8, a0
394; RV64-NEXT:    vsra.vi v8, v8, 1
395; RV64-NEXT:    vsrl.vi v9, v8, 15
396; RV64-NEXT:    vadd.vv v8, v8, v9
397; RV64-NEXT:    ret
398  %head = insertelement <vscale x 2 x i16> poison, i16 -7, i32 0
399  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
400  %vc = sdiv <vscale x 2 x i16> %va, %splat
401  ret <vscale x 2 x i16> %vc
402}
403
404define <vscale x 4 x i16> @vdiv_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
405; CHECK-LABEL: vdiv_vv_nxv4i16:
406; CHECK:       # %bb.0:
407; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
408; CHECK-NEXT:    vdiv.vv v8, v8, v9
409; CHECK-NEXT:    ret
410  %vc = sdiv <vscale x 4 x i16> %va, %vb
411  ret <vscale x 4 x i16> %vc
412}
413
414define <vscale x 4 x i16> @vdiv_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
415; CHECK-LABEL: vdiv_vx_nxv4i16:
416; CHECK:       # %bb.0:
417; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
418; CHECK-NEXT:    vdiv.vx v8, v8, a0
419; CHECK-NEXT:    ret
420  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
421  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
422  %vc = sdiv <vscale x 4 x i16> %va, %splat
423  ret <vscale x 4 x i16> %vc
424}
425
426define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
427; RV32-LABEL: vdiv_vi_nxv4i16_0:
428; RV32:       # %bb.0:
429; RV32-NEXT:    lui a0, 1048571
430; RV32-NEXT:    addi a0, a0, 1755
431; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
432; RV32-NEXT:    vmulh.vx v8, v8, a0
433; RV32-NEXT:    vsra.vi v8, v8, 1
434; RV32-NEXT:    vsrl.vi v9, v8, 15
435; RV32-NEXT:    vadd.vv v8, v8, v9
436; RV32-NEXT:    ret
437;
438; RV64-LABEL: vdiv_vi_nxv4i16_0:
439; RV64:       # %bb.0:
440; RV64-NEXT:    lui a0, 1048571
441; RV64-NEXT:    addiw a0, a0, 1755
442; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
443; RV64-NEXT:    vmulh.vx v8, v8, a0
444; RV64-NEXT:    vsra.vi v8, v8, 1
445; RV64-NEXT:    vsrl.vi v9, v8, 15
446; RV64-NEXT:    vadd.vv v8, v8, v9
447; RV64-NEXT:    ret
448  %head = insertelement <vscale x 4 x i16> poison, i16 -7, i32 0
449  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
450  %vc = sdiv <vscale x 4 x i16> %va, %splat
451  ret <vscale x 4 x i16> %vc
452}
453
454define <vscale x 8 x i16> @vdiv_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
455; CHECK-LABEL: vdiv_vv_nxv8i16:
456; CHECK:       # %bb.0:
457; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
458; CHECK-NEXT:    vdiv.vv v8, v8, v10
459; CHECK-NEXT:    ret
460  %vc = sdiv <vscale x 8 x i16> %va, %vb
461  ret <vscale x 8 x i16> %vc
462}
463
464define <vscale x 8 x i16> @vdiv_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
465; CHECK-LABEL: vdiv_vx_nxv8i16:
466; CHECK:       # %bb.0:
467; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
468; CHECK-NEXT:    vdiv.vx v8, v8, a0
469; CHECK-NEXT:    ret
470  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
471  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
472  %vc = sdiv <vscale x 8 x i16> %va, %splat
473  ret <vscale x 8 x i16> %vc
474}
475
476define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
477; RV32-LABEL: vdiv_vi_nxv8i16_0:
478; RV32:       # %bb.0:
479; RV32-NEXT:    lui a0, 1048571
480; RV32-NEXT:    addi a0, a0, 1755
481; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
482; RV32-NEXT:    vmulh.vx v8, v8, a0
483; RV32-NEXT:    vsra.vi v8, v8, 1
484; RV32-NEXT:    vsrl.vi v10, v8, 15
485; RV32-NEXT:    vadd.vv v8, v8, v10
486; RV32-NEXT:    ret
487;
488; RV64-LABEL: vdiv_vi_nxv8i16_0:
489; RV64:       # %bb.0:
490; RV64-NEXT:    lui a0, 1048571
491; RV64-NEXT:    addiw a0, a0, 1755
492; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
493; RV64-NEXT:    vmulh.vx v8, v8, a0
494; RV64-NEXT:    vsra.vi v8, v8, 1
495; RV64-NEXT:    vsrl.vi v10, v8, 15
496; RV64-NEXT:    vadd.vv v8, v8, v10
497; RV64-NEXT:    ret
498  %head = insertelement <vscale x 8 x i16> poison, i16 -7, i32 0
499  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
500  %vc = sdiv <vscale x 8 x i16> %va, %splat
501  ret <vscale x 8 x i16> %vc
502}
503
504define <vscale x 16 x i16> @vdiv_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
505; CHECK-LABEL: vdiv_vv_nxv16i16:
506; CHECK:       # %bb.0:
507; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
508; CHECK-NEXT:    vdiv.vv v8, v8, v12
509; CHECK-NEXT:    ret
510  %vc = sdiv <vscale x 16 x i16> %va, %vb
511  ret <vscale x 16 x i16> %vc
512}
513
514define <vscale x 16 x i16> @vdiv_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
515; CHECK-LABEL: vdiv_vx_nxv16i16:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
518; CHECK-NEXT:    vdiv.vx v8, v8, a0
519; CHECK-NEXT:    ret
520  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
521  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
522  %vc = sdiv <vscale x 16 x i16> %va, %splat
523  ret <vscale x 16 x i16> %vc
524}
525
526define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
527; RV32-LABEL: vdiv_vi_nxv16i16_0:
528; RV32:       # %bb.0:
529; RV32-NEXT:    lui a0, 1048571
530; RV32-NEXT:    addi a0, a0, 1755
531; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
532; RV32-NEXT:    vmulh.vx v8, v8, a0
533; RV32-NEXT:    vsra.vi v8, v8, 1
534; RV32-NEXT:    vsrl.vi v12, v8, 15
535; RV32-NEXT:    vadd.vv v8, v8, v12
536; RV32-NEXT:    ret
537;
538; RV64-LABEL: vdiv_vi_nxv16i16_0:
539; RV64:       # %bb.0:
540; RV64-NEXT:    lui a0, 1048571
541; RV64-NEXT:    addiw a0, a0, 1755
542; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
543; RV64-NEXT:    vmulh.vx v8, v8, a0
544; RV64-NEXT:    vsra.vi v8, v8, 1
545; RV64-NEXT:    vsrl.vi v12, v8, 15
546; RV64-NEXT:    vadd.vv v8, v8, v12
547; RV64-NEXT:    ret
548  %head = insertelement <vscale x 16 x i16> poison, i16 -7, i32 0
549  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
550  %vc = sdiv <vscale x 16 x i16> %va, %splat
551  ret <vscale x 16 x i16> %vc
552}
553
554define <vscale x 32 x i16> @vdiv_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
555; CHECK-LABEL: vdiv_vv_nxv32i16:
556; CHECK:       # %bb.0:
557; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
558; CHECK-NEXT:    vdiv.vv v8, v8, v16
559; CHECK-NEXT:    ret
560  %vc = sdiv <vscale x 32 x i16> %va, %vb
561  ret <vscale x 32 x i16> %vc
562}
563
564define <vscale x 32 x i16> @vdiv_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
565; CHECK-LABEL: vdiv_vx_nxv32i16:
566; CHECK:       # %bb.0:
567; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
568; CHECK-NEXT:    vdiv.vx v8, v8, a0
569; CHECK-NEXT:    ret
570  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
571  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
572  %vc = sdiv <vscale x 32 x i16> %va, %splat
573  ret <vscale x 32 x i16> %vc
574}
575
576define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
577; RV32-LABEL: vdiv_vi_nxv32i16_0:
578; RV32:       # %bb.0:
579; RV32-NEXT:    lui a0, 1048571
580; RV32-NEXT:    addi a0, a0, 1755
581; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
582; RV32-NEXT:    vmulh.vx v8, v8, a0
583; RV32-NEXT:    vsra.vi v8, v8, 1
584; RV32-NEXT:    vsrl.vi v16, v8, 15
585; RV32-NEXT:    vadd.vv v8, v8, v16
586; RV32-NEXT:    ret
587;
588; RV64-LABEL: vdiv_vi_nxv32i16_0:
589; RV64:       # %bb.0:
590; RV64-NEXT:    lui a0, 1048571
591; RV64-NEXT:    addiw a0, a0, 1755
592; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
593; RV64-NEXT:    vmulh.vx v8, v8, a0
594; RV64-NEXT:    vsra.vi v8, v8, 1
595; RV64-NEXT:    vsrl.vi v16, v8, 15
596; RV64-NEXT:    vadd.vv v8, v8, v16
597; RV64-NEXT:    ret
598  %head = insertelement <vscale x 32 x i16> poison, i16 -7, i32 0
599  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
600  %vc = sdiv <vscale x 32 x i16> %va, %splat
601  ret <vscale x 32 x i16> %vc
602}
603
604define <vscale x 1 x i32> @vdiv_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
605; CHECK-LABEL: vdiv_vv_nxv1i32:
606; CHECK:       # %bb.0:
607; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
608; CHECK-NEXT:    vdiv.vv v8, v8, v9
609; CHECK-NEXT:    ret
610  %vc = sdiv <vscale x 1 x i32> %va, %vb
611  ret <vscale x 1 x i32> %vc
612}
613
614define <vscale x 1 x i32> @vdiv_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
615; CHECK-LABEL: vdiv_vx_nxv1i32:
616; CHECK:       # %bb.0:
617; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
618; CHECK-NEXT:    vdiv.vx v8, v8, a0
619; CHECK-NEXT:    ret
620  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
621  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
622  %vc = sdiv <vscale x 1 x i32> %va, %splat
623  ret <vscale x 1 x i32> %vc
624}
625
626define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
627; RV32-LABEL: vdiv_vi_nxv1i32_0:
628; RV32:       # %bb.0:
629; RV32-NEXT:    lui a0, 449390
630; RV32-NEXT:    addi a0, a0, -1171
631; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
632; RV32-NEXT:    vmulh.vx v9, v8, a0
633; RV32-NEXT:    vsub.vv v8, v9, v8
634; RV32-NEXT:    vsrl.vi v9, v8, 31
635; RV32-NEXT:    vsra.vi v8, v8, 2
636; RV32-NEXT:    vadd.vv v8, v8, v9
637; RV32-NEXT:    ret
638;
639; RV64-LABEL: vdiv_vi_nxv1i32_0:
640; RV64:       # %bb.0:
641; RV64-NEXT:    lui a0, 449390
642; RV64-NEXT:    addiw a0, a0, -1171
643; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
644; RV64-NEXT:    vmulh.vx v9, v8, a0
645; RV64-NEXT:    vsub.vv v8, v9, v8
646; RV64-NEXT:    vsra.vi v8, v8, 2
647; RV64-NEXT:    vsrl.vi v9, v8, 31
648; RV64-NEXT:    vadd.vv v8, v8, v9
649; RV64-NEXT:    ret
650  %head = insertelement <vscale x 1 x i32> poison, i32 -7, i32 0
651  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
652  %vc = sdiv <vscale x 1 x i32> %va, %splat
653  ret <vscale x 1 x i32> %vc
654}
655
656define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
657; CHECK-LABEL: vdiv_vv_nxv2i32:
658; CHECK:       # %bb.0:
659; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
660; CHECK-NEXT:    vdiv.vv v8, v8, v9
661; CHECK-NEXT:    ret
662  %vc = sdiv <vscale x 2 x i32> %va, %vb
663  ret <vscale x 2 x i32> %vc
664}
665
666define <vscale x 2 x i32> @vdiv_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
667; CHECK-LABEL: vdiv_vx_nxv2i32:
668; CHECK:       # %bb.0:
669; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
670; CHECK-NEXT:    vdiv.vx v8, v8, a0
671; CHECK-NEXT:    ret
672  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
673  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
674  %vc = sdiv <vscale x 2 x i32> %va, %splat
675  ret <vscale x 2 x i32> %vc
676}
677
678define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
679; RV32-LABEL: vdiv_vi_nxv2i32_0:
680; RV32:       # %bb.0:
681; RV32-NEXT:    lui a0, 449390
682; RV32-NEXT:    addi a0, a0, -1171
683; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
684; RV32-NEXT:    vmulh.vx v9, v8, a0
685; RV32-NEXT:    vsub.vv v8, v9, v8
686; RV32-NEXT:    vsrl.vi v9, v8, 31
687; RV32-NEXT:    vsra.vi v8, v8, 2
688; RV32-NEXT:    vadd.vv v8, v8, v9
689; RV32-NEXT:    ret
690;
691; RV64-LABEL: vdiv_vi_nxv2i32_0:
692; RV64:       # %bb.0:
693; RV64-NEXT:    lui a0, 449390
694; RV64-NEXT:    addiw a0, a0, -1171
695; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
696; RV64-NEXT:    vmulh.vx v9, v8, a0
697; RV64-NEXT:    vsub.vv v8, v9, v8
698; RV64-NEXT:    vsra.vi v8, v8, 2
699; RV64-NEXT:    vsrl.vi v9, v8, 31
700; RV64-NEXT:    vadd.vv v8, v8, v9
701; RV64-NEXT:    ret
702  %head = insertelement <vscale x 2 x i32> poison, i32 -7, i32 0
703  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
704  %vc = sdiv <vscale x 2 x i32> %va, %splat
705  ret <vscale x 2 x i32> %vc
706}
707
708define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
709; CHECK-LABEL: vdiv_vv_nxv4i32:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
712; CHECK-NEXT:    vdiv.vv v8, v8, v10
713; CHECK-NEXT:    ret
714  %vc = sdiv <vscale x 4 x i32> %va, %vb
715  ret <vscale x 4 x i32> %vc
716}
717
718define <vscale x 4 x i32> @vdiv_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
719; CHECK-LABEL: vdiv_vx_nxv4i32:
720; CHECK:       # %bb.0:
721; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
722; CHECK-NEXT:    vdiv.vx v8, v8, a0
723; CHECK-NEXT:    ret
724  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
725  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
726  %vc = sdiv <vscale x 4 x i32> %va, %splat
727  ret <vscale x 4 x i32> %vc
728}
729
730define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
731; RV32-LABEL: vdiv_vi_nxv4i32_0:
732; RV32:       # %bb.0:
733; RV32-NEXT:    lui a0, 449390
734; RV32-NEXT:    addi a0, a0, -1171
735; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
736; RV32-NEXT:    vmulh.vx v10, v8, a0
737; RV32-NEXT:    vsub.vv v8, v10, v8
738; RV32-NEXT:    vsrl.vi v10, v8, 31
739; RV32-NEXT:    vsra.vi v8, v8, 2
740; RV32-NEXT:    vadd.vv v8, v8, v10
741; RV32-NEXT:    ret
742;
743; RV64-LABEL: vdiv_vi_nxv4i32_0:
744; RV64:       # %bb.0:
745; RV64-NEXT:    lui a0, 449390
746; RV64-NEXT:    addiw a0, a0, -1171
747; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
748; RV64-NEXT:    vmulh.vx v10, v8, a0
749; RV64-NEXT:    vsub.vv v8, v10, v8
750; RV64-NEXT:    vsra.vi v8, v8, 2
751; RV64-NEXT:    vsrl.vi v10, v8, 31
752; RV64-NEXT:    vadd.vv v8, v8, v10
753; RV64-NEXT:    ret
754  %head = insertelement <vscale x 4 x i32> poison, i32 -7, i32 0
755  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
756  %vc = sdiv <vscale x 4 x i32> %va, %splat
757  ret <vscale x 4 x i32> %vc
758}
759
760define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
761; CHECK-LABEL: vdiv_vv_nxv8i32:
762; CHECK:       # %bb.0:
763; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
764; CHECK-NEXT:    vdiv.vv v8, v8, v12
765; CHECK-NEXT:    ret
766  %vc = sdiv <vscale x 8 x i32> %va, %vb
767  ret <vscale x 8 x i32> %vc
768}
769
770define <vscale x 8 x i32> @vdiv_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
771; CHECK-LABEL: vdiv_vx_nxv8i32:
772; CHECK:       # %bb.0:
773; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
774; CHECK-NEXT:    vdiv.vx v8, v8, a0
775; CHECK-NEXT:    ret
776  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
777  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
778  %vc = sdiv <vscale x 8 x i32> %va, %splat
779  ret <vscale x 8 x i32> %vc
780}
781
782define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
783; RV32-LABEL: vdiv_vi_nxv8i32_0:
784; RV32:       # %bb.0:
785; RV32-NEXT:    lui a0, 449390
786; RV32-NEXT:    addi a0, a0, -1171
787; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
788; RV32-NEXT:    vmulh.vx v12, v8, a0
789; RV32-NEXT:    vsub.vv v8, v12, v8
790; RV32-NEXT:    vsrl.vi v12, v8, 31
791; RV32-NEXT:    vsra.vi v8, v8, 2
792; RV32-NEXT:    vadd.vv v8, v8, v12
793; RV32-NEXT:    ret
794;
795; RV64-LABEL: vdiv_vi_nxv8i32_0:
796; RV64:       # %bb.0:
797; RV64-NEXT:    lui a0, 449390
798; RV64-NEXT:    addiw a0, a0, -1171
799; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
800; RV64-NEXT:    vmulh.vx v12, v8, a0
801; RV64-NEXT:    vsub.vv v8, v12, v8
802; RV64-NEXT:    vsra.vi v8, v8, 2
803; RV64-NEXT:    vsrl.vi v12, v8, 31
804; RV64-NEXT:    vadd.vv v8, v8, v12
805; RV64-NEXT:    ret
806  %head = insertelement <vscale x 8 x i32> poison, i32 -7, i32 0
807  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
808  %vc = sdiv <vscale x 8 x i32> %va, %splat
809  ret <vscale x 8 x i32> %vc
810}
811
812define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
813; CHECK-LABEL: vdiv_vv_nxv16i32:
814; CHECK:       # %bb.0:
815; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
816; CHECK-NEXT:    vdiv.vv v8, v8, v16
817; CHECK-NEXT:    ret
818  %vc = sdiv <vscale x 16 x i32> %va, %vb
819  ret <vscale x 16 x i32> %vc
820}
821
822define <vscale x 16 x i32> @vdiv_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
823; CHECK-LABEL: vdiv_vx_nxv16i32:
824; CHECK:       # %bb.0:
825; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
826; CHECK-NEXT:    vdiv.vx v8, v8, a0
827; CHECK-NEXT:    ret
828  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
829  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
830  %vc = sdiv <vscale x 16 x i32> %va, %splat
831  ret <vscale x 16 x i32> %vc
832}
833
834define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
835; RV32-LABEL: vdiv_vi_nxv16i32_0:
836; RV32:       # %bb.0:
837; RV32-NEXT:    lui a0, 449390
838; RV32-NEXT:    addi a0, a0, -1171
839; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
840; RV32-NEXT:    vmulh.vx v16, v8, a0
841; RV32-NEXT:    vsub.vv v8, v16, v8
842; RV32-NEXT:    vsrl.vi v16, v8, 31
843; RV32-NEXT:    vsra.vi v8, v8, 2
844; RV32-NEXT:    vadd.vv v8, v8, v16
845; RV32-NEXT:    ret
846;
847; RV64-LABEL: vdiv_vi_nxv16i32_0:
848; RV64:       # %bb.0:
849; RV64-NEXT:    lui a0, 449390
850; RV64-NEXT:    addiw a0, a0, -1171
851; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
852; RV64-NEXT:    vmulh.vx v16, v8, a0
853; RV64-NEXT:    vsub.vv v8, v16, v8
854; RV64-NEXT:    vsra.vi v8, v8, 2
855; RV64-NEXT:    vsrl.vi v16, v8, 31
856; RV64-NEXT:    vadd.vv v8, v8, v16
857; RV64-NEXT:    ret
858  %head = insertelement <vscale x 16 x i32> poison, i32 -7, i32 0
859  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
860  %vc = sdiv <vscale x 16 x i32> %va, %splat
861  ret <vscale x 16 x i32> %vc
862}
863
864define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
865; CHECK-LABEL: vdiv_vv_nxv1i64:
866; CHECK:       # %bb.0:
867; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
868; CHECK-NEXT:    vdiv.vv v8, v8, v9
869; CHECK-NEXT:    ret
870  %vc = sdiv <vscale x 1 x i64> %va, %vb
871  ret <vscale x 1 x i64> %vc
872}
873
874define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
875; RV32-LABEL: vdiv_vx_nxv1i64:
876; RV32:       # %bb.0:
877; RV32-NEXT:    addi sp, sp, -16
878; RV32-NEXT:    .cfi_def_cfa_offset 16
879; RV32-NEXT:    sw a1, 12(sp)
880; RV32-NEXT:    sw a0, 8(sp)
881; RV32-NEXT:    addi a0, sp, 8
882; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
883; RV32-NEXT:    vlse64.v v9, (a0), zero
884; RV32-NEXT:    vdiv.vv v8, v8, v9
885; RV32-NEXT:    addi sp, sp, 16
886; RV32-NEXT:    ret
887;
888; RV64-LABEL: vdiv_vx_nxv1i64:
889; RV64:       # %bb.0:
890; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
891; RV64-NEXT:    vdiv.vx v8, v8, a0
892; RV64-NEXT:    ret
893  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
894  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
895  %vc = sdiv <vscale x 1 x i64> %va, %splat
896  ret <vscale x 1 x i64> %vc
897}
898
899define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
900; RV32-V-LABEL: vdiv_vi_nxv1i64_0:
901; RV32-V:       # %bb.0:
902; RV32-V-NEXT:    addi sp, sp, -16
903; RV32-V-NEXT:    .cfi_def_cfa_offset 16
904; RV32-V-NEXT:    lui a0, 748983
905; RV32-V-NEXT:    addi a0, a0, -586
906; RV32-V-NEXT:    sw a0, 12(sp)
907; RV32-V-NEXT:    lui a0, 898779
908; RV32-V-NEXT:    addi a0, a0, 1755
909; RV32-V-NEXT:    sw a0, 8(sp)
910; RV32-V-NEXT:    addi a0, sp, 8
911; RV32-V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
912; RV32-V-NEXT:    vlse64.v v9, (a0), zero
913; RV32-V-NEXT:    vmulh.vv v8, v8, v9
914; RV32-V-NEXT:    li a0, 63
915; RV32-V-NEXT:    vsrl.vx v9, v8, a0
916; RV32-V-NEXT:    vsra.vi v8, v8, 1
917; RV32-V-NEXT:    vadd.vv v8, v8, v9
918; RV32-V-NEXT:    addi sp, sp, 16
919; RV32-V-NEXT:    ret
920;
921; ZVE64X-LABEL: vdiv_vi_nxv1i64_0:
922; ZVE64X:       # %bb.0:
923; ZVE64X-NEXT:    li a0, -7
924; ZVE64X-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
925; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
926; ZVE64X-NEXT:    ret
927;
928; RV64-V-LABEL: vdiv_vi_nxv1i64_0:
929; RV64-V:       # %bb.0:
930; RV64-V-NEXT:    lui a0, %hi(.LCPI58_0)
931; RV64-V-NEXT:    ld a0, %lo(.LCPI58_0)(a0)
932; RV64-V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
933; RV64-V-NEXT:    vmulh.vx v8, v8, a0
934; RV64-V-NEXT:    li a0, 63
935; RV64-V-NEXT:    vsrl.vx v9, v8, a0
936; RV64-V-NEXT:    vsra.vi v8, v8, 1
937; RV64-V-NEXT:    vadd.vv v8, v8, v9
938; RV64-V-NEXT:    ret
939  %head = insertelement <vscale x 1 x i64> poison, i64 -7, i32 0
940  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
941  %vc = sdiv <vscale x 1 x i64> %va, %splat
942  ret <vscale x 1 x i64> %vc
943}
944
945define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
946; CHECK-LABEL: vdiv_vv_nxv2i64:
947; CHECK:       # %bb.0:
948; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
949; CHECK-NEXT:    vdiv.vv v8, v8, v10
950; CHECK-NEXT:    ret
951  %vc = sdiv <vscale x 2 x i64> %va, %vb
952  ret <vscale x 2 x i64> %vc
953}
954
955define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
956; RV32-LABEL: vdiv_vx_nxv2i64:
957; RV32:       # %bb.0:
958; RV32-NEXT:    addi sp, sp, -16
959; RV32-NEXT:    .cfi_def_cfa_offset 16
960; RV32-NEXT:    sw a1, 12(sp)
961; RV32-NEXT:    sw a0, 8(sp)
962; RV32-NEXT:    addi a0, sp, 8
963; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
964; RV32-NEXT:    vlse64.v v10, (a0), zero
965; RV32-NEXT:    vdiv.vv v8, v8, v10
966; RV32-NEXT:    addi sp, sp, 16
967; RV32-NEXT:    ret
968;
969; RV64-LABEL: vdiv_vx_nxv2i64:
970; RV64:       # %bb.0:
971; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
972; RV64-NEXT:    vdiv.vx v8, v8, a0
973; RV64-NEXT:    ret
974  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
975  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
976  %vc = sdiv <vscale x 2 x i64> %va, %splat
977  ret <vscale x 2 x i64> %vc
978}
979
980define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
981; RV32-V-LABEL: vdiv_vi_nxv2i64_0:
982; RV32-V:       # %bb.0:
983; RV32-V-NEXT:    addi sp, sp, -16
984; RV32-V-NEXT:    .cfi_def_cfa_offset 16
985; RV32-V-NEXT:    lui a0, 748983
986; RV32-V-NEXT:    addi a0, a0, -586
987; RV32-V-NEXT:    sw a0, 12(sp)
988; RV32-V-NEXT:    lui a0, 898779
989; RV32-V-NEXT:    addi a0, a0, 1755
990; RV32-V-NEXT:    sw a0, 8(sp)
991; RV32-V-NEXT:    addi a0, sp, 8
992; RV32-V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
993; RV32-V-NEXT:    vlse64.v v10, (a0), zero
994; RV32-V-NEXT:    vmulh.vv v8, v8, v10
995; RV32-V-NEXT:    li a0, 63
996; RV32-V-NEXT:    vsrl.vx v10, v8, a0
997; RV32-V-NEXT:    vsra.vi v8, v8, 1
998; RV32-V-NEXT:    vadd.vv v8, v8, v10
999; RV32-V-NEXT:    addi sp, sp, 16
1000; RV32-V-NEXT:    ret
1001;
1002; ZVE64X-LABEL: vdiv_vi_nxv2i64_0:
1003; ZVE64X:       # %bb.0:
1004; ZVE64X-NEXT:    li a0, -7
1005; ZVE64X-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1006; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
1007; ZVE64X-NEXT:    ret
1008;
1009; RV64-V-LABEL: vdiv_vi_nxv2i64_0:
1010; RV64-V:       # %bb.0:
1011; RV64-V-NEXT:    lui a0, %hi(.LCPI61_0)
1012; RV64-V-NEXT:    ld a0, %lo(.LCPI61_0)(a0)
1013; RV64-V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1014; RV64-V-NEXT:    vmulh.vx v8, v8, a0
1015; RV64-V-NEXT:    li a0, 63
1016; RV64-V-NEXT:    vsrl.vx v10, v8, a0
1017; RV64-V-NEXT:    vsra.vi v8, v8, 1
1018; RV64-V-NEXT:    vadd.vv v8, v8, v10
1019; RV64-V-NEXT:    ret
1020  %head = insertelement <vscale x 2 x i64> poison, i64 -7, i32 0
1021  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1022  %vc = sdiv <vscale x 2 x i64> %va, %splat
1023  ret <vscale x 2 x i64> %vc
1024}
1025
1026define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
1027; CHECK-LABEL: vdiv_vv_nxv4i64:
1028; CHECK:       # %bb.0:
1029; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1030; CHECK-NEXT:    vdiv.vv v8, v8, v12
1031; CHECK-NEXT:    ret
1032  %vc = sdiv <vscale x 4 x i64> %va, %vb
1033  ret <vscale x 4 x i64> %vc
1034}
1035
1036define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
1037; RV32-LABEL: vdiv_vx_nxv4i64:
1038; RV32:       # %bb.0:
1039; RV32-NEXT:    addi sp, sp, -16
1040; RV32-NEXT:    .cfi_def_cfa_offset 16
1041; RV32-NEXT:    sw a1, 12(sp)
1042; RV32-NEXT:    sw a0, 8(sp)
1043; RV32-NEXT:    addi a0, sp, 8
1044; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1045; RV32-NEXT:    vlse64.v v12, (a0), zero
1046; RV32-NEXT:    vdiv.vv v8, v8, v12
1047; RV32-NEXT:    addi sp, sp, 16
1048; RV32-NEXT:    ret
1049;
1050; RV64-LABEL: vdiv_vx_nxv4i64:
1051; RV64:       # %bb.0:
1052; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1053; RV64-NEXT:    vdiv.vx v8, v8, a0
1054; RV64-NEXT:    ret
1055  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1056  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1057  %vc = sdiv <vscale x 4 x i64> %va, %splat
1058  ret <vscale x 4 x i64> %vc
1059}
1060
1061define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
1062; RV32-V-LABEL: vdiv_vi_nxv4i64_0:
1063; RV32-V:       # %bb.0:
1064; RV32-V-NEXT:    addi sp, sp, -16
1065; RV32-V-NEXT:    .cfi_def_cfa_offset 16
1066; RV32-V-NEXT:    lui a0, 748983
1067; RV32-V-NEXT:    addi a0, a0, -586
1068; RV32-V-NEXT:    sw a0, 12(sp)
1069; RV32-V-NEXT:    lui a0, 898779
1070; RV32-V-NEXT:    addi a0, a0, 1755
1071; RV32-V-NEXT:    sw a0, 8(sp)
1072; RV32-V-NEXT:    addi a0, sp, 8
1073; RV32-V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1074; RV32-V-NEXT:    vlse64.v v12, (a0), zero
1075; RV32-V-NEXT:    vmulh.vv v8, v8, v12
1076; RV32-V-NEXT:    li a0, 63
1077; RV32-V-NEXT:    vsrl.vx v12, v8, a0
1078; RV32-V-NEXT:    vsra.vi v8, v8, 1
1079; RV32-V-NEXT:    vadd.vv v8, v8, v12
1080; RV32-V-NEXT:    addi sp, sp, 16
1081; RV32-V-NEXT:    ret
1082;
1083; ZVE64X-LABEL: vdiv_vi_nxv4i64_0:
1084; ZVE64X:       # %bb.0:
1085; ZVE64X-NEXT:    li a0, -7
1086; ZVE64X-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1087; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
1088; ZVE64X-NEXT:    ret
1089;
1090; RV64-V-LABEL: vdiv_vi_nxv4i64_0:
1091; RV64-V:       # %bb.0:
1092; RV64-V-NEXT:    lui a0, %hi(.LCPI64_0)
1093; RV64-V-NEXT:    ld a0, %lo(.LCPI64_0)(a0)
1094; RV64-V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1095; RV64-V-NEXT:    vmulh.vx v8, v8, a0
1096; RV64-V-NEXT:    li a0, 63
1097; RV64-V-NEXT:    vsrl.vx v12, v8, a0
1098; RV64-V-NEXT:    vsra.vi v8, v8, 1
1099; RV64-V-NEXT:    vadd.vv v8, v8, v12
1100; RV64-V-NEXT:    ret
1101  %head = insertelement <vscale x 4 x i64> poison, i64 -7, i32 0
1102  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1103  %vc = sdiv <vscale x 4 x i64> %va, %splat
1104  ret <vscale x 4 x i64> %vc
1105}
1106
1107define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1108; CHECK-LABEL: vdiv_vv_nxv8i64:
1109; CHECK:       # %bb.0:
1110; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1111; CHECK-NEXT:    vdiv.vv v8, v8, v16
1112; CHECK-NEXT:    ret
1113  %vc = sdiv <vscale x 8 x i64> %va, %vb
1114  ret <vscale x 8 x i64> %vc
1115}
1116
1117define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
1118; RV32-LABEL: vdiv_vx_nxv8i64:
1119; RV32:       # %bb.0:
1120; RV32-NEXT:    addi sp, sp, -16
1121; RV32-NEXT:    .cfi_def_cfa_offset 16
1122; RV32-NEXT:    sw a1, 12(sp)
1123; RV32-NEXT:    sw a0, 8(sp)
1124; RV32-NEXT:    addi a0, sp, 8
1125; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1126; RV32-NEXT:    vlse64.v v16, (a0), zero
1127; RV32-NEXT:    vdiv.vv v8, v8, v16
1128; RV32-NEXT:    addi sp, sp, 16
1129; RV32-NEXT:    ret
1130;
1131; RV64-LABEL: vdiv_vx_nxv8i64:
1132; RV64:       # %bb.0:
1133; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1134; RV64-NEXT:    vdiv.vx v8, v8, a0
1135; RV64-NEXT:    ret
1136  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1137  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1138  %vc = sdiv <vscale x 8 x i64> %va, %splat
1139  ret <vscale x 8 x i64> %vc
1140}
1141
1142define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
1143; RV32-V-LABEL: vdiv_vi_nxv8i64_0:
1144; RV32-V:       # %bb.0:
1145; RV32-V-NEXT:    addi sp, sp, -16
1146; RV32-V-NEXT:    .cfi_def_cfa_offset 16
1147; RV32-V-NEXT:    lui a0, 748983
1148; RV32-V-NEXT:    addi a0, a0, -586
1149; RV32-V-NEXT:    sw a0, 12(sp)
1150; RV32-V-NEXT:    lui a0, 898779
1151; RV32-V-NEXT:    addi a0, a0, 1755
1152; RV32-V-NEXT:    sw a0, 8(sp)
1153; RV32-V-NEXT:    addi a0, sp, 8
1154; RV32-V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1155; RV32-V-NEXT:    vlse64.v v16, (a0), zero
1156; RV32-V-NEXT:    vmulh.vv v8, v8, v16
1157; RV32-V-NEXT:    li a0, 63
1158; RV32-V-NEXT:    vsrl.vx v16, v8, a0
1159; RV32-V-NEXT:    vsra.vi v8, v8, 1
1160; RV32-V-NEXT:    vadd.vv v8, v8, v16
1161; RV32-V-NEXT:    addi sp, sp, 16
1162; RV32-V-NEXT:    ret
1163;
1164; ZVE64X-LABEL: vdiv_vi_nxv8i64_0:
1165; ZVE64X:       # %bb.0:
1166; ZVE64X-NEXT:    li a0, -7
1167; ZVE64X-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1168; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
1169; ZVE64X-NEXT:    ret
1170;
1171; RV64-V-LABEL: vdiv_vi_nxv8i64_0:
1172; RV64-V:       # %bb.0:
1173; RV64-V-NEXT:    lui a0, %hi(.LCPI67_0)
1174; RV64-V-NEXT:    ld a0, %lo(.LCPI67_0)(a0)
1175; RV64-V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1176; RV64-V-NEXT:    vmulh.vx v8, v8, a0
1177; RV64-V-NEXT:    li a0, 63
1178; RV64-V-NEXT:    vsrl.vx v16, v8, a0
1179; RV64-V-NEXT:    vsra.vi v8, v8, 1
1180; RV64-V-NEXT:    vadd.vv v8, v8, v16
1181; RV64-V-NEXT:    ret
1182  %head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0
1183  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1184  %vc = sdiv <vscale x 8 x i64> %va, %splat
1185  ret <vscale x 8 x i64> %vc
1186}
1187