1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 4 5declare <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8() 6 7define <vscale x 1 x i8> @stepvector_nxv1i8() { 8; CHECK-LABEL: stepvector_nxv1i8: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 11; CHECK-NEXT: vid.v v8 12; CHECK-NEXT: ret 13 %v = call <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8() 14 ret <vscale x 1 x i8> %v 15} 16 17declare <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8() 18 19define <vscale x 2 x i8> @stepvector_nxv2i8() { 20; CHECK-LABEL: stepvector_nxv2i8: 21; CHECK: # %bb.0: 22; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 23; CHECK-NEXT: vid.v v8 24; CHECK-NEXT: ret 25 %v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8() 26 ret <vscale x 2 x i8> %v 27} 28 29declare <vscale x 3 x i8> @llvm.experimental.stepvector.nxv3i8() 30 31define <vscale x 3 x i8> @stepvector_nxv3i8() { 32; CHECK-LABEL: stepvector_nxv3i8: 33; CHECK: # %bb.0: 34; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 35; CHECK-NEXT: vid.v v8 36; CHECK-NEXT: ret 37 %v = call <vscale x 3 x i8> @llvm.experimental.stepvector.nxv3i8() 38 ret <vscale x 3 x i8> %v 39} 40 41declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8() 42 43define <vscale x 4 x i8> @stepvector_nxv4i8() { 44; CHECK-LABEL: stepvector_nxv4i8: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 47; CHECK-NEXT: vid.v v8 48; CHECK-NEXT: ret 49 %v = call <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8() 50 ret <vscale x 4 x i8> %v 51} 52 53declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 54 55define <vscale x 8 x i8> @stepvector_nxv8i8() { 56; CHECK-LABEL: stepvector_nxv8i8: 57; CHECK: # %bb.0: 58; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 59; CHECK-NEXT: vid.v v8 60; CHECK-NEXT: ret 61 %v = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 62 ret <vscale x 8 x i8> %v 63} 64 65define <vscale x 8 x i8> @add_stepvector_nxv8i8() { 66; CHECK-LABEL: add_stepvector_nxv8i8: 67; CHECK: # %bb.0: # %entry 68; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 69; CHECK-NEXT: vid.v v8 70; CHECK-NEXT: vsll.vi v8, v8, 1 71; CHECK-NEXT: ret 72entry: 73 %0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 74 %1 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 75 %2 = add <vscale x 8 x i8> %0, %1 76 ret <vscale x 8 x i8> %2 77} 78 79define <vscale x 8 x i8> @mul_stepvector_nxv8i8() { 80; CHECK-LABEL: mul_stepvector_nxv8i8: 81; CHECK: # %bb.0: # %entry 82; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 83; CHECK-NEXT: vid.v v8 84; CHECK-NEXT: li a0, 3 85; CHECK-NEXT: vmul.vx v8, v8, a0 86; CHECK-NEXT: ret 87entry: 88 %0 = insertelement <vscale x 8 x i8> poison, i8 3, i32 0 89 %1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 90 %2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 91 %3 = mul <vscale x 8 x i8> %2, %1 92 ret <vscale x 8 x i8> %3 93} 94 95define <vscale x 8 x i8> @shl_stepvector_nxv8i8() { 96; CHECK-LABEL: shl_stepvector_nxv8i8: 97; CHECK: # %bb.0: # %entry 98; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 99; CHECK-NEXT: vid.v v8 100; CHECK-NEXT: vsll.vi v8, v8, 2 101; CHECK-NEXT: ret 102entry: 103 %0 = insertelement <vscale x 8 x i8> poison, i8 2, i32 0 104 %1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 105 %2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 106 %3 = shl <vscale x 8 x i8> %2, %1 107 ret <vscale x 8 x i8> %3 108} 109 110declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8() 111 112define <vscale x 16 x i8> @stepvector_nxv16i8() { 113; CHECK-LABEL: stepvector_nxv16i8: 114; CHECK: # %bb.0: 115; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 116; CHECK-NEXT: vid.v v8 117; CHECK-NEXT: ret 118 %v = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8() 119 ret <vscale x 16 x i8> %v 120} 121 122declare <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8() 123 124define <vscale x 32 x i8> @stepvector_nxv32i8() { 125; CHECK-LABEL: stepvector_nxv32i8: 126; CHECK: # %bb.0: 127; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 128; CHECK-NEXT: vid.v v8 129; CHECK-NEXT: ret 130 %v = call <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8() 131 ret <vscale x 32 x i8> %v 132} 133 134declare <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8() 135 136define <vscale x 64 x i8> @stepvector_nxv64i8() { 137; CHECK-LABEL: stepvector_nxv64i8: 138; CHECK: # %bb.0: 139; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 140; CHECK-NEXT: vid.v v8 141; CHECK-NEXT: ret 142 %v = call <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8() 143 ret <vscale x 64 x i8> %v 144} 145 146declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16() 147 148define <vscale x 1 x i16> @stepvector_nxv1i16() { 149; CHECK-LABEL: stepvector_nxv1i16: 150; CHECK: # %bb.0: 151; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 152; CHECK-NEXT: vid.v v8 153; CHECK-NEXT: ret 154 %v = call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16() 155 ret <vscale x 1 x i16> %v 156} 157 158declare <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16() 159 160define <vscale x 2 x i16> @stepvector_nxv2i16() { 161; CHECK-LABEL: stepvector_nxv2i16: 162; CHECK: # %bb.0: 163; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 164; CHECK-NEXT: vid.v v8 165; CHECK-NEXT: ret 166 %v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16() 167 ret <vscale x 2 x i16> %v 168} 169 170declare <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16() 171 172define <vscale x 3 x i16> @stepvector_nxv3i16() { 173; CHECK-LABEL: stepvector_nxv3i16: 174; CHECK: # %bb.0: 175; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 176; CHECK-NEXT: vid.v v8 177; CHECK-NEXT: ret 178 %v = call <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16() 179 ret <vscale x 3 x i16> %v 180} 181 182declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16() 183 184define <vscale x 4 x i16> @stepvector_nxv4i16() { 185; CHECK-LABEL: stepvector_nxv4i16: 186; CHECK: # %bb.0: 187; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 188; CHECK-NEXT: vid.v v8 189; CHECK-NEXT: ret 190 %v = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16() 191 ret <vscale x 4 x i16> %v 192} 193 194declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16() 195 196define <vscale x 8 x i16> @stepvector_nxv8i16() { 197; CHECK-LABEL: stepvector_nxv8i16: 198; CHECK: # %bb.0: 199; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 200; CHECK-NEXT: vid.v v8 201; CHECK-NEXT: ret 202 %v = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16() 203 ret <vscale x 8 x i16> %v 204} 205 206declare <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 207 208define <vscale x 16 x i16> @stepvector_nxv16i16() { 209; CHECK-LABEL: stepvector_nxv16i16: 210; CHECK: # %bb.0: 211; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 212; CHECK-NEXT: vid.v v8 213; CHECK-NEXT: ret 214 %v = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 215 ret <vscale x 16 x i16> %v 216} 217 218define <vscale x 16 x i16> @add_stepvector_nxv16i16() { 219; CHECK-LABEL: add_stepvector_nxv16i16: 220; CHECK: # %bb.0: # %entry 221; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 222; CHECK-NEXT: vid.v v8 223; CHECK-NEXT: vsll.vi v8, v8, 1 224; CHECK-NEXT: ret 225entry: 226 %0 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 227 %1 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 228 %2 = add <vscale x 16 x i16> %0, %1 229 ret <vscale x 16 x i16> %2 230} 231 232define <vscale x 16 x i16> @mul_stepvector_nxv16i16() { 233; CHECK-LABEL: mul_stepvector_nxv16i16: 234; CHECK: # %bb.0: # %entry 235; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 236; CHECK-NEXT: vid.v v8 237; CHECK-NEXT: li a0, 3 238; CHECK-NEXT: vmul.vx v8, v8, a0 239; CHECK-NEXT: ret 240entry: 241 %0 = insertelement <vscale x 16 x i16> poison, i16 3, i32 0 242 %1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 243 %2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 244 %3 = mul <vscale x 16 x i16> %2, %1 245 ret <vscale x 16 x i16> %3 246} 247 248define <vscale x 16 x i16> @shl_stepvector_nxv16i16() { 249; CHECK-LABEL: shl_stepvector_nxv16i16: 250; CHECK: # %bb.0: # %entry 251; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 252; CHECK-NEXT: vid.v v8 253; CHECK-NEXT: vsll.vi v8, v8, 2 254; CHECK-NEXT: ret 255entry: 256 %0 = insertelement <vscale x 16 x i16> poison, i16 2, i32 0 257 %1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 258 %2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 259 %3 = shl <vscale x 16 x i16> %2, %1 260 ret <vscale x 16 x i16> %3 261} 262 263declare <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16() 264 265define <vscale x 32 x i16> @stepvector_nxv32i16() { 266; CHECK-LABEL: stepvector_nxv32i16: 267; CHECK: # %bb.0: 268; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 269; CHECK-NEXT: vid.v v8 270; CHECK-NEXT: ret 271 %v = call <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16() 272 ret <vscale x 32 x i16> %v 273} 274 275declare <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32() 276 277define <vscale x 1 x i32> @stepvector_nxv1i32() { 278; CHECK-LABEL: stepvector_nxv1i32: 279; CHECK: # %bb.0: 280; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 281; CHECK-NEXT: vid.v v8 282; CHECK-NEXT: ret 283 %v = call <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32() 284 ret <vscale x 1 x i32> %v 285} 286 287declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32() 288 289define <vscale x 2 x i32> @stepvector_nxv2i32() { 290; CHECK-LABEL: stepvector_nxv2i32: 291; CHECK: # %bb.0: 292; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 293; CHECK-NEXT: vid.v v8 294; CHECK-NEXT: ret 295 %v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32() 296 ret <vscale x 2 x i32> %v 297} 298 299declare <vscale x 3 x i32> @llvm.experimental.stepvector.nxv3i32() 300 301define <vscale x 3 x i32> @stepvector_nxv3i32() { 302; CHECK-LABEL: stepvector_nxv3i32: 303; CHECK: # %bb.0: 304; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 305; CHECK-NEXT: vid.v v8 306; CHECK-NEXT: ret 307 %v = call <vscale x 3 x i32> @llvm.experimental.stepvector.nxv3i32() 308 ret <vscale x 3 x i32> %v 309} 310 311declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32() 312 313define <vscale x 4 x i32> @stepvector_nxv4i32() { 314; CHECK-LABEL: stepvector_nxv4i32: 315; CHECK: # %bb.0: 316; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 317; CHECK-NEXT: vid.v v8 318; CHECK-NEXT: ret 319 %v = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32() 320 ret <vscale x 4 x i32> %v 321} 322 323declare <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32() 324 325define <vscale x 8 x i32> @stepvector_nxv8i32() { 326; CHECK-LABEL: stepvector_nxv8i32: 327; CHECK: # %bb.0: 328; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 329; CHECK-NEXT: vid.v v8 330; CHECK-NEXT: ret 331 %v = call <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32() 332 ret <vscale x 8 x i32> %v 333} 334 335declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 336 337define <vscale x 16 x i32> @stepvector_nxv16i32() { 338; CHECK-LABEL: stepvector_nxv16i32: 339; CHECK: # %bb.0: 340; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 341; CHECK-NEXT: vid.v v8 342; CHECK-NEXT: ret 343 %v = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 344 ret <vscale x 16 x i32> %v 345} 346 347define <vscale x 16 x i32> @add_stepvector_nxv16i32() { 348; CHECK-LABEL: add_stepvector_nxv16i32: 349; CHECK: # %bb.0: # %entry 350; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 351; CHECK-NEXT: vid.v v8 352; CHECK-NEXT: vsll.vi v8, v8, 1 353; CHECK-NEXT: ret 354entry: 355 %0 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 356 %1 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 357 %2 = add <vscale x 16 x i32> %0, %1 358 ret <vscale x 16 x i32> %2 359} 360 361define <vscale x 16 x i32> @mul_stepvector_nxv16i32() { 362; CHECK-LABEL: mul_stepvector_nxv16i32: 363; CHECK: # %bb.0: # %entry 364; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 365; CHECK-NEXT: vid.v v8 366; CHECK-NEXT: li a0, 3 367; CHECK-NEXT: vmul.vx v8, v8, a0 368; CHECK-NEXT: ret 369entry: 370 %0 = insertelement <vscale x 16 x i32> poison, i32 3, i32 0 371 %1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 372 %2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 373 %3 = mul <vscale x 16 x i32> %2, %1 374 ret <vscale x 16 x i32> %3 375} 376 377define <vscale x 16 x i32> @shl_stepvector_nxv16i32() { 378; CHECK-LABEL: shl_stepvector_nxv16i32: 379; CHECK: # %bb.0: # %entry 380; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 381; CHECK-NEXT: vid.v v8 382; CHECK-NEXT: vsll.vi v8, v8, 2 383; CHECK-NEXT: ret 384entry: 385 %0 = insertelement <vscale x 16 x i32> poison, i32 2, i32 0 386 %1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 387 %2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 388 %3 = shl <vscale x 16 x i32> %2, %1 389 ret <vscale x 16 x i32> %3 390} 391 392declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64() 393 394define <vscale x 1 x i64> @stepvector_nxv1i64() { 395; CHECK-LABEL: stepvector_nxv1i64: 396; CHECK: # %bb.0: 397; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 398; CHECK-NEXT: vid.v v8 399; CHECK-NEXT: ret 400 %v = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64() 401 ret <vscale x 1 x i64> %v 402} 403 404declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64() 405 406define <vscale x 2 x i64> @stepvector_nxv2i64() { 407; CHECK-LABEL: stepvector_nxv2i64: 408; CHECK: # %bb.0: 409; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 410; CHECK-NEXT: vid.v v8 411; CHECK-NEXT: ret 412 %v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64() 413 ret <vscale x 2 x i64> %v 414} 415 416declare <vscale x 3 x i64> @llvm.experimental.stepvector.nxv3i64() 417 418define <vscale x 3 x i64> @stepvector_nxv3i64() { 419; CHECK-LABEL: stepvector_nxv3i64: 420; CHECK: # %bb.0: 421; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 422; CHECK-NEXT: vid.v v8 423; CHECK-NEXT: ret 424 %v = call <vscale x 3 x i64> @llvm.experimental.stepvector.nxv3i64() 425 ret <vscale x 3 x i64> %v 426} 427 428declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64() 429 430define <vscale x 4 x i64> @stepvector_nxv4i64() { 431; CHECK-LABEL: stepvector_nxv4i64: 432; CHECK: # %bb.0: 433; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 434; CHECK-NEXT: vid.v v8 435; CHECK-NEXT: ret 436 %v = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64() 437 ret <vscale x 4 x i64> %v 438} 439 440declare <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 441 442define <vscale x 8 x i64> @stepvector_nxv8i64() { 443; CHECK-LABEL: stepvector_nxv8i64: 444; CHECK: # %bb.0: 445; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 446; CHECK-NEXT: vid.v v8 447; CHECK-NEXT: ret 448 %v = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 449 ret <vscale x 8 x i64> %v 450} 451 452define <vscale x 8 x i64> @add_stepvector_nxv8i64() { 453; CHECK-LABEL: add_stepvector_nxv8i64: 454; CHECK: # %bb.0: # %entry 455; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 456; CHECK-NEXT: vid.v v8 457; CHECK-NEXT: vsll.vi v8, v8, 1 458; CHECK-NEXT: ret 459entry: 460 %0 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 461 %1 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 462 %2 = add <vscale x 8 x i64> %0, %1 463 ret <vscale x 8 x i64> %2 464} 465 466define <vscale x 8 x i64> @mul_stepvector_nxv8i64() { 467; CHECK-LABEL: mul_stepvector_nxv8i64: 468; CHECK: # %bb.0: # %entry 469; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 470; CHECK-NEXT: vid.v v8 471; CHECK-NEXT: li a0, 3 472; CHECK-NEXT: vmul.vx v8, v8, a0 473; CHECK-NEXT: ret 474entry: 475 %0 = insertelement <vscale x 8 x i64> poison, i64 3, i32 0 476 %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 477 %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 478 %3 = mul <vscale x 8 x i64> %2, %1 479 ret <vscale x 8 x i64> %3 480} 481 482define <vscale x 8 x i64> @mul_bigimm_stepvector_nxv8i64() { 483; RV32-LABEL: mul_bigimm_stepvector_nxv8i64: 484; RV32: # %bb.0: # %entry 485; RV32-NEXT: addi sp, sp, -16 486; RV32-NEXT: .cfi_def_cfa_offset 16 487; RV32-NEXT: li a0, 7 488; RV32-NEXT: sw a0, 12(sp) 489; RV32-NEXT: lui a0, 797989 490; RV32-NEXT: addi a0, a0, -683 491; RV32-NEXT: sw a0, 8(sp) 492; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 493; RV32-NEXT: addi a0, sp, 8 494; RV32-NEXT: vlse64.v v8, (a0), zero 495; RV32-NEXT: vid.v v16 496; RV32-NEXT: vmul.vv v8, v16, v8 497; RV32-NEXT: addi sp, sp, 16 498; RV32-NEXT: ret 499; 500; RV64-LABEL: mul_bigimm_stepvector_nxv8i64: 501; RV64: # %bb.0: # %entry 502; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu 503; RV64-NEXT: vid.v v8 504; RV64-NEXT: lui a0, 1987 505; RV64-NEXT: addiw a0, a0, -731 506; RV64-NEXT: slli a0, a0, 12 507; RV64-NEXT: addi a0, a0, -683 508; RV64-NEXT: vmul.vx v8, v8, a0 509; RV64-NEXT: ret 510entry: 511 %0 = insertelement <vscale x 8 x i64> poison, i64 33333333333, i32 0 512 %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 513 %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 514 %3 = mul <vscale x 8 x i64> %2, %1 515 ret <vscale x 8 x i64> %3 516} 517 518 519define <vscale x 8 x i64> @shl_stepvector_nxv8i64() { 520; CHECK-LABEL: shl_stepvector_nxv8i64: 521; CHECK: # %bb.0: # %entry 522; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 523; CHECK-NEXT: vid.v v8 524; CHECK-NEXT: vsll.vi v8, v8, 2 525; CHECK-NEXT: ret 526entry: 527 %0 = insertelement <vscale x 8 x i64> poison, i64 2, i32 0 528 %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 529 %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 530 %3 = shl <vscale x 8 x i64> %2, %1 531 ret <vscale x 8 x i64> %3 532} 533 534declare <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 535 536define <vscale x 16 x i64> @stepvector_nxv16i64() { 537; RV32-LABEL: stepvector_nxv16i64: 538; RV32: # %bb.0: 539; RV32-NEXT: addi sp, sp, -16 540; RV32-NEXT: .cfi_def_cfa_offset 16 541; RV32-NEXT: sw zero, 12(sp) 542; RV32-NEXT: csrr a0, vlenb 543; RV32-NEXT: sw a0, 8(sp) 544; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 545; RV32-NEXT: addi a0, sp, 8 546; RV32-NEXT: vlse64.v v16, (a0), zero 547; RV32-NEXT: vid.v v8 548; RV32-NEXT: vadd.vv v16, v8, v16 549; RV32-NEXT: addi sp, sp, 16 550; RV32-NEXT: ret 551; 552; RV64-LABEL: stepvector_nxv16i64: 553; RV64: # %bb.0: 554; RV64-NEXT: csrr a0, vlenb 555; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 556; RV64-NEXT: vid.v v8 557; RV64-NEXT: vadd.vx v16, v8, a0 558; RV64-NEXT: ret 559 %v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 560 ret <vscale x 16 x i64> %v 561} 562 563define <vscale x 16 x i64> @add_stepvector_nxv16i64() { 564; RV32-LABEL: add_stepvector_nxv16i64: 565; RV32: # %bb.0: # %entry 566; RV32-NEXT: addi sp, sp, -16 567; RV32-NEXT: .cfi_def_cfa_offset 16 568; RV32-NEXT: sw zero, 12(sp) 569; RV32-NEXT: csrr a0, vlenb 570; RV32-NEXT: slli a0, a0, 1 571; RV32-NEXT: sw a0, 8(sp) 572; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 573; RV32-NEXT: addi a0, sp, 8 574; RV32-NEXT: vlse64.v v16, (a0), zero 575; RV32-NEXT: vid.v v8 576; RV32-NEXT: vsll.vi v8, v8, 1 577; RV32-NEXT: vadd.vv v16, v8, v16 578; RV32-NEXT: addi sp, sp, 16 579; RV32-NEXT: ret 580; 581; RV64-LABEL: add_stepvector_nxv16i64: 582; RV64: # %bb.0: # %entry 583; RV64-NEXT: csrr a0, vlenb 584; RV64-NEXT: slli a0, a0, 1 585; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 586; RV64-NEXT: vid.v v8 587; RV64-NEXT: vsll.vi v8, v8, 1 588; RV64-NEXT: vadd.vx v16, v8, a0 589; RV64-NEXT: ret 590entry: 591 %0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 592 %1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 593 %2 = add <vscale x 16 x i64> %0, %1 594 ret <vscale x 16 x i64> %2 595} 596 597define <vscale x 16 x i64> @mul_stepvector_nxv16i64() { 598; RV32-LABEL: mul_stepvector_nxv16i64: 599; RV32: # %bb.0: # %entry 600; RV32-NEXT: addi sp, sp, -16 601; RV32-NEXT: .cfi_def_cfa_offset 16 602; RV32-NEXT: sw zero, 12(sp) 603; RV32-NEXT: csrr a0, vlenb 604; RV32-NEXT: slli a1, a0, 1 605; RV32-NEXT: add a0, a1, a0 606; RV32-NEXT: sw a0, 8(sp) 607; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 608; RV32-NEXT: addi a0, sp, 8 609; RV32-NEXT: vlse64.v v16, (a0), zero 610; RV32-NEXT: vid.v v8 611; RV32-NEXT: li a0, 3 612; RV32-NEXT: vmul.vx v8, v8, a0 613; RV32-NEXT: vadd.vv v16, v8, v16 614; RV32-NEXT: addi sp, sp, 16 615; RV32-NEXT: ret 616; 617; RV64-LABEL: mul_stepvector_nxv16i64: 618; RV64: # %bb.0: # %entry 619; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu 620; RV64-NEXT: vid.v v8 621; RV64-NEXT: li a0, 3 622; RV64-NEXT: vmul.vx v8, v8, a0 623; RV64-NEXT: csrr a0, vlenb 624; RV64-NEXT: slli a1, a0, 1 625; RV64-NEXT: add a0, a1, a0 626; RV64-NEXT: vadd.vx v16, v8, a0 627; RV64-NEXT: ret 628entry: 629 %0 = insertelement <vscale x 16 x i64> poison, i64 3, i32 0 630 %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer 631 %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 632 %3 = mul <vscale x 16 x i64> %2, %1 633 ret <vscale x 16 x i64> %3 634} 635 636define <vscale x 16 x i64> @mul_bigimm_stepvector_nxv16i64() { 637; RV32-LABEL: mul_bigimm_stepvector_nxv16i64: 638; RV32: # %bb.0: # %entry 639; RV32-NEXT: addi sp, sp, -16 640; RV32-NEXT: .cfi_def_cfa_offset 16 641; RV32-NEXT: li a0, 7 642; RV32-NEXT: sw a0, 12(sp) 643; RV32-NEXT: lui a0, 797989 644; RV32-NEXT: addi a0, a0, -683 645; RV32-NEXT: sw a0, 8(sp) 646; RV32-NEXT: csrr a0, vlenb 647; RV32-NEXT: lui a1, 11557 648; RV32-NEXT: addi a1, a1, -683 649; RV32-NEXT: mul a1, a0, a1 650; RV32-NEXT: sw a1, 8(sp) 651; RV32-NEXT: srli a0, a0, 3 652; RV32-NEXT: li a1, 62 653; RV32-NEXT: mul a1, a0, a1 654; RV32-NEXT: lui a2, 92455 655; RV32-NEXT: addi a2, a2, -1368 656; RV32-NEXT: mulhu a0, a0, a2 657; RV32-NEXT: add a0, a0, a1 658; RV32-NEXT: sw a0, 12(sp) 659; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 660; RV32-NEXT: addi a0, sp, 8 661; RV32-NEXT: vlse64.v v8, (a0), zero 662; RV32-NEXT: addi a0, sp, 8 663; RV32-NEXT: vlse64.v v16, (a0), zero 664; RV32-NEXT: vid.v v24 665; RV32-NEXT: vmul.vv v8, v24, v8 666; RV32-NEXT: vadd.vv v16, v8, v16 667; RV32-NEXT: addi sp, sp, 16 668; RV32-NEXT: ret 669; 670; RV64-LABEL: mul_bigimm_stepvector_nxv16i64: 671; RV64: # %bb.0: # %entry 672; RV64-NEXT: csrr a0, vlenb 673; RV64-NEXT: lui a1, 1987 674; RV64-NEXT: addiw a1, a1, -731 675; RV64-NEXT: slli a1, a1, 12 676; RV64-NEXT: addi a1, a1, -683 677; RV64-NEXT: mul a0, a0, a1 678; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu 679; RV64-NEXT: vid.v v8 680; RV64-NEXT: vmul.vx v8, v8, a1 681; RV64-NEXT: vadd.vx v16, v8, a0 682; RV64-NEXT: ret 683entry: 684 %0 = insertelement <vscale x 16 x i64> poison, i64 33333333333, i32 0 685 %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer 686 %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 687 %3 = mul <vscale x 16 x i64> %2, %1 688 ret <vscale x 16 x i64> %3 689} 690 691define <vscale x 16 x i64> @shl_stepvector_nxv16i64() { 692; RV32-LABEL: shl_stepvector_nxv16i64: 693; RV32: # %bb.0: # %entry 694; RV32-NEXT: addi sp, sp, -16 695; RV32-NEXT: .cfi_def_cfa_offset 16 696; RV32-NEXT: sw zero, 12(sp) 697; RV32-NEXT: csrr a0, vlenb 698; RV32-NEXT: slli a0, a0, 2 699; RV32-NEXT: sw a0, 8(sp) 700; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 701; RV32-NEXT: addi a0, sp, 8 702; RV32-NEXT: vlse64.v v16, (a0), zero 703; RV32-NEXT: vid.v v8 704; RV32-NEXT: vsll.vi v8, v8, 2 705; RV32-NEXT: vadd.vv v16, v8, v16 706; RV32-NEXT: addi sp, sp, 16 707; RV32-NEXT: ret 708; 709; RV64-LABEL: shl_stepvector_nxv16i64: 710; RV64: # %bb.0: # %entry 711; RV64-NEXT: csrr a0, vlenb 712; RV64-NEXT: slli a0, a0, 2 713; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 714; RV64-NEXT: vid.v v8 715; RV64-NEXT: vsll.vi v8, v8, 2 716; RV64-NEXT: vadd.vx v16, v8, a0 717; RV64-NEXT: ret 718entry: 719 %0 = insertelement <vscale x 16 x i64> poison, i64 2, i32 0 720 %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer 721 %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 722 %3 = shl <vscale x 16 x i64> %2, %1 723 ret <vscale x 16 x i64> %3 724} 725