1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s \
3; RUN:     | FileCheck %s --check-prefixes=CHECK
4; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s \
5; RUN:     | FileCheck %s --check-prefixes=CHECK
6
7declare <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
8
9define <vscale x 1 x i8> @stepvector_nxv1i8() {
10; CHECK-LABEL: stepvector_nxv1i8:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
13; CHECK-NEXT:    vid.v v8
14; CHECK-NEXT:    ret
15  %v = call <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
16  ret <vscale x 1 x i8> %v
17}
18
19declare <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
20
21define <vscale x 2 x i8> @stepvector_nxv2i8() {
22; CHECK-LABEL: stepvector_nxv2i8:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
25; CHECK-NEXT:    vid.v v8
26; CHECK-NEXT:    ret
27  %v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
28  ret <vscale x 2 x i8> %v
29}
30
31declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
32
33define <vscale x 4 x i8> @stepvector_nxv4i8() {
34; CHECK-LABEL: stepvector_nxv4i8:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
37; CHECK-NEXT:    vid.v v8
38; CHECK-NEXT:    ret
39  %v = call <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
40  ret <vscale x 4 x i8> %v
41}
42
43declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
44
45define <vscale x 8 x i8> @stepvector_nxv8i8() {
46; CHECK-LABEL: stepvector_nxv8i8:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
49; CHECK-NEXT:    vid.v v8
50; CHECK-NEXT:    ret
51  %v = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
52  ret <vscale x 8 x i8> %v
53}
54
55define <vscale x 8 x i8> @add_stepvector_nxv8i8() {
56; CHECK-LABEL: add_stepvector_nxv8i8:
57; CHECK:       # %bb.0: # %entry
58; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
59; CHECK-NEXT:    vid.v v25
60; CHECK-NEXT:    vsll.vi v8, v25, 1
61; CHECK-NEXT:    ret
62entry:
63  %0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
64  %1 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
65  %2 = add <vscale x 8 x i8> %0, %1
66  ret <vscale x 8 x i8> %2
67}
68
69define <vscale x 8 x i8> @mul_stepvector_nxv8i8() {
70; CHECK-LABEL: mul_stepvector_nxv8i8:
71; CHECK:       # %bb.0: # %entry
72; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
73; CHECK-NEXT:    vid.v v25
74; CHECK-NEXT:    addi a0, zero, 3
75; CHECK-NEXT:    vmul.vx v8, v25, a0
76; CHECK-NEXT:    ret
77entry:
78  %0 = insertelement <vscale x 8 x i8> poison, i8 3, i32 0
79  %1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
80  %2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
81  %3 = mul <vscale x 8 x i8> %2, %1
82  ret <vscale x 8 x i8> %3
83}
84
85define <vscale x 8 x i8> @shl_stepvector_nxv8i8() {
86; CHECK-LABEL: shl_stepvector_nxv8i8:
87; CHECK:       # %bb.0: # %entry
88; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
89; CHECK-NEXT:    vid.v v25
90; CHECK-NEXT:    vsll.vi v8, v25, 2
91; CHECK-NEXT:    ret
92entry:
93  %0 = insertelement <vscale x 8 x i8> poison, i8 2, i32 0
94  %1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
95  %2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
96  %3 = shl <vscale x 8 x i8> %2, %1
97  ret <vscale x 8 x i8> %3
98}
99
100declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
101
102define <vscale x 16 x i8> @stepvector_nxv16i8() {
103; CHECK-LABEL: stepvector_nxv16i8:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
106; CHECK-NEXT:    vid.v v8
107; CHECK-NEXT:    ret
108  %v = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
109  ret <vscale x 16 x i8> %v
110}
111
112declare <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
113
114define <vscale x 32 x i8> @stepvector_nxv32i8() {
115; CHECK-LABEL: stepvector_nxv32i8:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
118; CHECK-NEXT:    vid.v v8
119; CHECK-NEXT:    ret
120  %v = call <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
121  ret <vscale x 32 x i8> %v
122}
123
124declare <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
125
126define <vscale x 64 x i8> @stepvector_nxv64i8() {
127; CHECK-LABEL: stepvector_nxv64i8:
128; CHECK:       # %bb.0:
129; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
130; CHECK-NEXT:    vid.v v8
131; CHECK-NEXT:    ret
132  %v = call <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
133  ret <vscale x 64 x i8> %v
134}
135
136declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
137
138define <vscale x 1 x i16> @stepvector_nxv1i16() {
139; CHECK-LABEL: stepvector_nxv1i16:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
142; CHECK-NEXT:    vid.v v8
143; CHECK-NEXT:    ret
144  %v = call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
145  ret <vscale x 1 x i16> %v
146}
147
148declare <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
149
150define <vscale x 2 x i16> @stepvector_nxv2i16() {
151; CHECK-LABEL: stepvector_nxv2i16:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
154; CHECK-NEXT:    vid.v v8
155; CHECK-NEXT:    ret
156  %v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
157  ret <vscale x 2 x i16> %v
158}
159
160declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
161
162define <vscale x 4 x i16> @stepvector_nxv4i16() {
163; CHECK-LABEL: stepvector_nxv4i16:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
166; CHECK-NEXT:    vid.v v8
167; CHECK-NEXT:    ret
168  %v = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
169  ret <vscale x 4 x i16> %v
170}
171
172declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
173
174define <vscale x 8 x i16> @stepvector_nxv8i16() {
175; CHECK-LABEL: stepvector_nxv8i16:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
178; CHECK-NEXT:    vid.v v8
179; CHECK-NEXT:    ret
180  %v = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
181  ret <vscale x 8 x i16> %v
182}
183
184declare <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
185
186define <vscale x 16 x i16> @stepvector_nxv16i16() {
187; CHECK-LABEL: stepvector_nxv16i16:
188; CHECK:       # %bb.0:
189; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
190; CHECK-NEXT:    vid.v v8
191; CHECK-NEXT:    ret
192  %v = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
193  ret <vscale x 16 x i16> %v
194}
195
196define <vscale x 16 x i16> @add_stepvector_nxv16i16() {
197; CHECK-LABEL: add_stepvector_nxv16i16:
198; CHECK:       # %bb.0: # %entry
199; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
200; CHECK-NEXT:    vid.v v28
201; CHECK-NEXT:    vsll.vi v8, v28, 1
202; CHECK-NEXT:    ret
203entry:
204  %0 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
205  %1 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
206  %2 = add <vscale x 16 x i16> %0, %1
207  ret <vscale x 16 x i16> %2
208}
209
210define <vscale x 16 x i16> @mul_stepvector_nxv16i16() {
211; CHECK-LABEL: mul_stepvector_nxv16i16:
212; CHECK:       # %bb.0: # %entry
213; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
214; CHECK-NEXT:    vid.v v28
215; CHECK-NEXT:    addi a0, zero, 3
216; CHECK-NEXT:    vmul.vx v8, v28, a0
217; CHECK-NEXT:    ret
218entry:
219  %0 = insertelement <vscale x 16 x i16> poison, i16 3, i32 0
220  %1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
221  %2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
222  %3 = mul <vscale x 16 x i16> %2, %1
223  ret <vscale x 16 x i16> %3
224}
225
226define <vscale x 16 x i16> @shl_stepvector_nxv16i16() {
227; CHECK-LABEL: shl_stepvector_nxv16i16:
228; CHECK:       # %bb.0: # %entry
229; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
230; CHECK-NEXT:    vid.v v28
231; CHECK-NEXT:    vsll.vi v8, v28, 2
232; CHECK-NEXT:    ret
233entry:
234  %0 = insertelement <vscale x 16 x i16> poison, i16 2, i32 0
235  %1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
236  %2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
237  %3 = shl <vscale x 16 x i16> %2, %1
238  ret <vscale x 16 x i16> %3
239}
240
241declare <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
242
243define <vscale x 32 x i16> @stepvector_nxv32i16() {
244; CHECK-LABEL: stepvector_nxv32i16:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
247; CHECK-NEXT:    vid.v v8
248; CHECK-NEXT:    ret
249  %v = call <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
250  ret <vscale x 32 x i16> %v
251}
252
253declare <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
254
255define <vscale x 1 x i32> @stepvector_nxv1i32() {
256; CHECK-LABEL: stepvector_nxv1i32:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
259; CHECK-NEXT:    vid.v v8
260; CHECK-NEXT:    ret
261  %v = call <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
262  ret <vscale x 1 x i32> %v
263}
264
265declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
266
267define <vscale x 2 x i32> @stepvector_nxv2i32() {
268; CHECK-LABEL: stepvector_nxv2i32:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
271; CHECK-NEXT:    vid.v v8
272; CHECK-NEXT:    ret
273  %v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
274  ret <vscale x 2 x i32> %v
275}
276
277declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
278
279define <vscale x 4 x i32> @stepvector_nxv4i32() {
280; CHECK-LABEL: stepvector_nxv4i32:
281; CHECK:       # %bb.0:
282; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
283; CHECK-NEXT:    vid.v v8
284; CHECK-NEXT:    ret
285  %v = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
286  ret <vscale x 4 x i32> %v
287}
288
289declare <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
290
291define <vscale x 8 x i32> @stepvector_nxv8i32() {
292; CHECK-LABEL: stepvector_nxv8i32:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
295; CHECK-NEXT:    vid.v v8
296; CHECK-NEXT:    ret
297  %v = call <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
298  ret <vscale x 8 x i32> %v
299}
300
301declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
302
303define <vscale x 16 x i32> @stepvector_nxv16i32() {
304; CHECK-LABEL: stepvector_nxv16i32:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
307; CHECK-NEXT:    vid.v v8
308; CHECK-NEXT:    ret
309  %v = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
310  ret <vscale x 16 x i32> %v
311}
312
313define <vscale x 16 x i32> @add_stepvector_nxv16i32() {
314; CHECK-LABEL: add_stepvector_nxv16i32:
315; CHECK:       # %bb.0: # %entry
316; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
317; CHECK-NEXT:    vid.v v8
318; CHECK-NEXT:    vsll.vi v8, v8, 1
319; CHECK-NEXT:    ret
320entry:
321  %0 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
322  %1 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
323  %2 = add <vscale x 16 x i32> %0, %1
324  ret <vscale x 16 x i32> %2
325}
326
327define <vscale x 16 x i32> @mul_stepvector_nxv16i32() {
328; CHECK-LABEL: mul_stepvector_nxv16i32:
329; CHECK:       # %bb.0: # %entry
330; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
331; CHECK-NEXT:    vid.v v8
332; CHECK-NEXT:    addi a0, zero, 3
333; CHECK-NEXT:    vmul.vx v8, v8, a0
334; CHECK-NEXT:    ret
335entry:
336  %0 = insertelement <vscale x 16 x i32> poison, i32 3, i32 0
337  %1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
338  %2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
339  %3 = mul <vscale x 16 x i32> %2, %1
340  ret <vscale x 16 x i32> %3
341}
342
343define <vscale x 16 x i32> @shl_stepvector_nxv16i32() {
344; CHECK-LABEL: shl_stepvector_nxv16i32:
345; CHECK:       # %bb.0: # %entry
346; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
347; CHECK-NEXT:    vid.v v8
348; CHECK-NEXT:    vsll.vi v8, v8, 2
349; CHECK-NEXT:    ret
350entry:
351  %0 = insertelement <vscale x 16 x i32> poison, i32 2, i32 0
352  %1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
353  %2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
354  %3 = shl <vscale x 16 x i32> %2, %1
355  ret <vscale x 16 x i32> %3
356}
357
358declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
359
360define <vscale x 1 x i64> @stepvector_nxv1i64() {
361; CHECK-LABEL: stepvector_nxv1i64:
362; CHECK:       # %bb.0:
363; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
364; CHECK-NEXT:    vid.v v8
365; CHECK-NEXT:    ret
366  %v = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
367  ret <vscale x 1 x i64> %v
368}
369
370declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
371
372define <vscale x 2 x i64> @stepvector_nxv2i64() {
373; CHECK-LABEL: stepvector_nxv2i64:
374; CHECK:       # %bb.0:
375; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
376; CHECK-NEXT:    vid.v v8
377; CHECK-NEXT:    ret
378  %v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
379  ret <vscale x 2 x i64> %v
380}
381
382declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
383
384define <vscale x 4 x i64> @stepvector_nxv4i64() {
385; CHECK-LABEL: stepvector_nxv4i64:
386; CHECK:       # %bb.0:
387; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
388; CHECK-NEXT:    vid.v v8
389; CHECK-NEXT:    ret
390  %v = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
391  ret <vscale x 4 x i64> %v
392}
393
394declare <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
395
396define <vscale x 8 x i64> @stepvector_nxv8i64() {
397; CHECK-LABEL: stepvector_nxv8i64:
398; CHECK:       # %bb.0:
399; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
400; CHECK-NEXT:    vid.v v8
401; CHECK-NEXT:    ret
402  %v = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
403  ret <vscale x 8 x i64> %v
404}
405
406define <vscale x 8 x i64> @add_stepvector_nxv8i64() {
407; CHECK-LABEL: add_stepvector_nxv8i64:
408; CHECK:       # %bb.0: # %entry
409; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
410; CHECK-NEXT:    vid.v v8
411; CHECK-NEXT:    vsll.vi v8, v8, 1
412; CHECK-NEXT:    ret
413entry:
414  %0 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
415  %1 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
416  %2 = add <vscale x 8 x i64> %0, %1
417  ret <vscale x 8 x i64> %2
418}
419
420define <vscale x 8 x i64> @mul_stepvector_nxv8i64() {
421; CHECK-LABEL: mul_stepvector_nxv8i64:
422; CHECK:       # %bb.0: # %entry
423; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
424; CHECK-NEXT:    vid.v v8
425; CHECK-NEXT:    addi a0, zero, 3
426; CHECK-NEXT:    vmul.vx v8, v8, a0
427; CHECK-NEXT:    ret
428entry:
429  %0 = insertelement <vscale x 8 x i64> poison, i64 3, i32 0
430  %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
431  %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
432  %3 = mul <vscale x 8 x i64> %2, %1
433  ret <vscale x 8 x i64> %3
434}
435
436define <vscale x 8 x i64> @shl_stepvector_nxv8i64() {
437; CHECK-LABEL: shl_stepvector_nxv8i64:
438; CHECK:       # %bb.0: # %entry
439; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
440; CHECK-NEXT:    vid.v v8
441; CHECK-NEXT:    vsll.vi v8, v8, 2
442; CHECK-NEXT:    ret
443entry:
444  %0 = insertelement <vscale x 8 x i64> poison, i64 2, i32 0
445  %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
446  %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
447  %3 = shl <vscale x 8 x i64> %2, %1
448  ret <vscale x 8 x i64> %3
449}
450
451declare <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
452
453define <vscale x 16 x i64> @stepvector_nxv16i64() {
454; CHECK-LABEL: stepvector_nxv16i64:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    csrr a0, vlenb
457; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
458; CHECK-NEXT:    vid.v v8
459; CHECK-NEXT:    vadd.vx v16, v8, a0
460; CHECK-NEXT:    ret
461  %v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
462  ret <vscale x 16 x i64> %v
463}
464
465define <vscale x 16 x i64> @add_stepvector_nxv16i64() {
466; RV32-LABEL: add_stepvector_nxv16i64:
467; RV32:       # %bb.0: # %entry
468; RV32-NEXT:    csrr a0, vlenb
469; RV32-NEXT:    slli a0, a0, 1
470; RV32-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
471; RV32-NEXT:    vmv.v.x v8, a0
472; RV32-NEXT:    addi a0, zero, 32
473; RV32-NEXT:    vsll.vx v8, v8, a0
474; RV32-NEXT:    vsrl.vx v16, v8, a0
475; RV32-NEXT:    vid.v v8
476; RV32-NEXT:    vsll.vi v8, v8, 1
477; RV32-NEXT:    vadd.vv v16, v8, v16
478; RV32-NEXT:    ret
479;
480; RV64-LABEL: add_stepvector_nxv16i64:
481; RV64:       # %bb.0: # %entry
482; RV64-NEXT:    csrr a0, vlenb
483; RV64-NEXT:    slli a0, a0, 1
484; RV64-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
485; RV64-NEXT:    vid.v v8
486; RV64-NEXT:    vsll.vi v8, v8, 1
487; RV64-NEXT:    vadd.vx v16, v8, a0
488; RV64-NEXT:    ret
489entry:
490  %0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
491  %1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
492  %2 = add <vscale x 16 x i64> %0, %1
493  ret <vscale x 16 x i64> %2
494}
495
496define <vscale x 16 x i64> @mul_stepvector_nxv16i64() {
497; RV32-LABEL: mul_stepvector_nxv16i64:
498; RV32:       # %bb.0: # %entry
499; RV32-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
500; RV32-NEXT:    vid.v v8
501; RV32-NEXT:    addi a0, zero, 3
502; RV32-NEXT:    vmul.vx v8, v8, a0
503; RV32-NEXT:    csrr a0, vlenb
504; RV32-NEXT:    srli a0, a0, 3
505; RV32-NEXT:    addi a1, zero, 24
506; RV32-NEXT:    mul a0, a0, a1
507; RV32-NEXT:    vmv.v.x v16, a0
508; RV32-NEXT:    addi a0, zero, 32
509; RV32-NEXT:    vsll.vx v16, v16, a0
510; RV32-NEXT:    vsrl.vx v16, v16, a0
511; RV32-NEXT:    vadd.vv v16, v8, v16
512; RV32-NEXT:    ret
513;
514; RV64-LABEL: mul_stepvector_nxv16i64:
515; RV64:       # %bb.0: # %entry
516; RV64-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
517; RV64-NEXT:    vid.v v8
518; RV64-NEXT:    addi a0, zero, 3
519; RV64-NEXT:    vmul.vx v8, v8, a0
520; RV64-NEXT:    csrr a0, vlenb
521; RV64-NEXT:    srli a0, a0, 3
522; RV64-NEXT:    addi a1, zero, 24
523; RV64-NEXT:    mul a0, a0, a1
524; RV64-NEXT:    vadd.vx v16, v8, a0
525; RV64-NEXT:    ret
526entry:
527  %0 = insertelement <vscale x 16 x i64> poison, i64 3, i32 0
528  %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer
529  %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
530  %3 = mul <vscale x 16 x i64> %2, %1
531  ret <vscale x 16 x i64> %3
532}
533
534define <vscale x 16 x i64> @shl_stepvector_nxv16i64() {
535; RV32-LABEL: shl_stepvector_nxv16i64:
536; RV32:       # %bb.0: # %entry
537; RV32-NEXT:    csrr a0, vlenb
538; RV32-NEXT:    slli a0, a0, 2
539; RV32-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
540; RV32-NEXT:    vmv.v.x v8, a0
541; RV32-NEXT:    addi a0, zero, 32
542; RV32-NEXT:    vsll.vx v8, v8, a0
543; RV32-NEXT:    vsrl.vx v16, v8, a0
544; RV32-NEXT:    vid.v v8
545; RV32-NEXT:    vsll.vi v8, v8, 2
546; RV32-NEXT:    vadd.vv v16, v8, v16
547; RV32-NEXT:    ret
548;
549; RV64-LABEL: shl_stepvector_nxv16i64:
550; RV64:       # %bb.0: # %entry
551; RV64-NEXT:    csrr a0, vlenb
552; RV64-NEXT:    slli a0, a0, 2
553; RV64-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
554; RV64-NEXT:    vid.v v8
555; RV64-NEXT:    vsll.vi v8, v8, 2
556; RV64-NEXT:    vadd.vx v16, v8, a0
557; RV64-NEXT:    ret
558entry:
559  %0 = insertelement <vscale x 16 x i64> poison, i64 2, i32 0
560  %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer
561  %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
562  %3 = shl <vscale x 16 x i64> %2, %1
563  ret <vscale x 16 x i64> %3
564}
565