1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s \
3; RUN:     | FileCheck %s --check-prefixes=CHECK
4; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s \
5; RUN:     | FileCheck %s --check-prefixes=CHECK
6
7declare <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
8
9define <vscale x 1 x i8> @stepvector_nxv1i8() {
10; CHECK-LABEL: stepvector_nxv1i8:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
13; CHECK-NEXT:    vid.v v8
14; CHECK-NEXT:    ret
15  %v = call <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
16  ret <vscale x 1 x i8> %v
17}
18
19declare <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
20
21define <vscale x 2 x i8> @stepvector_nxv2i8() {
22; CHECK-LABEL: stepvector_nxv2i8:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
25; CHECK-NEXT:    vid.v v8
26; CHECK-NEXT:    ret
27  %v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
28  ret <vscale x 2 x i8> %v
29}
30
31declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
32
33define <vscale x 4 x i8> @stepvector_nxv4i8() {
34; CHECK-LABEL: stepvector_nxv4i8:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
37; CHECK-NEXT:    vid.v v8
38; CHECK-NEXT:    ret
39  %v = call <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
40  ret <vscale x 4 x i8> %v
41}
42
43declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
44
45define <vscale x 8 x i8> @stepvector_nxv8i8() {
46; CHECK-LABEL: stepvector_nxv8i8:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
49; CHECK-NEXT:    vid.v v8
50; CHECK-NEXT:    ret
51  %v = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
52  ret <vscale x 8 x i8> %v
53}
54
55declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
56
57define <vscale x 16 x i8> @stepvector_nxv16i8() {
58; CHECK-LABEL: stepvector_nxv16i8:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
61; CHECK-NEXT:    vid.v v8
62; CHECK-NEXT:    ret
63  %v = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
64  ret <vscale x 16 x i8> %v
65}
66
67declare <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
68
69define <vscale x 32 x i8> @stepvector_nxv32i8() {
70; CHECK-LABEL: stepvector_nxv32i8:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
73; CHECK-NEXT:    vid.v v8
74; CHECK-NEXT:    ret
75  %v = call <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
76  ret <vscale x 32 x i8> %v
77}
78
79declare <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
80
81define <vscale x 64 x i8> @stepvector_nxv64i8() {
82; CHECK-LABEL: stepvector_nxv64i8:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
85; CHECK-NEXT:    vid.v v8
86; CHECK-NEXT:    ret
87  %v = call <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
88  ret <vscale x 64 x i8> %v
89}
90
91declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
92
93define <vscale x 1 x i16> @stepvector_nxv1i16() {
94; CHECK-LABEL: stepvector_nxv1i16:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
97; CHECK-NEXT:    vid.v v8
98; CHECK-NEXT:    ret
99  %v = call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
100  ret <vscale x 1 x i16> %v
101}
102
103declare <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
104
105define <vscale x 2 x i16> @stepvector_nxv2i16() {
106; CHECK-LABEL: stepvector_nxv2i16:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
109; CHECK-NEXT:    vid.v v8
110; CHECK-NEXT:    ret
111  %v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
112  ret <vscale x 2 x i16> %v
113}
114
115declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
116
117define <vscale x 4 x i16> @stepvector_nxv4i16() {
118; CHECK-LABEL: stepvector_nxv4i16:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
121; CHECK-NEXT:    vid.v v8
122; CHECK-NEXT:    ret
123  %v = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
124  ret <vscale x 4 x i16> %v
125}
126
127declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
128
129define <vscale x 8 x i16> @stepvector_nxv8i16() {
130; CHECK-LABEL: stepvector_nxv8i16:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
133; CHECK-NEXT:    vid.v v8
134; CHECK-NEXT:    ret
135  %v = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
136  ret <vscale x 8 x i16> %v
137}
138
139declare <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
140
141define <vscale x 16 x i16> @stepvector_nxv16i16() {
142; CHECK-LABEL: stepvector_nxv16i16:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
145; CHECK-NEXT:    vid.v v8
146; CHECK-NEXT:    ret
147  %v = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
148  ret <vscale x 16 x i16> %v
149}
150
151declare <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
152
153define <vscale x 32 x i16> @stepvector_nxv32i16() {
154; CHECK-LABEL: stepvector_nxv32i16:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
157; CHECK-NEXT:    vid.v v8
158; CHECK-NEXT:    ret
159  %v = call <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
160  ret <vscale x 32 x i16> %v
161}
162
163declare <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
164
165define <vscale x 1 x i32> @stepvector_nxv1i32() {
166; CHECK-LABEL: stepvector_nxv1i32:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
169; CHECK-NEXT:    vid.v v8
170; CHECK-NEXT:    ret
171  %v = call <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
172  ret <vscale x 1 x i32> %v
173}
174
175declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
176
177define <vscale x 2 x i32> @stepvector_nxv2i32() {
178; CHECK-LABEL: stepvector_nxv2i32:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
181; CHECK-NEXT:    vid.v v8
182; CHECK-NEXT:    ret
183  %v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
184  ret <vscale x 2 x i32> %v
185}
186
187declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
188
189define <vscale x 4 x i32> @stepvector_nxv4i32() {
190; CHECK-LABEL: stepvector_nxv4i32:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
193; CHECK-NEXT:    vid.v v8
194; CHECK-NEXT:    ret
195  %v = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
196  ret <vscale x 4 x i32> %v
197}
198
199declare <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
200
201define <vscale x 8 x i32> @stepvector_nxv8i32() {
202; CHECK-LABEL: stepvector_nxv8i32:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
205; CHECK-NEXT:    vid.v v8
206; CHECK-NEXT:    ret
207  %v = call <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
208  ret <vscale x 8 x i32> %v
209}
210
211declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
212
213define <vscale x 16 x i32> @stepvector_nxv16i32() {
214; CHECK-LABEL: stepvector_nxv16i32:
215; CHECK:       # %bb.0:
216; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
217; CHECK-NEXT:    vid.v v8
218; CHECK-NEXT:    ret
219  %v = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
220  ret <vscale x 16 x i32> %v
221}
222
223declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
224
225define <vscale x 1 x i64> @stepvector_nxv1i64() {
226; CHECK-LABEL: stepvector_nxv1i64:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
229; CHECK-NEXT:    vid.v v8
230; CHECK-NEXT:    ret
231  %v = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
232  ret <vscale x 1 x i64> %v
233}
234
235declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
236
237define <vscale x 2 x i64> @stepvector_nxv2i64() {
238; CHECK-LABEL: stepvector_nxv2i64:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
241; CHECK-NEXT:    vid.v v8
242; CHECK-NEXT:    ret
243  %v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
244  ret <vscale x 2 x i64> %v
245}
246
247declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
248
249define <vscale x 4 x i64> @stepvector_nxv4i64() {
250; CHECK-LABEL: stepvector_nxv4i64:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
253; CHECK-NEXT:    vid.v v8
254; CHECK-NEXT:    ret
255  %v = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
256  ret <vscale x 4 x i64> %v
257}
258
259declare <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
260
261define <vscale x 8 x i64> @stepvector_nxv8i64() {
262; CHECK-LABEL: stepvector_nxv8i64:
263; CHECK:       # %bb.0:
264; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
265; CHECK-NEXT:    vid.v v8
266; CHECK-NEXT:    ret
267  %v = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
268  ret <vscale x 8 x i64> %v
269}
270
271declare <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
272
273define <vscale x 16 x i64> @stepvector_nxv16i64() {
274; CHECK-LABEL: stepvector_nxv16i64:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    csrr a0, vlenb
277; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
278; CHECK-NEXT:    vid.v v8
279; CHECK-NEXT:    vadd.vx v16, v8, a0
280; CHECK-NEXT:    ret
281  %v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
282  ret <vscale x 16 x i64> %v
283}
284