1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt %s -S -riscv-codegenprepare -mtriple=riscv64 | FileCheck %s
3
4; Test that we can convert the %wide.trip.count zext to a sext. The dominating
5; condition %cmp3 ruled out %n being negative.
6define void @test1(ptr nocapture noundef %a, i32 noundef signext %n) {
7; CHECK-LABEL: @test1(
8; CHECK-NEXT:  entry:
9; CHECK-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[N:%.*]], 0
10; CHECK-NEXT:    br i1 [[CMP3]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
11; CHECK:       for.body.preheader:
12; CHECK-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[N]] to i64
13; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
14; CHECK:       for.cond.cleanup.loopexit:
15; CHECK-NEXT:    br label [[FOR_COND_CLEANUP]]
16; CHECK:       for.cond.cleanup:
17; CHECK-NEXT:    ret void
18; CHECK:       for.body:
19; CHECK-NEXT:    [[LSR_IV5:%.*]] = phi i64 [ [[WIDE_TRIP_COUNT]], [[FOR_BODY_PREHEADER]] ], [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY]] ]
20; CHECK-NEXT:    [[LSR_IV:%.*]] = phi ptr [ [[A:%.*]], [[FOR_BODY_PREHEADER]] ], [ [[UGLYGEP:%.*]], [[FOR_BODY]] ]
21; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LSR_IV]], align 4
22; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 4
23; CHECK-NEXT:    store i32 [[ADD]], ptr [[LSR_IV]], align 4
24; CHECK-NEXT:    [[UGLYGEP]] = getelementptr i8, ptr [[LSR_IV]], i64 4
25; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV5]], -1
26; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
27; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[FOR_BODY]]
28;
29entry:
30  %cmp3 = icmp sgt i32 %n, 0
31  br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
32
33for.body.preheader:                               ; preds = %entry
34  %wide.trip.count = zext i32 %n to i64
35  br label %for.body
36
37for.cond.cleanup.loopexit:                        ; preds = %for.body
38  br label %for.cond.cleanup
39
40for.cond.cleanup:                                 ; preds = %for.cond.cleanup.loopexit, %entry
41  ret void
42
43for.body:                                         ; preds = %for.body.preheader, %for.body
44  %lsr.iv5 = phi i64 [ %wide.trip.count, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
45  %lsr.iv = phi ptr [ %a, %for.body.preheader ], [ %uglygep, %for.body ]
46  %0 = load i32, ptr %lsr.iv, align 4
47  %add = add nsw i32 %0, 4
48  store i32 %add, ptr %lsr.iv, align 4
49  %uglygep = getelementptr i8, ptr %lsr.iv, i64 4
50  %lsr.iv.next = add nsw i64 %lsr.iv5, -1
51  %exitcond.not = icmp eq i64 %lsr.iv.next, 0
52  br i1 %exitcond.not, label %for.cond.cleanup.loopexit, label %for.body
53}
54
55; Make sure we convert the 4294967294 in for.body.preheader.new to -2 based on
56; the upper 33 bits being zero by the dominating condition %cmp3.
57define void @test2(ptr nocapture noundef %a, i32 noundef signext %n) {
58; CHECK-LABEL: @test2(
59; CHECK-NEXT:  entry:
60; CHECK-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[N:%.*]], 0
61; CHECK-NEXT:    br i1 [[CMP3]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
62; CHECK:       for.body.preheader:
63; CHECK-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[N]] to i64
64; CHECK-NEXT:    [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1
65; CHECK-NEXT:    [[TMP0:%.*]] = icmp eq i32 [[N]], 1
66; CHECK-NEXT:    br i1 [[TMP0]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY_PREHEADER_NEW:%.*]]
67; CHECK:       for.body.preheader.new:
68; CHECK-NEXT:    [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], -2
69; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
70; CHECK:       for.cond.cleanup.loopexit.unr-lcssa:
71; CHECK-NEXT:    [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[FOR_BODY]] ]
72; CHECK-NEXT:    [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0
73; CHECK-NEXT:    br i1 [[LCMP_MOD_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL:%.*]]
74; CHECK:       for.body.epil:
75; CHECK-NEXT:    [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV_UNR]]
76; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX_EPIL]], align 4
77; CHECK-NEXT:    [[ADD_EPIL:%.*]] = add nsw i32 [[TMP1]], 4
78; CHECK-NEXT:    store i32 [[ADD_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4
79; CHECK-NEXT:    br label [[FOR_COND_CLEANUP]]
80; CHECK:       for.cond.cleanup:
81; CHECK-NEXT:    ret void
82; CHECK:       for.body:
83; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1]], [[FOR_BODY]] ]
84; CHECK-NEXT:    [[NITER:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[FOR_BODY]] ]
85; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]
86; CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
87; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], 4
88; CHECK-NEXT:    store i32 [[ADD]], ptr [[ARRAYIDX]], align 4
89; CHECK-NEXT:    [[INDVARS_IV_NEXT:%.*]] = or i64 [[INDVARS_IV]], 1
90; CHECK-NEXT:    [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
91; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
92; CHECK-NEXT:    [[ADD_1:%.*]] = add nsw i32 [[TMP3]], 4
93; CHECK-NEXT:    store i32 [[ADD_1]], ptr [[ARRAYIDX_1]], align 4
94; CHECK-NEXT:    [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2
95; CHECK-NEXT:    [[NITER_NEXT_1]] = add i64 [[NITER]], 2
96; CHECK-NEXT:    [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
97; CHECK-NEXT:    br i1 [[NITER_NCMP_1]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]]
98;
99entry:
100  %cmp3 = icmp sgt i32 %n, 0
101  br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
102
103for.body.preheader:                               ; preds = %entry
104  %wide.trip.count = zext i32 %n to i64
105  %xtraiter = and i64 %wide.trip.count, 1
106  %0 = icmp eq i32 %n, 1
107  br i1 %0, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new
108
109for.body.preheader.new:                           ; preds = %for.body.preheader
110  %unroll_iter = and i64 %wide.trip.count, 4294967294
111  br label %for.body
112
113for.cond.cleanup.loopexit.unr-lcssa:              ; preds = %for.body, %for.body.preheader
114  %indvars.iv.unr = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next.1, %for.body ]
115  %lcmp.mod.not = icmp eq i64 %xtraiter, 0
116  br i1 %lcmp.mod.not, label %for.cond.cleanup, label %for.body.epil
117
118for.body.epil:                                    ; preds = %for.cond.cleanup.loopexit.unr-lcssa
119  %arrayidx.epil = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.unr
120  %1 = load i32, ptr %arrayidx.epil, align 4
121  %add.epil = add nsw i32 %1, 4
122  store i32 %add.epil, ptr %arrayidx.epil, align 4
123  br label %for.cond.cleanup
124
125for.cond.cleanup:                                 ; preds = %for.body.epil, %for.cond.cleanup.loopexit.unr-lcssa, %entry
126  ret void
127
128for.body:                                         ; preds = %for.body, %for.body.preheader.new
129  %indvars.iv = phi i64 [ 0, %for.body.preheader.new ], [ %indvars.iv.next.1, %for.body ]
130  %niter = phi i64 [ 0, %for.body.preheader.new ], [ %niter.next.1, %for.body ]
131  %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
132  %2 = load i32, ptr %arrayidx, align 4
133  %add = add nsw i32 %2, 4
134  store i32 %add, ptr %arrayidx, align 4
135  %indvars.iv.next = or i64 %indvars.iv, 1
136  %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
137  %3 = load i32, ptr %arrayidx.1, align 4
138  %add.1 = add nsw i32 %3, 4
139  store i32 %add.1, ptr %arrayidx.1, align 4
140  %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
141  %niter.next.1 = add i64 %niter, 2
142  %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
143  br i1 %niter.ncmp.1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body
144}
145