1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 -verify-machineinstrs | FileCheck %s -check-prefixes=RV32
3; RUN: llc < %s -mtriple=riscv64 -verify-machineinstrs | FileCheck %s -check-prefixes=RV64
4
5; Test case:
6; - `A[row]` is loop invariant and should be hoisted up to preheader
7; FIXME: RV32 is working as expected, but RV64 doesn't
8
9; The following LLVM IR simulates:
10; int A[16][16];
11; void test(int row, int N) {
12; 	for (int i=0; i<N; ++I) {
13; 		A[row][i+1] = 4;
14; 		A[row][i+2] = 5;
15; 	}
16; }
17
18; After LSR:
19; int A[16][16];
20; void test(int row, int N) {
21; 	for (int *ptr = A[row][2]; N>0; N--) {
22; 		*(ptr-1) = 4;
23; 		*(ptr) = 5;
24; 		++ptr;
25; 	}
26; }
27
28@A = internal global [16 x [16 x i32]] zeroinitializer, align 32		; <[16 x [16 x i32]]*> [#uses=2]
29
30define void @test(i32 signext %row, i32 signext %N.in) nounwind {
31; RV32-LABEL: test:
32; RV32:       # %bb.0: # %entry
33; RV32-NEXT:    blez a1, .LBB0_3
34; RV32-NEXT:  # %bb.1: # %cond_true.preheader
35; RV32-NEXT:    slli a0, a0, 6
36; RV32-NEXT:    lui a2, %hi(A)
37; RV32-NEXT:    addi a2, a2, %lo(A)
38; RV32-NEXT:    add a0, a2, a0
39; RV32-NEXT:    addi a0, a0, 8
40; RV32-NEXT:    li a2, 4
41; RV32-NEXT:    li a3, 5
42; RV32-NEXT:  .LBB0_2: # %cond_true
43; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
44; RV32-NEXT:    sw a2, -4(a0)
45; RV32-NEXT:    sw a3, 0(a0)
46; RV32-NEXT:    addi a1, a1, -1
47; RV32-NEXT:    addi a0, a0, 4
48; RV32-NEXT:    bnez a1, .LBB0_2
49; RV32-NEXT:  .LBB0_3: # %return
50; RV32-NEXT:    ret
51;
52; RV64-LABEL: test:
53; RV64:       # %bb.0: # %entry
54; RV64-NEXT:    blez a1, .LBB0_3
55; RV64-NEXT:  # %bb.1: # %cond_true.preheader
56; RV64-NEXT:    li a4, 0
57; RV64-NEXT:    slli a0, a0, 6
58; RV64-NEXT:    lui a2, %hi(A)
59; RV64-NEXT:    addi a2, a2, %lo(A)
60; RV64-NEXT:    add a0, a2, a0
61; RV64-NEXT:    li a2, 4
62; RV64-NEXT:    li a3, 5
63; RV64-NEXT:  .LBB0_2: # %cond_true
64; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
65; RV64-NEXT:    addiw a5, a4, 1
66; RV64-NEXT:    slli a6, a5, 2
67; RV64-NEXT:    add a6, a0, a6
68; RV64-NEXT:    sw a2, 0(a6)
69; RV64-NEXT:    addiw a4, a4, 2
70; RV64-NEXT:    slli a4, a4, 2
71; RV64-NEXT:    add a4, a0, a4
72; RV64-NEXT:    sw a3, 0(a4)
73; RV64-NEXT:    mv a4, a5
74; RV64-NEXT:    bne a5, a1, .LBB0_2
75; RV64-NEXT:  .LBB0_3: # %return
76; RV64-NEXT:    ret
77entry:
78	%N = bitcast i32 %N.in to i32
79	%tmp5 = icmp sgt i32 %N.in, 0
80	br i1 %tmp5, label %cond_true, label %return
81
82cond_true:
83	%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ]
84	%tmp2 = add i32 %indvar, 1
85	%tmp = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2
86	store i32 4, i32* %tmp
87	%tmp5.upgrd.1 = add i32 %indvar, 2
88	%tmp7 = getelementptr [16 x [16 x i32]], [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1
89	store i32 5, i32* %tmp7
90	%indvar.next = add i32 %indvar, 1
91	%exitcond = icmp eq i32 %indvar.next, %N
92	br i1 %exitcond, label %return, label %cond_true
93
94return:
95	ret void
96}
97