1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV64I 6; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zba \ 7; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBA 8; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbb \ 9; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBB 10; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbs \ 11; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBS 12 13; Materializing constants 14 15; TODO: It would be preferable if anyext constant returns were sign rather 16; than zero extended. See PR39092. For now, mark returns as explicitly signext 17; (this matches what Clang would generate for equivalent C/C++ anyway). 18 19define signext i32 @zero() nounwind { 20; RV32I-LABEL: zero: 21; RV32I: # %bb.0: 22; RV32I-NEXT: li a0, 0 23; RV32I-NEXT: ret 24; 25; RV64I-LABEL: zero: 26; RV64I: # %bb.0: 27; RV64I-NEXT: li a0, 0 28; RV64I-NEXT: ret 29; 30; RV64IZBA-LABEL: zero: 31; RV64IZBA: # %bb.0: 32; RV64IZBA-NEXT: li a0, 0 33; RV64IZBA-NEXT: ret 34; 35; RV64IZBB-LABEL: zero: 36; RV64IZBB: # %bb.0: 37; RV64IZBB-NEXT: li a0, 0 38; RV64IZBB-NEXT: ret 39; 40; RV64IZBS-LABEL: zero: 41; RV64IZBS: # %bb.0: 42; RV64IZBS-NEXT: li a0, 0 43; RV64IZBS-NEXT: ret 44 ret i32 0 45} 46 47define signext i32 @pos_small() nounwind { 48; RV32I-LABEL: pos_small: 49; RV32I: # %bb.0: 50; RV32I-NEXT: li a0, 2047 51; RV32I-NEXT: ret 52; 53; RV64I-LABEL: pos_small: 54; RV64I: # %bb.0: 55; RV64I-NEXT: li a0, 2047 56; RV64I-NEXT: ret 57; 58; RV64IZBA-LABEL: pos_small: 59; RV64IZBA: # %bb.0: 60; RV64IZBA-NEXT: li a0, 2047 61; RV64IZBA-NEXT: ret 62; 63; RV64IZBB-LABEL: pos_small: 64; RV64IZBB: # %bb.0: 65; RV64IZBB-NEXT: li a0, 2047 66; RV64IZBB-NEXT: ret 67; 68; RV64IZBS-LABEL: pos_small: 69; RV64IZBS: # %bb.0: 70; RV64IZBS-NEXT: li a0, 2047 71; RV64IZBS-NEXT: ret 72 ret i32 2047 73} 74 75define signext i32 @neg_small() nounwind { 76; RV32I-LABEL: neg_small: 77; RV32I: # %bb.0: 78; RV32I-NEXT: li a0, -2048 79; RV32I-NEXT: ret 80; 81; RV64I-LABEL: neg_small: 82; RV64I: # %bb.0: 83; RV64I-NEXT: li a0, -2048 84; RV64I-NEXT: ret 85; 86; RV64IZBA-LABEL: neg_small: 87; RV64IZBA: # %bb.0: 88; RV64IZBA-NEXT: li a0, -2048 89; RV64IZBA-NEXT: ret 90; 91; RV64IZBB-LABEL: neg_small: 92; RV64IZBB: # %bb.0: 93; RV64IZBB-NEXT: li a0, -2048 94; RV64IZBB-NEXT: ret 95; 96; RV64IZBS-LABEL: neg_small: 97; RV64IZBS: # %bb.0: 98; RV64IZBS-NEXT: li a0, -2048 99; RV64IZBS-NEXT: ret 100 ret i32 -2048 101} 102 103define signext i32 @pos_i32() nounwind { 104; RV32I-LABEL: pos_i32: 105; RV32I: # %bb.0: 106; RV32I-NEXT: lui a0, 423811 107; RV32I-NEXT: addi a0, a0, -1297 108; RV32I-NEXT: ret 109; 110; RV64I-LABEL: pos_i32: 111; RV64I: # %bb.0: 112; RV64I-NEXT: lui a0, 423811 113; RV64I-NEXT: addiw a0, a0, -1297 114; RV64I-NEXT: ret 115; 116; RV64IZBA-LABEL: pos_i32: 117; RV64IZBA: # %bb.0: 118; RV64IZBA-NEXT: lui a0, 423811 119; RV64IZBA-NEXT: addiw a0, a0, -1297 120; RV64IZBA-NEXT: ret 121; 122; RV64IZBB-LABEL: pos_i32: 123; RV64IZBB: # %bb.0: 124; RV64IZBB-NEXT: lui a0, 423811 125; RV64IZBB-NEXT: addiw a0, a0, -1297 126; RV64IZBB-NEXT: ret 127; 128; RV64IZBS-LABEL: pos_i32: 129; RV64IZBS: # %bb.0: 130; RV64IZBS-NEXT: lui a0, 423811 131; RV64IZBS-NEXT: addiw a0, a0, -1297 132; RV64IZBS-NEXT: ret 133 ret i32 1735928559 134} 135 136define signext i32 @neg_i32() nounwind { 137; RV32I-LABEL: neg_i32: 138; RV32I: # %bb.0: 139; RV32I-NEXT: lui a0, 912092 140; RV32I-NEXT: addi a0, a0, -273 141; RV32I-NEXT: ret 142; 143; RV64I-LABEL: neg_i32: 144; RV64I: # %bb.0: 145; RV64I-NEXT: lui a0, 912092 146; RV64I-NEXT: addiw a0, a0, -273 147; RV64I-NEXT: ret 148; 149; RV64IZBA-LABEL: neg_i32: 150; RV64IZBA: # %bb.0: 151; RV64IZBA-NEXT: lui a0, 912092 152; RV64IZBA-NEXT: addiw a0, a0, -273 153; RV64IZBA-NEXT: ret 154; 155; RV64IZBB-LABEL: neg_i32: 156; RV64IZBB: # %bb.0: 157; RV64IZBB-NEXT: lui a0, 912092 158; RV64IZBB-NEXT: addiw a0, a0, -273 159; RV64IZBB-NEXT: ret 160; 161; RV64IZBS-LABEL: neg_i32: 162; RV64IZBS: # %bb.0: 163; RV64IZBS-NEXT: lui a0, 912092 164; RV64IZBS-NEXT: addiw a0, a0, -273 165; RV64IZBS-NEXT: ret 166 ret i32 -559038737 167} 168 169define signext i32 @pos_i32_hi20_only() nounwind { 170; RV32I-LABEL: pos_i32_hi20_only: 171; RV32I: # %bb.0: 172; RV32I-NEXT: lui a0, 16 173; RV32I-NEXT: ret 174; 175; RV64I-LABEL: pos_i32_hi20_only: 176; RV64I: # %bb.0: 177; RV64I-NEXT: lui a0, 16 178; RV64I-NEXT: ret 179; 180; RV64IZBA-LABEL: pos_i32_hi20_only: 181; RV64IZBA: # %bb.0: 182; RV64IZBA-NEXT: lui a0, 16 183; RV64IZBA-NEXT: ret 184; 185; RV64IZBB-LABEL: pos_i32_hi20_only: 186; RV64IZBB: # %bb.0: 187; RV64IZBB-NEXT: lui a0, 16 188; RV64IZBB-NEXT: ret 189; 190; RV64IZBS-LABEL: pos_i32_hi20_only: 191; RV64IZBS: # %bb.0: 192; RV64IZBS-NEXT: lui a0, 16 193; RV64IZBS-NEXT: ret 194 ret i32 65536 ; 0x10000 195} 196 197define signext i32 @neg_i32_hi20_only() nounwind { 198; RV32I-LABEL: neg_i32_hi20_only: 199; RV32I: # %bb.0: 200; RV32I-NEXT: lui a0, 1048560 201; RV32I-NEXT: ret 202; 203; RV64I-LABEL: neg_i32_hi20_only: 204; RV64I: # %bb.0: 205; RV64I-NEXT: lui a0, 1048560 206; RV64I-NEXT: ret 207; 208; RV64IZBA-LABEL: neg_i32_hi20_only: 209; RV64IZBA: # %bb.0: 210; RV64IZBA-NEXT: lui a0, 1048560 211; RV64IZBA-NEXT: ret 212; 213; RV64IZBB-LABEL: neg_i32_hi20_only: 214; RV64IZBB: # %bb.0: 215; RV64IZBB-NEXT: lui a0, 1048560 216; RV64IZBB-NEXT: ret 217; 218; RV64IZBS-LABEL: neg_i32_hi20_only: 219; RV64IZBS: # %bb.0: 220; RV64IZBS-NEXT: lui a0, 1048560 221; RV64IZBS-NEXT: ret 222 ret i32 -65536 ; -0x10000 223} 224 225; This can be materialized with ADDI+SLLI, improving compressibility. 226 227define signext i32 @imm_left_shifted_addi() nounwind { 228; RV32I-LABEL: imm_left_shifted_addi: 229; RV32I: # %bb.0: 230; RV32I-NEXT: lui a0, 32 231; RV32I-NEXT: addi a0, a0, -64 232; RV32I-NEXT: ret 233; 234; RV64I-LABEL: imm_left_shifted_addi: 235; RV64I: # %bb.0: 236; RV64I-NEXT: lui a0, 32 237; RV64I-NEXT: addiw a0, a0, -64 238; RV64I-NEXT: ret 239; 240; RV64IZBA-LABEL: imm_left_shifted_addi: 241; RV64IZBA: # %bb.0: 242; RV64IZBA-NEXT: lui a0, 32 243; RV64IZBA-NEXT: addiw a0, a0, -64 244; RV64IZBA-NEXT: ret 245; 246; RV64IZBB-LABEL: imm_left_shifted_addi: 247; RV64IZBB: # %bb.0: 248; RV64IZBB-NEXT: lui a0, 32 249; RV64IZBB-NEXT: addiw a0, a0, -64 250; RV64IZBB-NEXT: ret 251; 252; RV64IZBS-LABEL: imm_left_shifted_addi: 253; RV64IZBS: # %bb.0: 254; RV64IZBS-NEXT: lui a0, 32 255; RV64IZBS-NEXT: addiw a0, a0, -64 256; RV64IZBS-NEXT: ret 257 ret i32 131008 ; 0x1FFC0 258} 259 260; This can be materialized with ADDI+SRLI, improving compressibility. 261 262define signext i32 @imm_right_shifted_addi() nounwind { 263; RV32I-LABEL: imm_right_shifted_addi: 264; RV32I: # %bb.0: 265; RV32I-NEXT: lui a0, 524288 266; RV32I-NEXT: addi a0, a0, -1 267; RV32I-NEXT: ret 268; 269; RV64I-LABEL: imm_right_shifted_addi: 270; RV64I: # %bb.0: 271; RV64I-NEXT: lui a0, 524288 272; RV64I-NEXT: addiw a0, a0, -1 273; RV64I-NEXT: ret 274; 275; RV64IZBA-LABEL: imm_right_shifted_addi: 276; RV64IZBA: # %bb.0: 277; RV64IZBA-NEXT: lui a0, 524288 278; RV64IZBA-NEXT: addiw a0, a0, -1 279; RV64IZBA-NEXT: ret 280; 281; RV64IZBB-LABEL: imm_right_shifted_addi: 282; RV64IZBB: # %bb.0: 283; RV64IZBB-NEXT: lui a0, 524288 284; RV64IZBB-NEXT: addiw a0, a0, -1 285; RV64IZBB-NEXT: ret 286; 287; RV64IZBS-LABEL: imm_right_shifted_addi: 288; RV64IZBS: # %bb.0: 289; RV64IZBS-NEXT: lui a0, 524288 290; RV64IZBS-NEXT: addiw a0, a0, -1 291; RV64IZBS-NEXT: ret 292 ret i32 2147483647 ; 0x7FFFFFFF 293} 294 295; This can be materialized with LUI+SRLI, improving compressibility. 296 297define signext i32 @imm_right_shifted_lui() nounwind { 298; RV32I-LABEL: imm_right_shifted_lui: 299; RV32I: # %bb.0: 300; RV32I-NEXT: lui a0, 56 301; RV32I-NEXT: addi a0, a0, 580 302; RV32I-NEXT: ret 303; 304; RV64I-LABEL: imm_right_shifted_lui: 305; RV64I: # %bb.0: 306; RV64I-NEXT: lui a0, 56 307; RV64I-NEXT: addiw a0, a0, 580 308; RV64I-NEXT: ret 309; 310; RV64IZBA-LABEL: imm_right_shifted_lui: 311; RV64IZBA: # %bb.0: 312; RV64IZBA-NEXT: lui a0, 56 313; RV64IZBA-NEXT: addiw a0, a0, 580 314; RV64IZBA-NEXT: ret 315; 316; RV64IZBB-LABEL: imm_right_shifted_lui: 317; RV64IZBB: # %bb.0: 318; RV64IZBB-NEXT: lui a0, 56 319; RV64IZBB-NEXT: addiw a0, a0, 580 320; RV64IZBB-NEXT: ret 321; 322; RV64IZBS-LABEL: imm_right_shifted_lui: 323; RV64IZBS: # %bb.0: 324; RV64IZBS-NEXT: lui a0, 56 325; RV64IZBS-NEXT: addiw a0, a0, 580 326; RV64IZBS-NEXT: ret 327 ret i32 229956 ; 0x38244 328} 329 330define i64 @imm64_1() nounwind { 331; RV32I-LABEL: imm64_1: 332; RV32I: # %bb.0: 333; RV32I-NEXT: lui a0, 524288 334; RV32I-NEXT: li a1, 0 335; RV32I-NEXT: ret 336; 337; RV64I-LABEL: imm64_1: 338; RV64I: # %bb.0: 339; RV64I-NEXT: li a0, 1 340; RV64I-NEXT: slli a0, a0, 31 341; RV64I-NEXT: ret 342; 343; RV64IZBA-LABEL: imm64_1: 344; RV64IZBA: # %bb.0: 345; RV64IZBA-NEXT: li a0, 1 346; RV64IZBA-NEXT: slli a0, a0, 31 347; RV64IZBA-NEXT: ret 348; 349; RV64IZBB-LABEL: imm64_1: 350; RV64IZBB: # %bb.0: 351; RV64IZBB-NEXT: li a0, 1 352; RV64IZBB-NEXT: slli a0, a0, 31 353; RV64IZBB-NEXT: ret 354; 355; RV64IZBS-LABEL: imm64_1: 356; RV64IZBS: # %bb.0: 357; RV64IZBS-NEXT: li a0, 1 358; RV64IZBS-NEXT: slli a0, a0, 31 359; RV64IZBS-NEXT: ret 360 ret i64 2147483648 ; 0x8000_0000 361} 362 363define i64 @imm64_2() nounwind { 364; RV32I-LABEL: imm64_2: 365; RV32I: # %bb.0: 366; RV32I-NEXT: li a0, -1 367; RV32I-NEXT: li a1, 0 368; RV32I-NEXT: ret 369; 370; RV64I-LABEL: imm64_2: 371; RV64I: # %bb.0: 372; RV64I-NEXT: li a0, -1 373; RV64I-NEXT: srli a0, a0, 32 374; RV64I-NEXT: ret 375; 376; RV64IZBA-LABEL: imm64_2: 377; RV64IZBA: # %bb.0: 378; RV64IZBA-NEXT: li a0, -1 379; RV64IZBA-NEXT: srli a0, a0, 32 380; RV64IZBA-NEXT: ret 381; 382; RV64IZBB-LABEL: imm64_2: 383; RV64IZBB: # %bb.0: 384; RV64IZBB-NEXT: li a0, -1 385; RV64IZBB-NEXT: srli a0, a0, 32 386; RV64IZBB-NEXT: ret 387; 388; RV64IZBS-LABEL: imm64_2: 389; RV64IZBS: # %bb.0: 390; RV64IZBS-NEXT: li a0, -1 391; RV64IZBS-NEXT: srli a0, a0, 32 392; RV64IZBS-NEXT: ret 393 ret i64 4294967295 ; 0xFFFF_FFFF 394} 395 396define i64 @imm64_3() nounwind { 397; RV32I-LABEL: imm64_3: 398; RV32I: # %bb.0: 399; RV32I-NEXT: li a1, 1 400; RV32I-NEXT: li a0, 0 401; RV32I-NEXT: ret 402; 403; RV64I-LABEL: imm64_3: 404; RV64I: # %bb.0: 405; RV64I-NEXT: li a0, 1 406; RV64I-NEXT: slli a0, a0, 32 407; RV64I-NEXT: ret 408; 409; RV64IZBA-LABEL: imm64_3: 410; RV64IZBA: # %bb.0: 411; RV64IZBA-NEXT: li a0, 1 412; RV64IZBA-NEXT: slli a0, a0, 32 413; RV64IZBA-NEXT: ret 414; 415; RV64IZBB-LABEL: imm64_3: 416; RV64IZBB: # %bb.0: 417; RV64IZBB-NEXT: li a0, 1 418; RV64IZBB-NEXT: slli a0, a0, 32 419; RV64IZBB-NEXT: ret 420; 421; RV64IZBS-LABEL: imm64_3: 422; RV64IZBS: # %bb.0: 423; RV64IZBS-NEXT: li a0, 1 424; RV64IZBS-NEXT: slli a0, a0, 32 425; RV64IZBS-NEXT: ret 426 ret i64 4294967296 ; 0x1_0000_0000 427} 428 429define i64 @imm64_4() nounwind { 430; RV32I-LABEL: imm64_4: 431; RV32I: # %bb.0: 432; RV32I-NEXT: lui a1, 524288 433; RV32I-NEXT: li a0, 0 434; RV32I-NEXT: ret 435; 436; RV64I-LABEL: imm64_4: 437; RV64I: # %bb.0: 438; RV64I-NEXT: li a0, -1 439; RV64I-NEXT: slli a0, a0, 63 440; RV64I-NEXT: ret 441; 442; RV64IZBA-LABEL: imm64_4: 443; RV64IZBA: # %bb.0: 444; RV64IZBA-NEXT: li a0, -1 445; RV64IZBA-NEXT: slli a0, a0, 63 446; RV64IZBA-NEXT: ret 447; 448; RV64IZBB-LABEL: imm64_4: 449; RV64IZBB: # %bb.0: 450; RV64IZBB-NEXT: li a0, -1 451; RV64IZBB-NEXT: slli a0, a0, 63 452; RV64IZBB-NEXT: ret 453; 454; RV64IZBS-LABEL: imm64_4: 455; RV64IZBS: # %bb.0: 456; RV64IZBS-NEXT: li a0, -1 457; RV64IZBS-NEXT: slli a0, a0, 63 458; RV64IZBS-NEXT: ret 459 ret i64 9223372036854775808 ; 0x8000_0000_0000_0000 460} 461 462define i64 @imm64_5() nounwind { 463; RV32I-LABEL: imm64_5: 464; RV32I: # %bb.0: 465; RV32I-NEXT: lui a1, 524288 466; RV32I-NEXT: li a0, 0 467; RV32I-NEXT: ret 468; 469; RV64I-LABEL: imm64_5: 470; RV64I: # %bb.0: 471; RV64I-NEXT: li a0, -1 472; RV64I-NEXT: slli a0, a0, 63 473; RV64I-NEXT: ret 474; 475; RV64IZBA-LABEL: imm64_5: 476; RV64IZBA: # %bb.0: 477; RV64IZBA-NEXT: li a0, -1 478; RV64IZBA-NEXT: slli a0, a0, 63 479; RV64IZBA-NEXT: ret 480; 481; RV64IZBB-LABEL: imm64_5: 482; RV64IZBB: # %bb.0: 483; RV64IZBB-NEXT: li a0, -1 484; RV64IZBB-NEXT: slli a0, a0, 63 485; RV64IZBB-NEXT: ret 486; 487; RV64IZBS-LABEL: imm64_5: 488; RV64IZBS: # %bb.0: 489; RV64IZBS-NEXT: li a0, -1 490; RV64IZBS-NEXT: slli a0, a0, 63 491; RV64IZBS-NEXT: ret 492 ret i64 -9223372036854775808 ; 0x8000_0000_0000_0000 493} 494 495define i64 @imm64_6() nounwind { 496; RV32I-LABEL: imm64_6: 497; RV32I: # %bb.0: 498; RV32I-NEXT: lui a0, 74565 499; RV32I-NEXT: addi a1, a0, 1656 500; RV32I-NEXT: li a0, 0 501; RV32I-NEXT: ret 502; 503; RV64I-LABEL: imm64_6: 504; RV64I: # %bb.0: 505; RV64I-NEXT: lui a0, 9321 506; RV64I-NEXT: addiw a0, a0, -1329 507; RV64I-NEXT: slli a0, a0, 35 508; RV64I-NEXT: ret 509; 510; RV64IZBA-LABEL: imm64_6: 511; RV64IZBA: # %bb.0: 512; RV64IZBA-NEXT: lui a0, 9321 513; RV64IZBA-NEXT: addiw a0, a0, -1329 514; RV64IZBA-NEXT: slli a0, a0, 35 515; RV64IZBA-NEXT: ret 516; 517; RV64IZBB-LABEL: imm64_6: 518; RV64IZBB: # %bb.0: 519; RV64IZBB-NEXT: lui a0, 9321 520; RV64IZBB-NEXT: addiw a0, a0, -1329 521; RV64IZBB-NEXT: slli a0, a0, 35 522; RV64IZBB-NEXT: ret 523; 524; RV64IZBS-LABEL: imm64_6: 525; RV64IZBS: # %bb.0: 526; RV64IZBS-NEXT: lui a0, 9321 527; RV64IZBS-NEXT: addiw a0, a0, -1329 528; RV64IZBS-NEXT: slli a0, a0, 35 529; RV64IZBS-NEXT: ret 530 ret i64 1311768464867721216 ; 0x1234_5678_0000_0000 531} 532 533define i64 @imm64_7() nounwind { 534; RV32I-LABEL: imm64_7: 535; RV32I: # %bb.0: 536; RV32I-NEXT: lui a0, 45056 537; RV32I-NEXT: addi a0, a0, 15 538; RV32I-NEXT: lui a1, 458752 539; RV32I-NEXT: ret 540; 541; RV64I-LABEL: imm64_7: 542; RV64I: # %bb.0: 543; RV64I-NEXT: li a0, 7 544; RV64I-NEXT: slli a0, a0, 36 545; RV64I-NEXT: addi a0, a0, 11 546; RV64I-NEXT: slli a0, a0, 24 547; RV64I-NEXT: addi a0, a0, 15 548; RV64I-NEXT: ret 549; 550; RV64IZBA-LABEL: imm64_7: 551; RV64IZBA: # %bb.0: 552; RV64IZBA-NEXT: li a0, 7 553; RV64IZBA-NEXT: slli a0, a0, 36 554; RV64IZBA-NEXT: addi a0, a0, 11 555; RV64IZBA-NEXT: slli a0, a0, 24 556; RV64IZBA-NEXT: addi a0, a0, 15 557; RV64IZBA-NEXT: ret 558; 559; RV64IZBB-LABEL: imm64_7: 560; RV64IZBB: # %bb.0: 561; RV64IZBB-NEXT: li a0, 7 562; RV64IZBB-NEXT: slli a0, a0, 36 563; RV64IZBB-NEXT: addi a0, a0, 11 564; RV64IZBB-NEXT: slli a0, a0, 24 565; RV64IZBB-NEXT: addi a0, a0, 15 566; RV64IZBB-NEXT: ret 567; 568; RV64IZBS-LABEL: imm64_7: 569; RV64IZBS: # %bb.0: 570; RV64IZBS-NEXT: li a0, 7 571; RV64IZBS-NEXT: slli a0, a0, 36 572; RV64IZBS-NEXT: addi a0, a0, 11 573; RV64IZBS-NEXT: slli a0, a0, 24 574; RV64IZBS-NEXT: addi a0, a0, 15 575; RV64IZBS-NEXT: ret 576 ret i64 8070450532432478223 ; 0x7000_0000_0B00_000F 577} 578 579; TODO: it can be preferable to put constants that are expensive to materialise 580; into the constant pool, especially for -Os. 581define i64 @imm64_8() nounwind { 582; RV32I-LABEL: imm64_8: 583; RV32I: # %bb.0: 584; RV32I-NEXT: lui a0, 633806 585; RV32I-NEXT: addi a0, a0, -272 586; RV32I-NEXT: lui a1, 74565 587; RV32I-NEXT: addi a1, a1, 1656 588; RV32I-NEXT: ret 589; 590; RV64I-LABEL: imm64_8: 591; RV64I: # %bb.0: 592; RV64I-NEXT: lui a0, 583 593; RV64I-NEXT: addiw a0, a0, -1875 594; RV64I-NEXT: slli a0, a0, 14 595; RV64I-NEXT: addi a0, a0, -947 596; RV64I-NEXT: slli a0, a0, 12 597; RV64I-NEXT: addi a0, a0, 1511 598; RV64I-NEXT: slli a0, a0, 13 599; RV64I-NEXT: addi a0, a0, -272 600; RV64I-NEXT: ret 601; 602; RV64IZBA-LABEL: imm64_8: 603; RV64IZBA: # %bb.0: 604; RV64IZBA-NEXT: lui a0, 583 605; RV64IZBA-NEXT: addiw a0, a0, -1875 606; RV64IZBA-NEXT: slli a0, a0, 14 607; RV64IZBA-NEXT: addi a0, a0, -947 608; RV64IZBA-NEXT: slli a0, a0, 12 609; RV64IZBA-NEXT: addi a0, a0, 1511 610; RV64IZBA-NEXT: slli a0, a0, 13 611; RV64IZBA-NEXT: addi a0, a0, -272 612; RV64IZBA-NEXT: ret 613; 614; RV64IZBB-LABEL: imm64_8: 615; RV64IZBB: # %bb.0: 616; RV64IZBB-NEXT: lui a0, 583 617; RV64IZBB-NEXT: addiw a0, a0, -1875 618; RV64IZBB-NEXT: slli a0, a0, 14 619; RV64IZBB-NEXT: addi a0, a0, -947 620; RV64IZBB-NEXT: slli a0, a0, 12 621; RV64IZBB-NEXT: addi a0, a0, 1511 622; RV64IZBB-NEXT: slli a0, a0, 13 623; RV64IZBB-NEXT: addi a0, a0, -272 624; RV64IZBB-NEXT: ret 625; 626; RV64IZBS-LABEL: imm64_8: 627; RV64IZBS: # %bb.0: 628; RV64IZBS-NEXT: lui a0, 583 629; RV64IZBS-NEXT: addiw a0, a0, -1875 630; RV64IZBS-NEXT: slli a0, a0, 14 631; RV64IZBS-NEXT: addi a0, a0, -947 632; RV64IZBS-NEXT: slli a0, a0, 12 633; RV64IZBS-NEXT: addi a0, a0, 1511 634; RV64IZBS-NEXT: slli a0, a0, 13 635; RV64IZBS-NEXT: addi a0, a0, -272 636; RV64IZBS-NEXT: ret 637 ret i64 1311768467463790320 ; 0x1234_5678_9ABC_DEF0 638} 639 640define i64 @imm64_9() nounwind { 641; RV32I-LABEL: imm64_9: 642; RV32I: # %bb.0: 643; RV32I-NEXT: li a0, -1 644; RV32I-NEXT: li a1, -1 645; RV32I-NEXT: ret 646; 647; RV64I-LABEL: imm64_9: 648; RV64I: # %bb.0: 649; RV64I-NEXT: li a0, -1 650; RV64I-NEXT: ret 651; 652; RV64IZBA-LABEL: imm64_9: 653; RV64IZBA: # %bb.0: 654; RV64IZBA-NEXT: li a0, -1 655; RV64IZBA-NEXT: ret 656; 657; RV64IZBB-LABEL: imm64_9: 658; RV64IZBB: # %bb.0: 659; RV64IZBB-NEXT: li a0, -1 660; RV64IZBB-NEXT: ret 661; 662; RV64IZBS-LABEL: imm64_9: 663; RV64IZBS: # %bb.0: 664; RV64IZBS-NEXT: li a0, -1 665; RV64IZBS-NEXT: ret 666 ret i64 -1 667} 668 669; Various cases where extraneous ADDIs can be inserted where a (left shifted) 670; LUI suffices. 671 672define i64 @imm_left_shifted_lui_1() nounwind { 673; RV32I-LABEL: imm_left_shifted_lui_1: 674; RV32I: # %bb.0: 675; RV32I-NEXT: lui a0, 524290 676; RV32I-NEXT: li a1, 0 677; RV32I-NEXT: ret 678; 679; RV64I-LABEL: imm_left_shifted_lui_1: 680; RV64I: # %bb.0: 681; RV64I-NEXT: lui a0, 262145 682; RV64I-NEXT: slli a0, a0, 1 683; RV64I-NEXT: ret 684; 685; RV64IZBA-LABEL: imm_left_shifted_lui_1: 686; RV64IZBA: # %bb.0: 687; RV64IZBA-NEXT: lui a0, 262145 688; RV64IZBA-NEXT: slli a0, a0, 1 689; RV64IZBA-NEXT: ret 690; 691; RV64IZBB-LABEL: imm_left_shifted_lui_1: 692; RV64IZBB: # %bb.0: 693; RV64IZBB-NEXT: lui a0, 262145 694; RV64IZBB-NEXT: slli a0, a0, 1 695; RV64IZBB-NEXT: ret 696; 697; RV64IZBS-LABEL: imm_left_shifted_lui_1: 698; RV64IZBS: # %bb.0: 699; RV64IZBS-NEXT: lui a0, 262145 700; RV64IZBS-NEXT: slli a0, a0, 1 701; RV64IZBS-NEXT: ret 702 ret i64 2147491840 ; 0x8000_2000 703} 704 705define i64 @imm_left_shifted_lui_2() nounwind { 706; RV32I-LABEL: imm_left_shifted_lui_2: 707; RV32I: # %bb.0: 708; RV32I-NEXT: lui a0, 4 709; RV32I-NEXT: li a1, 1 710; RV32I-NEXT: ret 711; 712; RV64I-LABEL: imm_left_shifted_lui_2: 713; RV64I: # %bb.0: 714; RV64I-NEXT: lui a0, 262145 715; RV64I-NEXT: slli a0, a0, 2 716; RV64I-NEXT: ret 717; 718; RV64IZBA-LABEL: imm_left_shifted_lui_2: 719; RV64IZBA: # %bb.0: 720; RV64IZBA-NEXT: lui a0, 262145 721; RV64IZBA-NEXT: slli a0, a0, 2 722; RV64IZBA-NEXT: ret 723; 724; RV64IZBB-LABEL: imm_left_shifted_lui_2: 725; RV64IZBB: # %bb.0: 726; RV64IZBB-NEXT: lui a0, 262145 727; RV64IZBB-NEXT: slli a0, a0, 2 728; RV64IZBB-NEXT: ret 729; 730; RV64IZBS-LABEL: imm_left_shifted_lui_2: 731; RV64IZBS: # %bb.0: 732; RV64IZBS-NEXT: lui a0, 262145 733; RV64IZBS-NEXT: slli a0, a0, 2 734; RV64IZBS-NEXT: ret 735 ret i64 4294983680 ; 0x1_0000_4000 736} 737 738define i64 @imm_left_shifted_lui_3() nounwind { 739; RV32I-LABEL: imm_left_shifted_lui_3: 740; RV32I: # %bb.0: 741; RV32I-NEXT: lui a0, 1 742; RV32I-NEXT: addi a1, a0, 1 743; RV32I-NEXT: li a0, 0 744; RV32I-NEXT: ret 745; 746; RV64I-LABEL: imm_left_shifted_lui_3: 747; RV64I: # %bb.0: 748; RV64I-NEXT: lui a0, 4097 749; RV64I-NEXT: slli a0, a0, 20 750; RV64I-NEXT: ret 751; 752; RV64IZBA-LABEL: imm_left_shifted_lui_3: 753; RV64IZBA: # %bb.0: 754; RV64IZBA-NEXT: lui a0, 4097 755; RV64IZBA-NEXT: slli a0, a0, 20 756; RV64IZBA-NEXT: ret 757; 758; RV64IZBB-LABEL: imm_left_shifted_lui_3: 759; RV64IZBB: # %bb.0: 760; RV64IZBB-NEXT: lui a0, 4097 761; RV64IZBB-NEXT: slli a0, a0, 20 762; RV64IZBB-NEXT: ret 763; 764; RV64IZBS-LABEL: imm_left_shifted_lui_3: 765; RV64IZBS: # %bb.0: 766; RV64IZBS-NEXT: lui a0, 4097 767; RV64IZBS-NEXT: slli a0, a0, 20 768; RV64IZBS-NEXT: ret 769 ret i64 17596481011712 ; 0x1001_0000_0000 770} 771 772; Various cases where extraneous ADDIs can be inserted where a (right shifted) 773; LUI suffices, or where multiple ADDIs can be used instead of a single LUI. 774 775define i64 @imm_right_shifted_lui_1() nounwind { 776; RV32I-LABEL: imm_right_shifted_lui_1: 777; RV32I: # %bb.0: 778; RV32I-NEXT: lui a0, 1048575 779; RV32I-NEXT: addi a0, a0, 1 780; RV32I-NEXT: lui a1, 16 781; RV32I-NEXT: addi a1, a1, -1 782; RV32I-NEXT: ret 783; 784; RV64I-LABEL: imm_right_shifted_lui_1: 785; RV64I: # %bb.0: 786; RV64I-NEXT: lui a0, 983056 787; RV64I-NEXT: srli a0, a0, 16 788; RV64I-NEXT: ret 789; 790; RV64IZBA-LABEL: imm_right_shifted_lui_1: 791; RV64IZBA: # %bb.0: 792; RV64IZBA-NEXT: lui a0, 983056 793; RV64IZBA-NEXT: srli a0, a0, 16 794; RV64IZBA-NEXT: ret 795; 796; RV64IZBB-LABEL: imm_right_shifted_lui_1: 797; RV64IZBB: # %bb.0: 798; RV64IZBB-NEXT: lui a0, 983056 799; RV64IZBB-NEXT: srli a0, a0, 16 800; RV64IZBB-NEXT: ret 801; 802; RV64IZBS-LABEL: imm_right_shifted_lui_1: 803; RV64IZBS: # %bb.0: 804; RV64IZBS-NEXT: lui a0, 983056 805; RV64IZBS-NEXT: srli a0, a0, 16 806; RV64IZBS-NEXT: ret 807 ret i64 281474976706561 ; 0xFFFF_FFFF_F001 808} 809 810define i64 @imm_right_shifted_lui_2() nounwind { 811; RV32I-LABEL: imm_right_shifted_lui_2: 812; RV32I: # %bb.0: 813; RV32I-NEXT: lui a0, 1048575 814; RV32I-NEXT: addi a0, a0, 1 815; RV32I-NEXT: li a1, 255 816; RV32I-NEXT: ret 817; 818; RV64I-LABEL: imm_right_shifted_lui_2: 819; RV64I: # %bb.0: 820; RV64I-NEXT: lui a0, 1044481 821; RV64I-NEXT: slli a0, a0, 12 822; RV64I-NEXT: srli a0, a0, 24 823; RV64I-NEXT: ret 824; 825; RV64IZBA-LABEL: imm_right_shifted_lui_2: 826; RV64IZBA: # %bb.0: 827; RV64IZBA-NEXT: lui a0, 1044481 828; RV64IZBA-NEXT: slli a0, a0, 12 829; RV64IZBA-NEXT: srli a0, a0, 24 830; RV64IZBA-NEXT: ret 831; 832; RV64IZBB-LABEL: imm_right_shifted_lui_2: 833; RV64IZBB: # %bb.0: 834; RV64IZBB-NEXT: lui a0, 1044481 835; RV64IZBB-NEXT: slli a0, a0, 12 836; RV64IZBB-NEXT: srli a0, a0, 24 837; RV64IZBB-NEXT: ret 838; 839; RV64IZBS-LABEL: imm_right_shifted_lui_2: 840; RV64IZBS: # %bb.0: 841; RV64IZBS-NEXT: lui a0, 1044481 842; RV64IZBS-NEXT: slli a0, a0, 12 843; RV64IZBS-NEXT: srli a0, a0, 24 844; RV64IZBS-NEXT: ret 845 ret i64 1099511623681 ; 0xFF_FFFF_F001 846} 847 848; We can materialize the upper bits with a single (shifted) LUI, but that option 849; can be missed due to the lower bits, which aren't just 1s or just 0s. 850 851define i64 @imm_decoupled_lui_addi() nounwind { 852; RV32I-LABEL: imm_decoupled_lui_addi: 853; RV32I: # %bb.0: 854; RV32I-NEXT: li a0, -3 855; RV32I-NEXT: lui a1, 1 856; RV32I-NEXT: ret 857; 858; RV64I-LABEL: imm_decoupled_lui_addi: 859; RV64I: # %bb.0: 860; RV64I-NEXT: lui a0, 4097 861; RV64I-NEXT: slli a0, a0, 20 862; RV64I-NEXT: addi a0, a0, -3 863; RV64I-NEXT: ret 864; 865; RV64IZBA-LABEL: imm_decoupled_lui_addi: 866; RV64IZBA: # %bb.0: 867; RV64IZBA-NEXT: lui a0, 4097 868; RV64IZBA-NEXT: slli a0, a0, 20 869; RV64IZBA-NEXT: addi a0, a0, -3 870; RV64IZBA-NEXT: ret 871; 872; RV64IZBB-LABEL: imm_decoupled_lui_addi: 873; RV64IZBB: # %bb.0: 874; RV64IZBB-NEXT: lui a0, 4097 875; RV64IZBB-NEXT: slli a0, a0, 20 876; RV64IZBB-NEXT: addi a0, a0, -3 877; RV64IZBB-NEXT: ret 878; 879; RV64IZBS-LABEL: imm_decoupled_lui_addi: 880; RV64IZBS: # %bb.0: 881; RV64IZBS-NEXT: lui a0, 4097 882; RV64IZBS-NEXT: slli a0, a0, 20 883; RV64IZBS-NEXT: addi a0, a0, -3 884; RV64IZBS-NEXT: ret 885 ret i64 17596481011709 ; 0x1000_FFFF_FFFD 886} 887 888; This constant can be materialized for RV64 with LUI+SRLI+XORI. 889 890define i64 @imm_end_xori_1() nounwind { 891; RV32I-LABEL: imm_end_xori_1: 892; RV32I: # %bb.0: 893; RV32I-NEXT: lui a0, 8192 894; RV32I-NEXT: addi a0, a0, -1 895; RV32I-NEXT: lui a1, 917504 896; RV32I-NEXT: ret 897; 898; RV64I-LABEL: imm_end_xori_1: 899; RV64I: # %bb.0: 900; RV64I-NEXT: li a0, -1 901; RV64I-NEXT: slli a0, a0, 36 902; RV64I-NEXT: addi a0, a0, 1 903; RV64I-NEXT: slli a0, a0, 25 904; RV64I-NEXT: addi a0, a0, -1 905; RV64I-NEXT: ret 906; 907; RV64IZBA-LABEL: imm_end_xori_1: 908; RV64IZBA: # %bb.0: 909; RV64IZBA-NEXT: li a0, -1 910; RV64IZBA-NEXT: slli a0, a0, 36 911; RV64IZBA-NEXT: addi a0, a0, 1 912; RV64IZBA-NEXT: slli a0, a0, 25 913; RV64IZBA-NEXT: addi a0, a0, -1 914; RV64IZBA-NEXT: ret 915; 916; RV64IZBB-LABEL: imm_end_xori_1: 917; RV64IZBB: # %bb.0: 918; RV64IZBB-NEXT: li a0, -1 919; RV64IZBB-NEXT: slli a0, a0, 36 920; RV64IZBB-NEXT: addi a0, a0, 1 921; RV64IZBB-NEXT: slli a0, a0, 25 922; RV64IZBB-NEXT: addi a0, a0, -1 923; RV64IZBB-NEXT: ret 924; 925; RV64IZBS-LABEL: imm_end_xori_1: 926; RV64IZBS: # %bb.0: 927; RV64IZBS-NEXT: li a0, -1 928; RV64IZBS-NEXT: slli a0, a0, 36 929; RV64IZBS-NEXT: addi a0, a0, 1 930; RV64IZBS-NEXT: slli a0, a0, 25 931; RV64IZBS-NEXT: addi a0, a0, -1 932; RV64IZBS-NEXT: ret 933 ret i64 -2305843009180139521 ; 0xE000_0000_01FF_FFFF 934} 935 936; This constant can be materialized for RV64 with ADDI+SLLI+ADDI+ADDI. 937 938define i64 @imm_end_2addi_1() nounwind { 939; RV32I-LABEL: imm_end_2addi_1: 940; RV32I: # %bb.0: 941; RV32I-NEXT: lui a0, 1048575 942; RV32I-NEXT: addi a0, a0, 2047 943; RV32I-NEXT: lui a1, 1048512 944; RV32I-NEXT: addi a1, a1, 127 945; RV32I-NEXT: ret 946; 947; RV64I-LABEL: imm_end_2addi_1: 948; RV64I: # %bb.0: 949; RV64I-NEXT: li a0, -2047 950; RV64I-NEXT: slli a0, a0, 27 951; RV64I-NEXT: addi a0, a0, -1 952; RV64I-NEXT: slli a0, a0, 12 953; RV64I-NEXT: addi a0, a0, 2047 954; RV64I-NEXT: ret 955; 956; RV64IZBA-LABEL: imm_end_2addi_1: 957; RV64IZBA: # %bb.0: 958; RV64IZBA-NEXT: li a0, -2047 959; RV64IZBA-NEXT: slli a0, a0, 27 960; RV64IZBA-NEXT: addi a0, a0, -1 961; RV64IZBA-NEXT: slli a0, a0, 12 962; RV64IZBA-NEXT: addi a0, a0, 2047 963; RV64IZBA-NEXT: ret 964; 965; RV64IZBB-LABEL: imm_end_2addi_1: 966; RV64IZBB: # %bb.0: 967; RV64IZBB-NEXT: li a0, -2047 968; RV64IZBB-NEXT: slli a0, a0, 27 969; RV64IZBB-NEXT: addi a0, a0, -1 970; RV64IZBB-NEXT: slli a0, a0, 12 971; RV64IZBB-NEXT: addi a0, a0, 2047 972; RV64IZBB-NEXT: ret 973; 974; RV64IZBS-LABEL: imm_end_2addi_1: 975; RV64IZBS: # %bb.0: 976; RV64IZBS-NEXT: li a0, -2047 977; RV64IZBS-NEXT: slli a0, a0, 27 978; RV64IZBS-NEXT: addi a0, a0, -1 979; RV64IZBS-NEXT: slli a0, a0, 12 980; RV64IZBS-NEXT: addi a0, a0, 2047 981; RV64IZBS-NEXT: ret 982 ret i64 -1125350151030785 ; 0xFFFC_007F_FFFF_F7FF 983} 984 985; This constant can be more efficiently materialized for RV64 if we use two 986; registers instead of one. 987 988define i64 @imm_2reg_1() nounwind { 989; RV32I-LABEL: imm_2reg_1: 990; RV32I: # %bb.0: 991; RV32I-NEXT: lui a0, 74565 992; RV32I-NEXT: addi a0, a0, 1656 993; RV32I-NEXT: lui a1, 983040 994; RV32I-NEXT: ret 995; 996; RV64I-LABEL: imm_2reg_1: 997; RV64I: # %bb.0: 998; RV64I-NEXT: li a0, -1 999; RV64I-NEXT: slli a0, a0, 35 1000; RV64I-NEXT: addi a0, a0, 9 1001; RV64I-NEXT: slli a0, a0, 13 1002; RV64I-NEXT: addi a0, a0, 837 1003; RV64I-NEXT: slli a0, a0, 12 1004; RV64I-NEXT: addi a0, a0, 1656 1005; RV64I-NEXT: ret 1006; 1007; RV64IZBA-LABEL: imm_2reg_1: 1008; RV64IZBA: # %bb.0: 1009; RV64IZBA-NEXT: li a0, -1 1010; RV64IZBA-NEXT: slli a0, a0, 35 1011; RV64IZBA-NEXT: addi a0, a0, 9 1012; RV64IZBA-NEXT: slli a0, a0, 13 1013; RV64IZBA-NEXT: addi a0, a0, 837 1014; RV64IZBA-NEXT: slli a0, a0, 12 1015; RV64IZBA-NEXT: addi a0, a0, 1656 1016; RV64IZBA-NEXT: ret 1017; 1018; RV64IZBB-LABEL: imm_2reg_1: 1019; RV64IZBB: # %bb.0: 1020; RV64IZBB-NEXT: li a0, -1 1021; RV64IZBB-NEXT: slli a0, a0, 35 1022; RV64IZBB-NEXT: addi a0, a0, 9 1023; RV64IZBB-NEXT: slli a0, a0, 13 1024; RV64IZBB-NEXT: addi a0, a0, 837 1025; RV64IZBB-NEXT: slli a0, a0, 12 1026; RV64IZBB-NEXT: addi a0, a0, 1656 1027; RV64IZBB-NEXT: ret 1028; 1029; RV64IZBS-LABEL: imm_2reg_1: 1030; RV64IZBS: # %bb.0: 1031; RV64IZBS-NEXT: lui a0, 74565 1032; RV64IZBS-NEXT: addiw a0, a0, 1656 1033; RV64IZBS-NEXT: bseti a0, a0, 60 1034; RV64IZBS-NEXT: bseti a0, a0, 61 1035; RV64IZBS-NEXT: bseti a0, a0, 62 1036; RV64IZBS-NEXT: bseti a0, a0, 63 1037; RV64IZBS-NEXT: ret 1038 ret i64 -1152921504301427080 ; 0xF000_0000_1234_5678 1039} 1040 1041; FIXME: This should use a single ADDI for the immediate. 1042define void @imm_store_i16_neg1(i16* %p) nounwind { 1043; RV32I-LABEL: imm_store_i16_neg1: 1044; RV32I: # %bb.0: 1045; RV32I-NEXT: li a1, -1 1046; RV32I-NEXT: sh a1, 0(a0) 1047; RV32I-NEXT: ret 1048; 1049; RV64I-LABEL: imm_store_i16_neg1: 1050; RV64I: # %bb.0: 1051; RV64I-NEXT: li a1, -1 1052; RV64I-NEXT: sh a1, 0(a0) 1053; RV64I-NEXT: ret 1054; 1055; RV64IZBA-LABEL: imm_store_i16_neg1: 1056; RV64IZBA: # %bb.0: 1057; RV64IZBA-NEXT: li a1, -1 1058; RV64IZBA-NEXT: sh a1, 0(a0) 1059; RV64IZBA-NEXT: ret 1060; 1061; RV64IZBB-LABEL: imm_store_i16_neg1: 1062; RV64IZBB: # %bb.0: 1063; RV64IZBB-NEXT: li a1, -1 1064; RV64IZBB-NEXT: sh a1, 0(a0) 1065; RV64IZBB-NEXT: ret 1066; 1067; RV64IZBS-LABEL: imm_store_i16_neg1: 1068; RV64IZBS: # %bb.0: 1069; RV64IZBS-NEXT: li a1, -1 1070; RV64IZBS-NEXT: sh a1, 0(a0) 1071; RV64IZBS-NEXT: ret 1072 store i16 -1, i16* %p 1073 ret void 1074} 1075 1076; FIXME: This should use a single ADDI for the immediate. 1077define void @imm_store_i32_neg1(i32* %p) nounwind { 1078; RV32I-LABEL: imm_store_i32_neg1: 1079; RV32I: # %bb.0: 1080; RV32I-NEXT: li a1, -1 1081; RV32I-NEXT: sw a1, 0(a0) 1082; RV32I-NEXT: ret 1083; 1084; RV64I-LABEL: imm_store_i32_neg1: 1085; RV64I: # %bb.0: 1086; RV64I-NEXT: li a1, -1 1087; RV64I-NEXT: sw a1, 0(a0) 1088; RV64I-NEXT: ret 1089; 1090; RV64IZBA-LABEL: imm_store_i32_neg1: 1091; RV64IZBA: # %bb.0: 1092; RV64IZBA-NEXT: li a1, -1 1093; RV64IZBA-NEXT: sw a1, 0(a0) 1094; RV64IZBA-NEXT: ret 1095; 1096; RV64IZBB-LABEL: imm_store_i32_neg1: 1097; RV64IZBB: # %bb.0: 1098; RV64IZBB-NEXT: li a1, -1 1099; RV64IZBB-NEXT: sw a1, 0(a0) 1100; RV64IZBB-NEXT: ret 1101; 1102; RV64IZBS-LABEL: imm_store_i32_neg1: 1103; RV64IZBS: # %bb.0: 1104; RV64IZBS-NEXT: li a1, -1 1105; RV64IZBS-NEXT: sw a1, 0(a0) 1106; RV64IZBS-NEXT: ret 1107 store i32 -1, i32* %p 1108 ret void 1109} 1110 1111define i64 @imm_5372288229() { 1112; RV32I-LABEL: imm_5372288229: 1113; RV32I: # %bb.0: 1114; RV32I-NEXT: lui a0, 263018 1115; RV32I-NEXT: addi a0, a0, -795 1116; RV32I-NEXT: li a1, 1 1117; RV32I-NEXT: ret 1118; 1119; RV64I-LABEL: imm_5372288229: 1120; RV64I: # %bb.0: 1121; RV64I-NEXT: lui a0, 160 1122; RV64I-NEXT: addiw a0, a0, 437 1123; RV64I-NEXT: slli a0, a0, 13 1124; RV64I-NEXT: addi a0, a0, -795 1125; RV64I-NEXT: ret 1126; 1127; RV64IZBA-LABEL: imm_5372288229: 1128; RV64IZBA: # %bb.0: 1129; RV64IZBA-NEXT: lui a0, 655797 1130; RV64IZBA-NEXT: slli.uw a0, a0, 1 1131; RV64IZBA-NEXT: addi a0, a0, -795 1132; RV64IZBA-NEXT: ret 1133; 1134; RV64IZBB-LABEL: imm_5372288229: 1135; RV64IZBB: # %bb.0: 1136; RV64IZBB-NEXT: lui a0, 160 1137; RV64IZBB-NEXT: addiw a0, a0, 437 1138; RV64IZBB-NEXT: slli a0, a0, 13 1139; RV64IZBB-NEXT: addi a0, a0, -795 1140; RV64IZBB-NEXT: ret 1141; 1142; RV64IZBS-LABEL: imm_5372288229: 1143; RV64IZBS: # %bb.0: 1144; RV64IZBS-NEXT: lui a0, 263018 1145; RV64IZBS-NEXT: addiw a0, a0, -795 1146; RV64IZBS-NEXT: bseti a0, a0, 32 1147; RV64IZBS-NEXT: ret 1148 ret i64 5372288229 1149} 1150 1151define i64 @imm_neg_5372288229() { 1152; RV32I-LABEL: imm_neg_5372288229: 1153; RV32I: # %bb.0: 1154; RV32I-NEXT: lui a0, 785558 1155; RV32I-NEXT: addi a0, a0, 795 1156; RV32I-NEXT: li a1, -2 1157; RV32I-NEXT: ret 1158; 1159; RV64I-LABEL: imm_neg_5372288229: 1160; RV64I: # %bb.0: 1161; RV64I-NEXT: lui a0, 1048416 1162; RV64I-NEXT: addiw a0, a0, -437 1163; RV64I-NEXT: slli a0, a0, 13 1164; RV64I-NEXT: addi a0, a0, 795 1165; RV64I-NEXT: ret 1166; 1167; RV64IZBA-LABEL: imm_neg_5372288229: 1168; RV64IZBA: # %bb.0: 1169; RV64IZBA-NEXT: lui a0, 611378 1170; RV64IZBA-NEXT: addiw a0, a0, 265 1171; RV64IZBA-NEXT: sh1add a0, a0, a0 1172; RV64IZBA-NEXT: ret 1173; 1174; RV64IZBB-LABEL: imm_neg_5372288229: 1175; RV64IZBB: # %bb.0: 1176; RV64IZBB-NEXT: lui a0, 1048416 1177; RV64IZBB-NEXT: addiw a0, a0, -437 1178; RV64IZBB-NEXT: slli a0, a0, 13 1179; RV64IZBB-NEXT: addi a0, a0, 795 1180; RV64IZBB-NEXT: ret 1181; 1182; RV64IZBS-LABEL: imm_neg_5372288229: 1183; RV64IZBS: # %bb.0: 1184; RV64IZBS-NEXT: lui a0, 785558 1185; RV64IZBS-NEXT: addiw a0, a0, 795 1186; RV64IZBS-NEXT: bclri a0, a0, 32 1187; RV64IZBS-NEXT: ret 1188 ret i64 -5372288229 1189} 1190 1191define i64 @imm_8953813715() { 1192; RV32I-LABEL: imm_8953813715: 1193; RV32I: # %bb.0: 1194; RV32I-NEXT: lui a0, 88838 1195; RV32I-NEXT: addi a0, a0, -1325 1196; RV32I-NEXT: li a1, 2 1197; RV32I-NEXT: ret 1198; 1199; RV64I-LABEL: imm_8953813715: 1200; RV64I: # %bb.0: 1201; RV64I-NEXT: lui a0, 267 1202; RV64I-NEXT: addiw a0, a0, -637 1203; RV64I-NEXT: slli a0, a0, 13 1204; RV64I-NEXT: addi a0, a0, -1325 1205; RV64I-NEXT: ret 1206; 1207; RV64IZBA-LABEL: imm_8953813715: 1208; RV64IZBA: # %bb.0: 1209; RV64IZBA-NEXT: lui a0, 437198 1210; RV64IZBA-NEXT: addiw a0, a0, -265 1211; RV64IZBA-NEXT: sh2add a0, a0, a0 1212; RV64IZBA-NEXT: ret 1213; 1214; RV64IZBB-LABEL: imm_8953813715: 1215; RV64IZBB: # %bb.0: 1216; RV64IZBB-NEXT: lui a0, 267 1217; RV64IZBB-NEXT: addiw a0, a0, -637 1218; RV64IZBB-NEXT: slli a0, a0, 13 1219; RV64IZBB-NEXT: addi a0, a0, -1325 1220; RV64IZBB-NEXT: ret 1221; 1222; RV64IZBS-LABEL: imm_8953813715: 1223; RV64IZBS: # %bb.0: 1224; RV64IZBS-NEXT: lui a0, 88838 1225; RV64IZBS-NEXT: addiw a0, a0, -1325 1226; RV64IZBS-NEXT: bseti a0, a0, 33 1227; RV64IZBS-NEXT: ret 1228 ret i64 8953813715 1229} 1230 1231define i64 @imm_neg_8953813715() { 1232; RV32I-LABEL: imm_neg_8953813715: 1233; RV32I: # %bb.0: 1234; RV32I-NEXT: lui a0, 959738 1235; RV32I-NEXT: addi a0, a0, 1325 1236; RV32I-NEXT: li a1, -3 1237; RV32I-NEXT: ret 1238; 1239; RV64I-LABEL: imm_neg_8953813715: 1240; RV64I: # %bb.0: 1241; RV64I-NEXT: lui a0, 1048309 1242; RV64I-NEXT: addiw a0, a0, 637 1243; RV64I-NEXT: slli a0, a0, 13 1244; RV64I-NEXT: addi a0, a0, 1325 1245; RV64I-NEXT: ret 1246; 1247; RV64IZBA-LABEL: imm_neg_8953813715: 1248; RV64IZBA: # %bb.0: 1249; RV64IZBA-NEXT: lui a0, 611378 1250; RV64IZBA-NEXT: addiw a0, a0, 265 1251; RV64IZBA-NEXT: sh2add a0, a0, a0 1252; RV64IZBA-NEXT: ret 1253; 1254; RV64IZBB-LABEL: imm_neg_8953813715: 1255; RV64IZBB: # %bb.0: 1256; RV64IZBB-NEXT: lui a0, 1048309 1257; RV64IZBB-NEXT: addiw a0, a0, 637 1258; RV64IZBB-NEXT: slli a0, a0, 13 1259; RV64IZBB-NEXT: addi a0, a0, 1325 1260; RV64IZBB-NEXT: ret 1261; 1262; RV64IZBS-LABEL: imm_neg_8953813715: 1263; RV64IZBS: # %bb.0: 1264; RV64IZBS-NEXT: lui a0, 959738 1265; RV64IZBS-NEXT: addiw a0, a0, 1325 1266; RV64IZBS-NEXT: bclri a0, a0, 33 1267; RV64IZBS-NEXT: ret 1268 ret i64 -8953813715 1269} 1270 1271define i64 @imm_16116864687() { 1272; RV32I-LABEL: imm_16116864687: 1273; RV32I: # %bb.0: 1274; RV32I-NEXT: lui a0, 789053 1275; RV32I-NEXT: addi a0, a0, 1711 1276; RV32I-NEXT: li a1, 3 1277; RV32I-NEXT: ret 1278; 1279; RV64I-LABEL: imm_16116864687: 1280; RV64I: # %bb.0: 1281; RV64I-NEXT: lui a0, 961 1282; RV64I-NEXT: addiw a0, a0, -1475 1283; RV64I-NEXT: slli a0, a0, 12 1284; RV64I-NEXT: addi a0, a0, 1711 1285; RV64I-NEXT: ret 1286; 1287; RV64IZBA-LABEL: imm_16116864687: 1288; RV64IZBA: # %bb.0: 1289; RV64IZBA-NEXT: lui a0, 437198 1290; RV64IZBA-NEXT: addiw a0, a0, -265 1291; RV64IZBA-NEXT: sh3add a0, a0, a0 1292; RV64IZBA-NEXT: ret 1293; 1294; RV64IZBB-LABEL: imm_16116864687: 1295; RV64IZBB: # %bb.0: 1296; RV64IZBB-NEXT: lui a0, 961 1297; RV64IZBB-NEXT: addiw a0, a0, -1475 1298; RV64IZBB-NEXT: slli a0, a0, 12 1299; RV64IZBB-NEXT: addi a0, a0, 1711 1300; RV64IZBB-NEXT: ret 1301; 1302; RV64IZBS-LABEL: imm_16116864687: 1303; RV64IZBS: # %bb.0: 1304; RV64IZBS-NEXT: lui a0, 961 1305; RV64IZBS-NEXT: addiw a0, a0, -1475 1306; RV64IZBS-NEXT: slli a0, a0, 12 1307; RV64IZBS-NEXT: addi a0, a0, 1711 1308; RV64IZBS-NEXT: ret 1309 ret i64 16116864687 1310} 1311 1312define i64 @imm_neg_16116864687() { 1313; RV32I-LABEL: imm_neg_16116864687: 1314; RV32I: # %bb.0: 1315; RV32I-NEXT: lui a0, 259523 1316; RV32I-NEXT: addi a0, a0, -1711 1317; RV32I-NEXT: li a1, -4 1318; RV32I-NEXT: ret 1319; 1320; RV64I-LABEL: imm_neg_16116864687: 1321; RV64I: # %bb.0: 1322; RV64I-NEXT: lui a0, 1047615 1323; RV64I-NEXT: addiw a0, a0, 1475 1324; RV64I-NEXT: slli a0, a0, 12 1325; RV64I-NEXT: addi a0, a0, -1711 1326; RV64I-NEXT: ret 1327; 1328; RV64IZBA-LABEL: imm_neg_16116864687: 1329; RV64IZBA: # %bb.0: 1330; RV64IZBA-NEXT: lui a0, 611378 1331; RV64IZBA-NEXT: addiw a0, a0, 265 1332; RV64IZBA-NEXT: sh3add a0, a0, a0 1333; RV64IZBA-NEXT: ret 1334; 1335; RV64IZBB-LABEL: imm_neg_16116864687: 1336; RV64IZBB: # %bb.0: 1337; RV64IZBB-NEXT: lui a0, 1047615 1338; RV64IZBB-NEXT: addiw a0, a0, 1475 1339; RV64IZBB-NEXT: slli a0, a0, 12 1340; RV64IZBB-NEXT: addi a0, a0, -1711 1341; RV64IZBB-NEXT: ret 1342; 1343; RV64IZBS-LABEL: imm_neg_16116864687: 1344; RV64IZBS: # %bb.0: 1345; RV64IZBS-NEXT: lui a0, 1047615 1346; RV64IZBS-NEXT: addiw a0, a0, 1475 1347; RV64IZBS-NEXT: slli a0, a0, 12 1348; RV64IZBS-NEXT: addi a0, a0, -1711 1349; RV64IZBS-NEXT: ret 1350 ret i64 -16116864687 1351} 1352 1353define i64 @imm_2344336315() { 1354; RV32I-LABEL: imm_2344336315: 1355; RV32I: # %bb.0: 1356; RV32I-NEXT: lui a0, 572348 1357; RV32I-NEXT: addi a0, a0, -1093 1358; RV32I-NEXT: li a1, 0 1359; RV32I-NEXT: ret 1360; 1361; RV64I-LABEL: imm_2344336315: 1362; RV64I: # %bb.0: 1363; RV64I-NEXT: lui a0, 143087 1364; RV64I-NEXT: slli a0, a0, 2 1365; RV64I-NEXT: addi a0, a0, -1093 1366; RV64I-NEXT: ret 1367; 1368; RV64IZBA-LABEL: imm_2344336315: 1369; RV64IZBA: # %bb.0: 1370; RV64IZBA-NEXT: lui a0, 143087 1371; RV64IZBA-NEXT: slli a0, a0, 2 1372; RV64IZBA-NEXT: addi a0, a0, -1093 1373; RV64IZBA-NEXT: ret 1374; 1375; RV64IZBB-LABEL: imm_2344336315: 1376; RV64IZBB: # %bb.0: 1377; RV64IZBB-NEXT: lui a0, 143087 1378; RV64IZBB-NEXT: slli a0, a0, 2 1379; RV64IZBB-NEXT: addi a0, a0, -1093 1380; RV64IZBB-NEXT: ret 1381; 1382; RV64IZBS-LABEL: imm_2344336315: 1383; RV64IZBS: # %bb.0: 1384; RV64IZBS-NEXT: lui a0, 143087 1385; RV64IZBS-NEXT: slli a0, a0, 2 1386; RV64IZBS-NEXT: addi a0, a0, -1093 1387; RV64IZBS-NEXT: ret 1388 ret i64 2344336315 ; 0x8bbbbbbb 1389} 1390 1391define i64 @imm_70370820078523() { 1392; RV32I-LABEL: imm_70370820078523: 1393; RV32I: # %bb.0: 1394; RV32I-NEXT: lui a0, 506812 1395; RV32I-NEXT: addi a0, a0, -1093 1396; RV32I-NEXT: lui a1, 4 1397; RV32I-NEXT: ret 1398; 1399; RV64I-LABEL: imm_70370820078523: 1400; RV64I: # %bb.0: 1401; RV64I-NEXT: lui a0, 256 1402; RV64I-NEXT: addiw a0, a0, 31 1403; RV64I-NEXT: slli a0, a0, 12 1404; RV64I-NEXT: addi a0, a0, -273 1405; RV64I-NEXT: slli a0, a0, 14 1406; RV64I-NEXT: addi a0, a0, -1093 1407; RV64I-NEXT: ret 1408; 1409; RV64IZBA-LABEL: imm_70370820078523: 1410; RV64IZBA: # %bb.0: 1411; RV64IZBA-NEXT: lui a0, 256 1412; RV64IZBA-NEXT: addiw a0, a0, 31 1413; RV64IZBA-NEXT: slli a0, a0, 12 1414; RV64IZBA-NEXT: addi a0, a0, -273 1415; RV64IZBA-NEXT: slli a0, a0, 14 1416; RV64IZBA-NEXT: addi a0, a0, -1093 1417; RV64IZBA-NEXT: ret 1418; 1419; RV64IZBB-LABEL: imm_70370820078523: 1420; RV64IZBB: # %bb.0: 1421; RV64IZBB-NEXT: lui a0, 256 1422; RV64IZBB-NEXT: addiw a0, a0, 31 1423; RV64IZBB-NEXT: slli a0, a0, 12 1424; RV64IZBB-NEXT: addi a0, a0, -273 1425; RV64IZBB-NEXT: slli a0, a0, 14 1426; RV64IZBB-NEXT: addi a0, a0, -1093 1427; RV64IZBB-NEXT: ret 1428; 1429; RV64IZBS-LABEL: imm_70370820078523: 1430; RV64IZBS: # %bb.0: 1431; RV64IZBS-NEXT: lui a0, 506812 1432; RV64IZBS-NEXT: addiw a0, a0, -1093 1433; RV64IZBS-NEXT: bseti a0, a0, 46 1434; RV64IZBS-NEXT: ret 1435 ret i64 70370820078523 ; 0x40007bbbbbbb 1436} 1437 1438define i64 @imm_neg_9223372034778874949() { 1439; RV32I-LABEL: imm_neg_9223372034778874949: 1440; RV32I: # %bb.0: 1441; RV32I-NEXT: lui a0, 506812 1442; RV32I-NEXT: addi a0, a0, -1093 1443; RV32I-NEXT: lui a1, 524288 1444; RV32I-NEXT: ret 1445; 1446; RV64I-LABEL: imm_neg_9223372034778874949: 1447; RV64I: # %bb.0: 1448; RV64I-NEXT: li a0, -1 1449; RV64I-NEXT: slli a0, a0, 37 1450; RV64I-NEXT: addi a0, a0, 31 1451; RV64I-NEXT: slli a0, a0, 12 1452; RV64I-NEXT: addi a0, a0, -273 1453; RV64I-NEXT: slli a0, a0, 14 1454; RV64I-NEXT: addi a0, a0, -1093 1455; RV64I-NEXT: ret 1456; 1457; RV64IZBA-LABEL: imm_neg_9223372034778874949: 1458; RV64IZBA: # %bb.0: 1459; RV64IZBA-NEXT: li a0, -1 1460; RV64IZBA-NEXT: slli a0, a0, 37 1461; RV64IZBA-NEXT: addi a0, a0, 31 1462; RV64IZBA-NEXT: slli a0, a0, 12 1463; RV64IZBA-NEXT: addi a0, a0, -273 1464; RV64IZBA-NEXT: slli a0, a0, 14 1465; RV64IZBA-NEXT: addi a0, a0, -1093 1466; RV64IZBA-NEXT: ret 1467; 1468; RV64IZBB-LABEL: imm_neg_9223372034778874949: 1469; RV64IZBB: # %bb.0: 1470; RV64IZBB-NEXT: li a0, -1 1471; RV64IZBB-NEXT: slli a0, a0, 37 1472; RV64IZBB-NEXT: addi a0, a0, 31 1473; RV64IZBB-NEXT: slli a0, a0, 12 1474; RV64IZBB-NEXT: addi a0, a0, -273 1475; RV64IZBB-NEXT: slli a0, a0, 14 1476; RV64IZBB-NEXT: addi a0, a0, -1093 1477; RV64IZBB-NEXT: ret 1478; 1479; RV64IZBS-LABEL: imm_neg_9223372034778874949: 1480; RV64IZBS: # %bb.0: 1481; RV64IZBS-NEXT: lui a0, 506812 1482; RV64IZBS-NEXT: addiw a0, a0, -1093 1483; RV64IZBS-NEXT: bseti a0, a0, 63 1484; RV64IZBS-NEXT: ret 1485 ret i64 -9223372034778874949 ; 0x800000007bbbbbbb 1486} 1487 1488define i64 @imm_neg_9223301666034697285() { 1489; RV32I-LABEL: imm_neg_9223301666034697285: 1490; RV32I: # %bb.0: 1491; RV32I-NEXT: lui a0, 506812 1492; RV32I-NEXT: addi a0, a0, -1093 1493; RV32I-NEXT: lui a1, 524292 1494; RV32I-NEXT: ret 1495; 1496; RV64I-LABEL: imm_neg_9223301666034697285: 1497; RV64I: # %bb.0: 1498; RV64I-NEXT: lui a0, 917505 1499; RV64I-NEXT: slli a0, a0, 8 1500; RV64I-NEXT: addi a0, a0, 31 1501; RV64I-NEXT: slli a0, a0, 12 1502; RV64I-NEXT: addi a0, a0, -273 1503; RV64I-NEXT: slli a0, a0, 14 1504; RV64I-NEXT: addi a0, a0, -1093 1505; RV64I-NEXT: ret 1506; 1507; RV64IZBA-LABEL: imm_neg_9223301666034697285: 1508; RV64IZBA: # %bb.0: 1509; RV64IZBA-NEXT: lui a0, 917505 1510; RV64IZBA-NEXT: slli a0, a0, 8 1511; RV64IZBA-NEXT: addi a0, a0, 31 1512; RV64IZBA-NEXT: slli a0, a0, 12 1513; RV64IZBA-NEXT: addi a0, a0, -273 1514; RV64IZBA-NEXT: slli a0, a0, 14 1515; RV64IZBA-NEXT: addi a0, a0, -1093 1516; RV64IZBA-NEXT: ret 1517; 1518; RV64IZBB-LABEL: imm_neg_9223301666034697285: 1519; RV64IZBB: # %bb.0: 1520; RV64IZBB-NEXT: lui a0, 917505 1521; RV64IZBB-NEXT: slli a0, a0, 8 1522; RV64IZBB-NEXT: addi a0, a0, 31 1523; RV64IZBB-NEXT: slli a0, a0, 12 1524; RV64IZBB-NEXT: addi a0, a0, -273 1525; RV64IZBB-NEXT: slli a0, a0, 14 1526; RV64IZBB-NEXT: addi a0, a0, -1093 1527; RV64IZBB-NEXT: ret 1528; 1529; RV64IZBS-LABEL: imm_neg_9223301666034697285: 1530; RV64IZBS: # %bb.0: 1531; RV64IZBS-NEXT: lui a0, 506812 1532; RV64IZBS-NEXT: addiw a0, a0, -1093 1533; RV64IZBS-NEXT: bseti a0, a0, 46 1534; RV64IZBS-NEXT: bseti a0, a0, 63 1535; RV64IZBS-NEXT: ret 1536 ret i64 -9223301666034697285 ; 0x800040007bbbbbbb 1537} 1538 1539define i64 @imm_neg_2219066437() { 1540; RV32I-LABEL: imm_neg_2219066437: 1541; RV32I: # %bb.0: 1542; RV32I-NEXT: lui a0, 506812 1543; RV32I-NEXT: addi a0, a0, -1093 1544; RV32I-NEXT: li a1, -1 1545; RV32I-NEXT: ret 1546; 1547; RV64I-LABEL: imm_neg_2219066437: 1548; RV64I: # %bb.0: 1549; RV64I-NEXT: lui a0, 913135 1550; RV64I-NEXT: slli a0, a0, 2 1551; RV64I-NEXT: addi a0, a0, -1093 1552; RV64I-NEXT: ret 1553; 1554; RV64IZBA-LABEL: imm_neg_2219066437: 1555; RV64IZBA: # %bb.0: 1556; RV64IZBA-NEXT: lui a0, 913135 1557; RV64IZBA-NEXT: slli a0, a0, 2 1558; RV64IZBA-NEXT: addi a0, a0, -1093 1559; RV64IZBA-NEXT: ret 1560; 1561; RV64IZBB-LABEL: imm_neg_2219066437: 1562; RV64IZBB: # %bb.0: 1563; RV64IZBB-NEXT: lui a0, 913135 1564; RV64IZBB-NEXT: slli a0, a0, 2 1565; RV64IZBB-NEXT: addi a0, a0, -1093 1566; RV64IZBB-NEXT: ret 1567; 1568; RV64IZBS-LABEL: imm_neg_2219066437: 1569; RV64IZBS: # %bb.0: 1570; RV64IZBS-NEXT: lui a0, 913135 1571; RV64IZBS-NEXT: slli a0, a0, 2 1572; RV64IZBS-NEXT: addi a0, a0, -1093 1573; RV64IZBS-NEXT: ret 1574 ret i64 -2219066437 ; 0xffffffff7bbbbbbb 1575} 1576 1577define i64 @imm_neg_8798043653189() { 1578; RV32I-LABEL: imm_neg_8798043653189: 1579; RV32I: # %bb.0: 1580; RV32I-NEXT: lui a0, 572348 1581; RV32I-NEXT: addi a0, a0, -1093 1582; RV32I-NEXT: lui a1, 1048575 1583; RV32I-NEXT: addi a1, a1, 2047 1584; RV32I-NEXT: ret 1585; 1586; RV64I-LABEL: imm_neg_8798043653189: 1587; RV64I: # %bb.0: 1588; RV64I-NEXT: lui a0, 917475 1589; RV64I-NEXT: addiw a0, a0, -273 1590; RV64I-NEXT: slli a0, a0, 14 1591; RV64I-NEXT: addi a0, a0, -1093 1592; RV64I-NEXT: ret 1593; 1594; RV64IZBA-LABEL: imm_neg_8798043653189: 1595; RV64IZBA: # %bb.0: 1596; RV64IZBA-NEXT: lui a0, 917475 1597; RV64IZBA-NEXT: addiw a0, a0, -273 1598; RV64IZBA-NEXT: slli a0, a0, 14 1599; RV64IZBA-NEXT: addi a0, a0, -1093 1600; RV64IZBA-NEXT: ret 1601; 1602; RV64IZBB-LABEL: imm_neg_8798043653189: 1603; RV64IZBB: # %bb.0: 1604; RV64IZBB-NEXT: lui a0, 917475 1605; RV64IZBB-NEXT: addiw a0, a0, -273 1606; RV64IZBB-NEXT: slli a0, a0, 14 1607; RV64IZBB-NEXT: addi a0, a0, -1093 1608; RV64IZBB-NEXT: ret 1609; 1610; RV64IZBS-LABEL: imm_neg_8798043653189: 1611; RV64IZBS: # %bb.0: 1612; RV64IZBS-NEXT: lui a0, 572348 1613; RV64IZBS-NEXT: addiw a0, a0, -1093 1614; RV64IZBS-NEXT: bclri a0, a0, 43 1615; RV64IZBS-NEXT: ret 1616 ret i64 -8798043653189 ; 0xfffff7ff8bbbbbbb 1617} 1618 1619define i64 @imm_9223372034904144827() { 1620; RV32I-LABEL: imm_9223372034904144827: 1621; RV32I: # %bb.0: 1622; RV32I-NEXT: lui a0, 572348 1623; RV32I-NEXT: addi a0, a0, -1093 1624; RV32I-NEXT: lui a1, 524288 1625; RV32I-NEXT: addi a1, a1, -1 1626; RV32I-NEXT: ret 1627; 1628; RV64I-LABEL: imm_9223372034904144827: 1629; RV64I: # %bb.0: 1630; RV64I-NEXT: lui a0, 1048343 1631; RV64I-NEXT: addiw a0, a0, 1911 1632; RV64I-NEXT: slli a0, a0, 12 1633; RV64I-NEXT: addi a0, a0, 1911 1634; RV64I-NEXT: srli a0, a0, 1 1635; RV64I-NEXT: ret 1636; 1637; RV64IZBA-LABEL: imm_9223372034904144827: 1638; RV64IZBA: # %bb.0: 1639; RV64IZBA-NEXT: lui a0, 1048343 1640; RV64IZBA-NEXT: addiw a0, a0, 1911 1641; RV64IZBA-NEXT: slli a0, a0, 12 1642; RV64IZBA-NEXT: addi a0, a0, 1911 1643; RV64IZBA-NEXT: srli a0, a0, 1 1644; RV64IZBA-NEXT: ret 1645; 1646; RV64IZBB-LABEL: imm_9223372034904144827: 1647; RV64IZBB: # %bb.0: 1648; RV64IZBB-NEXT: lui a0, 1048343 1649; RV64IZBB-NEXT: addiw a0, a0, 1911 1650; RV64IZBB-NEXT: slli a0, a0, 12 1651; RV64IZBB-NEXT: addi a0, a0, 1911 1652; RV64IZBB-NEXT: srli a0, a0, 1 1653; RV64IZBB-NEXT: ret 1654; 1655; RV64IZBS-LABEL: imm_9223372034904144827: 1656; RV64IZBS: # %bb.0: 1657; RV64IZBS-NEXT: lui a0, 572348 1658; RV64IZBS-NEXT: addiw a0, a0, -1093 1659; RV64IZBS-NEXT: bclri a0, a0, 63 1660; RV64IZBS-NEXT: ret 1661 ret i64 9223372034904144827 ; 0x7fffffff8bbbbbbb 1662} 1663 1664define i64 @imm_neg_9223354442718100411() { 1665; RV32I-LABEL: imm_neg_9223354442718100411: 1666; RV32I: # %bb.0: 1667; RV32I-NEXT: lui a0, 572348 1668; RV32I-NEXT: addi a0, a0, -1093 1669; RV32I-NEXT: lui a1, 524287 1670; RV32I-NEXT: addi a1, a1, -1 1671; RV32I-NEXT: ret 1672; 1673; RV64I-LABEL: imm_neg_9223354442718100411: 1674; RV64I: # %bb.0: 1675; RV64I-NEXT: lui a0, 524287 1676; RV64I-NEXT: slli a0, a0, 6 1677; RV64I-NEXT: addi a0, a0, -29 1678; RV64I-NEXT: slli a0, a0, 12 1679; RV64I-NEXT: addi a0, a0, -273 1680; RV64I-NEXT: slli a0, a0, 14 1681; RV64I-NEXT: addi a0, a0, -1093 1682; RV64I-NEXT: ret 1683; 1684; RV64IZBA-LABEL: imm_neg_9223354442718100411: 1685; RV64IZBA: # %bb.0: 1686; RV64IZBA-NEXT: lui a0, 524287 1687; RV64IZBA-NEXT: slli a0, a0, 6 1688; RV64IZBA-NEXT: addi a0, a0, -29 1689; RV64IZBA-NEXT: slli a0, a0, 12 1690; RV64IZBA-NEXT: addi a0, a0, -273 1691; RV64IZBA-NEXT: slli a0, a0, 14 1692; RV64IZBA-NEXT: addi a0, a0, -1093 1693; RV64IZBA-NEXT: ret 1694; 1695; RV64IZBB-LABEL: imm_neg_9223354442718100411: 1696; RV64IZBB: # %bb.0: 1697; RV64IZBB-NEXT: lui a0, 524287 1698; RV64IZBB-NEXT: slli a0, a0, 6 1699; RV64IZBB-NEXT: addi a0, a0, -29 1700; RV64IZBB-NEXT: slli a0, a0, 12 1701; RV64IZBB-NEXT: addi a0, a0, -273 1702; RV64IZBB-NEXT: slli a0, a0, 14 1703; RV64IZBB-NEXT: addi a0, a0, -1093 1704; RV64IZBB-NEXT: ret 1705; 1706; RV64IZBS-LABEL: imm_neg_9223354442718100411: 1707; RV64IZBS: # %bb.0: 1708; RV64IZBS-NEXT: lui a0, 572348 1709; RV64IZBS-NEXT: addiw a0, a0, -1093 1710; RV64IZBS-NEXT: bclri a0, a0, 44 1711; RV64IZBS-NEXT: bclri a0, a0, 63 1712; RV64IZBS-NEXT: ret 1713 ret i64 9223354442718100411 ; 0x7fffefff8bbbbbbb 1714} 1715 1716define i64 @imm_2863311530() { 1717; RV32I-LABEL: imm_2863311530: 1718; RV32I: # %bb.0: 1719; RV32I-NEXT: lui a0, 699051 1720; RV32I-NEXT: addi a0, a0, -1366 1721; RV32I-NEXT: li a1, 0 1722; RV32I-NEXT: ret 1723; 1724; RV64I-LABEL: imm_2863311530: 1725; RV64I: # %bb.0: 1726; RV64I-NEXT: lui a0, 171 1727; RV64I-NEXT: addiw a0, a0, -1365 1728; RV64I-NEXT: slli a0, a0, 12 1729; RV64I-NEXT: addi a0, a0, -1366 1730; RV64I-NEXT: ret 1731; 1732; RV64IZBA-LABEL: imm_2863311530: 1733; RV64IZBA: # %bb.0: 1734; RV64IZBA-NEXT: lui a0, 699051 1735; RV64IZBA-NEXT: addiw a0, a0, -1366 1736; RV64IZBA-NEXT: zext.w a0, a0 1737; RV64IZBA-NEXT: ret 1738; 1739; RV64IZBB-LABEL: imm_2863311530: 1740; RV64IZBB: # %bb.0: 1741; RV64IZBB-NEXT: lui a0, 171 1742; RV64IZBB-NEXT: addiw a0, a0, -1365 1743; RV64IZBB-NEXT: slli a0, a0, 12 1744; RV64IZBB-NEXT: addi a0, a0, -1366 1745; RV64IZBB-NEXT: ret 1746; 1747; RV64IZBS-LABEL: imm_2863311530: 1748; RV64IZBS: # %bb.0: 1749; RV64IZBS-NEXT: lui a0, 174763 1750; RV64IZBS-NEXT: addiw a0, a0, -1366 1751; RV64IZBS-NEXT: bseti a0, a0, 31 1752; RV64IZBS-NEXT: ret 1753 ret i64 2863311530 ; #0xaaaaaaaa 1754} 1755 1756define i64 @imm_neg_2863311530() { 1757; RV32I-LABEL: imm_neg_2863311530: 1758; RV32I: # %bb.0: 1759; RV32I-NEXT: lui a0, 349525 1760; RV32I-NEXT: addi a0, a0, 1366 1761; RV32I-NEXT: li a1, -1 1762; RV32I-NEXT: ret 1763; 1764; RV64I-LABEL: imm_neg_2863311530: 1765; RV64I: # %bb.0: 1766; RV64I-NEXT: lui a0, 1048405 1767; RV64I-NEXT: addiw a0, a0, 1365 1768; RV64I-NEXT: slli a0, a0, 12 1769; RV64I-NEXT: addi a0, a0, 1366 1770; RV64I-NEXT: ret 1771; 1772; RV64IZBA-LABEL: imm_neg_2863311530: 1773; RV64IZBA: # %bb.0: 1774; RV64IZBA-NEXT: lui a0, 908766 1775; RV64IZBA-NEXT: addiw a0, a0, -546 1776; RV64IZBA-NEXT: sh2add a0, a0, a0 1777; RV64IZBA-NEXT: ret 1778; 1779; RV64IZBB-LABEL: imm_neg_2863311530: 1780; RV64IZBB: # %bb.0: 1781; RV64IZBB-NEXT: lui a0, 1048405 1782; RV64IZBB-NEXT: addiw a0, a0, 1365 1783; RV64IZBB-NEXT: slli a0, a0, 12 1784; RV64IZBB-NEXT: addi a0, a0, 1366 1785; RV64IZBB-NEXT: ret 1786; 1787; RV64IZBS-LABEL: imm_neg_2863311530: 1788; RV64IZBS: # %bb.0: 1789; RV64IZBS-NEXT: lui a0, 873813 1790; RV64IZBS-NEXT: addiw a0, a0, 1366 1791; RV64IZBS-NEXT: bclri a0, a0, 31 1792; RV64IZBS-NEXT: ret 1793 ret i64 -2863311530 ; #0xffffffff55555556 1794} 1795 1796define i64 @imm_2147486378() { 1797; RV32I-LABEL: imm_2147486378: 1798; RV32I: # %bb.0: 1799; RV32I-NEXT: lui a0, 524288 1800; RV32I-NEXT: addi a0, a0, 1365 1801; RV32I-NEXT: li a1, 0 1802; RV32I-NEXT: ret 1803; 1804; RV64I-LABEL: imm_2147486378: 1805; RV64I: # %bb.0: 1806; RV64I-NEXT: li a0, 1 1807; RV64I-NEXT: slli a0, a0, 31 1808; RV64I-NEXT: addi a0, a0, 1365 1809; RV64I-NEXT: ret 1810; 1811; RV64IZBA-LABEL: imm_2147486378: 1812; RV64IZBA: # %bb.0: 1813; RV64IZBA-NEXT: li a0, 1 1814; RV64IZBA-NEXT: slli a0, a0, 31 1815; RV64IZBA-NEXT: addi a0, a0, 1365 1816; RV64IZBA-NEXT: ret 1817; 1818; RV64IZBB-LABEL: imm_2147486378: 1819; RV64IZBB: # %bb.0: 1820; RV64IZBB-NEXT: li a0, 1 1821; RV64IZBB-NEXT: slli a0, a0, 31 1822; RV64IZBB-NEXT: addi a0, a0, 1365 1823; RV64IZBB-NEXT: ret 1824; 1825; RV64IZBS-LABEL: imm_2147486378: 1826; RV64IZBS: # %bb.0: 1827; RV64IZBS-NEXT: li a0, 1365 1828; RV64IZBS-NEXT: bseti a0, a0, 31 1829; RV64IZBS-NEXT: ret 1830 ret i64 2147485013 1831} 1832 1833define i64 @imm_neg_2147485013() { 1834; RV32I-LABEL: imm_neg_2147485013: 1835; RV32I: # %bb.0: 1836; RV32I-NEXT: lui a0, 524288 1837; RV32I-NEXT: addi a0, a0, -1365 1838; RV32I-NEXT: li a1, -1 1839; RV32I-NEXT: ret 1840; 1841; RV64I-LABEL: imm_neg_2147485013: 1842; RV64I: # %bb.0: 1843; RV64I-NEXT: li a0, -1 1844; RV64I-NEXT: slli a0, a0, 31 1845; RV64I-NEXT: addi a0, a0, -1365 1846; RV64I-NEXT: ret 1847; 1848; RV64IZBA-LABEL: imm_neg_2147485013: 1849; RV64IZBA: # %bb.0: 1850; RV64IZBA-NEXT: li a0, -1 1851; RV64IZBA-NEXT: slli a0, a0, 31 1852; RV64IZBA-NEXT: addi a0, a0, -1365 1853; RV64IZBA-NEXT: ret 1854; 1855; RV64IZBB-LABEL: imm_neg_2147485013: 1856; RV64IZBB: # %bb.0: 1857; RV64IZBB-NEXT: li a0, -1 1858; RV64IZBB-NEXT: slli a0, a0, 31 1859; RV64IZBB-NEXT: addi a0, a0, -1365 1860; RV64IZBB-NEXT: ret 1861; 1862; RV64IZBS-LABEL: imm_neg_2147485013: 1863; RV64IZBS: # %bb.0: 1864; RV64IZBS-NEXT: li a0, -1365 1865; RV64IZBS-NEXT: bclri a0, a0, 31 1866; RV64IZBS-NEXT: ret 1867 ret i64 -2147485013 1868} 1869 1870define i64 @imm_12900924131259() { 1871; RV32I-LABEL: imm_12900924131259: 1872; RV32I: # %bb.0: 1873; RV32I-NEXT: lui a0, 765952 1874; RV32I-NEXT: addi a0, a0, 1979 1875; RV32I-NEXT: lui a1, 1 1876; RV32I-NEXT: addi a1, a1, -1093 1877; RV32I-NEXT: ret 1878; 1879; RV64I-LABEL: imm_12900924131259: 1880; RV64I: # %bb.0: 1881; RV64I-NEXT: lui a0, 188 1882; RV64I-NEXT: addiw a0, a0, -1093 1883; RV64I-NEXT: slli a0, a0, 24 1884; RV64I-NEXT: addi a0, a0, 1979 1885; RV64I-NEXT: ret 1886; 1887; RV64IZBA-LABEL: imm_12900924131259: 1888; RV64IZBA: # %bb.0: 1889; RV64IZBA-NEXT: lui a0, 768955 1890; RV64IZBA-NEXT: slli.uw a0, a0, 12 1891; RV64IZBA-NEXT: addi a0, a0, 1979 1892; RV64IZBA-NEXT: ret 1893; 1894; RV64IZBB-LABEL: imm_12900924131259: 1895; RV64IZBB: # %bb.0: 1896; RV64IZBB-NEXT: lui a0, 188 1897; RV64IZBB-NEXT: addiw a0, a0, -1093 1898; RV64IZBB-NEXT: slli a0, a0, 24 1899; RV64IZBB-NEXT: addi a0, a0, 1979 1900; RV64IZBB-NEXT: ret 1901; 1902; RV64IZBS-LABEL: imm_12900924131259: 1903; RV64IZBS: # %bb.0: 1904; RV64IZBS-NEXT: lui a0, 188 1905; RV64IZBS-NEXT: addiw a0, a0, -1093 1906; RV64IZBS-NEXT: slli a0, a0, 24 1907; RV64IZBS-NEXT: addi a0, a0, 1979 1908; RV64IZBS-NEXT: ret 1909 ret i64 12900924131259 1910} 1911 1912define i64 @imm_50394234880() { 1913; RV32I-LABEL: imm_50394234880: 1914; RV32I: # %bb.0: 1915; RV32I-NEXT: lui a0, 768944 1916; RV32I-NEXT: li a1, 11 1917; RV32I-NEXT: ret 1918; 1919; RV64I-LABEL: imm_50394234880: 1920; RV64I: # %bb.0: 1921; RV64I-NEXT: lui a0, 188 1922; RV64I-NEXT: addiw a0, a0, -1093 1923; RV64I-NEXT: slli a0, a0, 16 1924; RV64I-NEXT: ret 1925; 1926; RV64IZBA-LABEL: imm_50394234880: 1927; RV64IZBA: # %bb.0: 1928; RV64IZBA-NEXT: lui a0, 768955 1929; RV64IZBA-NEXT: slli.uw a0, a0, 4 1930; RV64IZBA-NEXT: ret 1931; 1932; RV64IZBB-LABEL: imm_50394234880: 1933; RV64IZBB: # %bb.0: 1934; RV64IZBB-NEXT: lui a0, 188 1935; RV64IZBB-NEXT: addiw a0, a0, -1093 1936; RV64IZBB-NEXT: slli a0, a0, 16 1937; RV64IZBB-NEXT: ret 1938; 1939; RV64IZBS-LABEL: imm_50394234880: 1940; RV64IZBS: # %bb.0: 1941; RV64IZBS-NEXT: lui a0, 188 1942; RV64IZBS-NEXT: addiw a0, a0, -1093 1943; RV64IZBS-NEXT: slli a0, a0, 16 1944; RV64IZBS-NEXT: ret 1945 ret i64 50394234880 1946} 1947 1948define i64 @imm_12900936431479() { 1949; RV32I-LABEL: imm_12900936431479: 1950; RV32I: # %bb.0: 1951; RV32I-NEXT: lui a0, 768955 1952; RV32I-NEXT: addi a0, a0, 1911 1953; RV32I-NEXT: lui a1, 1 1954; RV32I-NEXT: addi a1, a1, -1093 1955; RV32I-NEXT: ret 1956; 1957; RV64I-LABEL: imm_12900936431479: 1958; RV64I: # %bb.0: 1959; RV64I-NEXT: lui a0, 192239 1960; RV64I-NEXT: slli a0, a0, 2 1961; RV64I-NEXT: addi a0, a0, -1093 1962; RV64I-NEXT: slli a0, a0, 12 1963; RV64I-NEXT: addi a0, a0, 1911 1964; RV64I-NEXT: ret 1965; 1966; RV64IZBA-LABEL: imm_12900936431479: 1967; RV64IZBA: # %bb.0: 1968; RV64IZBA-NEXT: lui a0, 768956 1969; RV64IZBA-NEXT: addiw a0, a0, -1093 1970; RV64IZBA-NEXT: slli.uw a0, a0, 12 1971; RV64IZBA-NEXT: addi a0, a0, 1911 1972; RV64IZBA-NEXT: ret 1973; 1974; RV64IZBB-LABEL: imm_12900936431479: 1975; RV64IZBB: # %bb.0: 1976; RV64IZBB-NEXT: lui a0, 192239 1977; RV64IZBB-NEXT: slli a0, a0, 2 1978; RV64IZBB-NEXT: addi a0, a0, -1093 1979; RV64IZBB-NEXT: slli a0, a0, 12 1980; RV64IZBB-NEXT: addi a0, a0, 1911 1981; RV64IZBB-NEXT: ret 1982; 1983; RV64IZBS-LABEL: imm_12900936431479: 1984; RV64IZBS: # %bb.0: 1985; RV64IZBS-NEXT: lui a0, 192239 1986; RV64IZBS-NEXT: slli a0, a0, 2 1987; RV64IZBS-NEXT: addi a0, a0, -1093 1988; RV64IZBS-NEXT: slli a0, a0, 12 1989; RV64IZBS-NEXT: addi a0, a0, 1911 1990; RV64IZBS-NEXT: ret 1991 ret i64 12900936431479 1992} 1993 1994define i64 @imm_12900918536874() { 1995; RV32I-LABEL: imm_12900918536874: 1996; RV32I: # %bb.0: 1997; RV32I-NEXT: lui a0, 764587 1998; RV32I-NEXT: addi a0, a0, -1366 1999; RV32I-NEXT: lui a1, 1 2000; RV32I-NEXT: addi a1, a1, -1093 2001; RV32I-NEXT: ret 2002; 2003; RV64I-LABEL: imm_12900918536874: 2004; RV64I: # %bb.0: 2005; RV64I-NEXT: lui a0, 188 2006; RV64I-NEXT: addiw a0, a0, -1093 2007; RV64I-NEXT: slli a0, a0, 12 2008; RV64I-NEXT: addi a0, a0, -1365 2009; RV64I-NEXT: slli a0, a0, 12 2010; RV64I-NEXT: addi a0, a0, -1366 2011; RV64I-NEXT: ret 2012; 2013; RV64IZBA-LABEL: imm_12900918536874: 2014; RV64IZBA: # %bb.0: 2015; RV64IZBA-NEXT: lui a0, 768955 2016; RV64IZBA-NEXT: addiw a0, a0, -1365 2017; RV64IZBA-NEXT: slli.uw a0, a0, 12 2018; RV64IZBA-NEXT: addi a0, a0, -1366 2019; RV64IZBA-NEXT: ret 2020; 2021; RV64IZBB-LABEL: imm_12900918536874: 2022; RV64IZBB: # %bb.0: 2023; RV64IZBB-NEXT: lui a0, 188 2024; RV64IZBB-NEXT: addiw a0, a0, -1093 2025; RV64IZBB-NEXT: slli a0, a0, 12 2026; RV64IZBB-NEXT: addi a0, a0, -1365 2027; RV64IZBB-NEXT: slli a0, a0, 12 2028; RV64IZBB-NEXT: addi a0, a0, -1366 2029; RV64IZBB-NEXT: ret 2030; 2031; RV64IZBS-LABEL: imm_12900918536874: 2032; RV64IZBS: # %bb.0: 2033; RV64IZBS-NEXT: lui a0, 188 2034; RV64IZBS-NEXT: addiw a0, a0, -1093 2035; RV64IZBS-NEXT: slli a0, a0, 12 2036; RV64IZBS-NEXT: addi a0, a0, -1365 2037; RV64IZBS-NEXT: slli a0, a0, 12 2038; RV64IZBS-NEXT: addi a0, a0, -1366 2039; RV64IZBS-NEXT: ret 2040 ret i64 12900918536874 2041} 2042 2043define i64 @imm_12900925247761() { 2044; RV32I-LABEL: imm_12900925247761: 2045; RV32I: # %bb.0: 2046; RV32I-NEXT: lui a0, 766225 2047; RV32I-NEXT: addi a0, a0, 273 2048; RV32I-NEXT: lui a1, 1 2049; RV32I-NEXT: addi a1, a1, -1093 2050; RV32I-NEXT: ret 2051; 2052; RV64I-LABEL: imm_12900925247761: 2053; RV64I: # %bb.0: 2054; RV64I-NEXT: lui a0, 188 2055; RV64I-NEXT: addiw a0, a0, -1093 2056; RV64I-NEXT: slli a0, a0, 12 2057; RV64I-NEXT: addi a0, a0, 273 2058; RV64I-NEXT: slli a0, a0, 12 2059; RV64I-NEXT: addi a0, a0, 273 2060; RV64I-NEXT: ret 2061; 2062; RV64IZBA-LABEL: imm_12900925247761: 2063; RV64IZBA: # %bb.0: 2064; RV64IZBA-NEXT: lui a0, 768955 2065; RV64IZBA-NEXT: addiw a0, a0, 273 2066; RV64IZBA-NEXT: slli.uw a0, a0, 12 2067; RV64IZBA-NEXT: addi a0, a0, 273 2068; RV64IZBA-NEXT: ret 2069; 2070; RV64IZBB-LABEL: imm_12900925247761: 2071; RV64IZBB: # %bb.0: 2072; RV64IZBB-NEXT: lui a0, 188 2073; RV64IZBB-NEXT: addiw a0, a0, -1093 2074; RV64IZBB-NEXT: slli a0, a0, 12 2075; RV64IZBB-NEXT: addi a0, a0, 273 2076; RV64IZBB-NEXT: slli a0, a0, 12 2077; RV64IZBB-NEXT: addi a0, a0, 273 2078; RV64IZBB-NEXT: ret 2079; 2080; RV64IZBS-LABEL: imm_12900925247761: 2081; RV64IZBS: # %bb.0: 2082; RV64IZBS-NEXT: lui a0, 188 2083; RV64IZBS-NEXT: addiw a0, a0, -1093 2084; RV64IZBS-NEXT: slli a0, a0, 12 2085; RV64IZBS-NEXT: addi a0, a0, 273 2086; RV64IZBS-NEXT: slli a0, a0, 12 2087; RV64IZBS-NEXT: addi a0, a0, 273 2088; RV64IZBS-NEXT: ret 2089 ret i64 12900925247761 2090} 2091 2092define i64 @imm_7158272001() { 2093; RV32I-LABEL: imm_7158272001: 2094; RV32I: # %bb.0: 2095; RV32I-NEXT: lui a0, 699049 2096; RV32I-NEXT: addi a0, a0, 1 2097; RV32I-NEXT: li a1, 1 2098; RV32I-NEXT: ret 2099; 2100; RV64I-LABEL: imm_7158272001: 2101; RV64I: # %bb.0: 2102; RV64I-NEXT: lui a0, 427 2103; RV64I-NEXT: addiw a0, a0, -1367 2104; RV64I-NEXT: slli a0, a0, 12 2105; RV64I-NEXT: addi a0, a0, 1 2106; RV64I-NEXT: ret 2107; 2108; RV64IZBA-LABEL: imm_7158272001: 2109; RV64IZBA: # %bb.0: 2110; RV64IZBA-NEXT: lui a0, 349525 2111; RV64IZBA-NEXT: sh2add a0, a0, a0 2112; RV64IZBA-NEXT: addi a0, a0, 1 2113; RV64IZBA-NEXT: ret 2114; 2115; RV64IZBB-LABEL: imm_7158272001: 2116; RV64IZBB: # %bb.0: 2117; RV64IZBB-NEXT: lui a0, 427 2118; RV64IZBB-NEXT: addiw a0, a0, -1367 2119; RV64IZBB-NEXT: slli a0, a0, 12 2120; RV64IZBB-NEXT: addi a0, a0, 1 2121; RV64IZBB-NEXT: ret 2122; 2123; RV64IZBS-LABEL: imm_7158272001: 2124; RV64IZBS: # %bb.0: 2125; RV64IZBS-NEXT: lui a0, 427 2126; RV64IZBS-NEXT: addiw a0, a0, -1367 2127; RV64IZBS-NEXT: slli a0, a0, 12 2128; RV64IZBS-NEXT: addi a0, a0, 1 2129; RV64IZBS-NEXT: ret 2130 ret i64 7158272001 ; 0x0000_0001_aaaa_9001 2131} 2132 2133define i64 @imm_12884889601() { 2134; RV32I-LABEL: imm_12884889601: 2135; RV32I: # %bb.0: 2136; RV32I-NEXT: lui a0, 1048573 2137; RV32I-NEXT: addi a0, a0, 1 2138; RV32I-NEXT: li a1, 2 2139; RV32I-NEXT: ret 2140; 2141; RV64I-LABEL: imm_12884889601: 2142; RV64I: # %bb.0: 2143; RV64I-NEXT: lui a0, 768 2144; RV64I-NEXT: addiw a0, a0, -3 2145; RV64I-NEXT: slli a0, a0, 12 2146; RV64I-NEXT: addi a0, a0, 1 2147; RV64I-NEXT: ret 2148; 2149; RV64IZBA-LABEL: imm_12884889601: 2150; RV64IZBA: # %bb.0: 2151; RV64IZBA-NEXT: lui a0, 349525 2152; RV64IZBA-NEXT: sh3add a0, a0, a0 2153; RV64IZBA-NEXT: addi a0, a0, 1 2154; RV64IZBA-NEXT: ret 2155; 2156; RV64IZBB-LABEL: imm_12884889601: 2157; RV64IZBB: # %bb.0: 2158; RV64IZBB-NEXT: lui a0, 768 2159; RV64IZBB-NEXT: addiw a0, a0, -3 2160; RV64IZBB-NEXT: slli a0, a0, 12 2161; RV64IZBB-NEXT: addi a0, a0, 1 2162; RV64IZBB-NEXT: ret 2163; 2164; RV64IZBS-LABEL: imm_12884889601: 2165; RV64IZBS: # %bb.0: 2166; RV64IZBS-NEXT: lui a0, 768 2167; RV64IZBS-NEXT: addiw a0, a0, -3 2168; RV64IZBS-NEXT: slli a0, a0, 12 2169; RV64IZBS-NEXT: addi a0, a0, 1 2170; RV64IZBS-NEXT: ret 2171 ret i64 12884889601 ; 0x0000_0002_ffff_d001 2172} 2173 2174define i64 @imm_neg_3435982847() { 2175; RV32I-LABEL: imm_neg_3435982847: 2176; RV32I: # %bb.0: 2177; RV32I-NEXT: lui a0, 209713 2178; RV32I-NEXT: addi a0, a0, 1 2179; RV32I-NEXT: li a1, -1 2180; RV32I-NEXT: ret 2181; 2182; RV64I-LABEL: imm_neg_3435982847: 2183; RV64I: # %bb.0: 2184; RV64I-NEXT: lui a0, 1048371 2185; RV64I-NEXT: addiw a0, a0, 817 2186; RV64I-NEXT: slli a0, a0, 12 2187; RV64I-NEXT: addi a0, a0, 1 2188; RV64I-NEXT: ret 2189; 2190; RV64IZBA-LABEL: imm_neg_3435982847: 2191; RV64IZBA: # %bb.0: 2192; RV64IZBA-NEXT: lui a0, 768955 2193; RV64IZBA-NEXT: sh1add a0, a0, a0 2194; RV64IZBA-NEXT: addi a0, a0, 1 2195; RV64IZBA-NEXT: ret 2196; 2197; RV64IZBB-LABEL: imm_neg_3435982847: 2198; RV64IZBB: # %bb.0: 2199; RV64IZBB-NEXT: lui a0, 1048371 2200; RV64IZBB-NEXT: addiw a0, a0, 817 2201; RV64IZBB-NEXT: slli a0, a0, 12 2202; RV64IZBB-NEXT: addi a0, a0, 1 2203; RV64IZBB-NEXT: ret 2204; 2205; RV64IZBS-LABEL: imm_neg_3435982847: 2206; RV64IZBS: # %bb.0: 2207; RV64IZBS-NEXT: lui a0, 734001 2208; RV64IZBS-NEXT: addiw a0, a0, 1 2209; RV64IZBS-NEXT: bclri a0, a0, 31 2210; RV64IZBS-NEXT: ret 2211 ret i64 -3435982847 ; 0xffff_ffff_3333_1001 2212} 2213 2214define i64 @imm_neg_5726842879() { 2215; RV32I-LABEL: imm_neg_5726842879: 2216; RV32I: # %bb.0: 2217; RV32I-NEXT: lui a0, 698997 2218; RV32I-NEXT: addi a0, a0, 1 2219; RV32I-NEXT: li a1, -2 2220; RV32I-NEXT: ret 2221; 2222; RV64I-LABEL: imm_neg_5726842879: 2223; RV64I: # %bb.0: 2224; RV64I-NEXT: lui a0, 1048235 2225; RV64I-NEXT: addiw a0, a0, -1419 2226; RV64I-NEXT: slli a0, a0, 12 2227; RV64I-NEXT: addi a0, a0, 1 2228; RV64I-NEXT: ret 2229; 2230; RV64IZBA-LABEL: imm_neg_5726842879: 2231; RV64IZBA: # %bb.0: 2232; RV64IZBA-NEXT: lui a0, 768945 2233; RV64IZBA-NEXT: sh2add a0, a0, a0 2234; RV64IZBA-NEXT: addi a0, a0, 1 2235; RV64IZBA-NEXT: ret 2236; 2237; RV64IZBB-LABEL: imm_neg_5726842879: 2238; RV64IZBB: # %bb.0: 2239; RV64IZBB-NEXT: lui a0, 1048235 2240; RV64IZBB-NEXT: addiw a0, a0, -1419 2241; RV64IZBB-NEXT: slli a0, a0, 12 2242; RV64IZBB-NEXT: addi a0, a0, 1 2243; RV64IZBB-NEXT: ret 2244; 2245; RV64IZBS-LABEL: imm_neg_5726842879: 2246; RV64IZBS: # %bb.0: 2247; RV64IZBS-NEXT: lui a0, 698997 2248; RV64IZBS-NEXT: addiw a0, a0, 1 2249; RV64IZBS-NEXT: bclri a0, a0, 32 2250; RV64IZBS-NEXT: ret 2251 ret i64 -5726842879 ; 0xffff_fffe_aaa7_5001 2252} 2253 2254define i64 @imm_neg_10307948543() { 2255; RV32I-LABEL: imm_neg_10307948543: 2256; RV32I: # %bb.0: 2257; RV32I-NEXT: lui a0, 629139 2258; RV32I-NEXT: addi a0, a0, 1 2259; RV32I-NEXT: li a1, -3 2260; RV32I-NEXT: ret 2261; 2262; RV64I-LABEL: imm_neg_10307948543: 2263; RV64I: # %bb.0: 2264; RV64I-NEXT: lui a0, 1047962 2265; RV64I-NEXT: addiw a0, a0, -1645 2266; RV64I-NEXT: slli a0, a0, 12 2267; RV64I-NEXT: addi a0, a0, 1 2268; RV64I-NEXT: ret 2269; 2270; RV64IZBA-LABEL: imm_neg_10307948543: 2271; RV64IZBA: # %bb.0: 2272; RV64IZBA-NEXT: lui a0, 768955 2273; RV64IZBA-NEXT: sh3add a0, a0, a0 2274; RV64IZBA-NEXT: addi a0, a0, 1 2275; RV64IZBA-NEXT: ret 2276; 2277; RV64IZBB-LABEL: imm_neg_10307948543: 2278; RV64IZBB: # %bb.0: 2279; RV64IZBB-NEXT: lui a0, 1047962 2280; RV64IZBB-NEXT: addiw a0, a0, -1645 2281; RV64IZBB-NEXT: slli a0, a0, 12 2282; RV64IZBB-NEXT: addi a0, a0, 1 2283; RV64IZBB-NEXT: ret 2284; 2285; RV64IZBS-LABEL: imm_neg_10307948543: 2286; RV64IZBS: # %bb.0: 2287; RV64IZBS-NEXT: lui a0, 629139 2288; RV64IZBS-NEXT: addiw a0, a0, 1 2289; RV64IZBS-NEXT: bclri a0, a0, 33 2290; RV64IZBS-NEXT: ret 2291 ret i64 -10307948543 ; 0xffff_fffd_9999_3001 2292} 2293 2294define i64 @li_rori_1() { 2295; RV32I-LABEL: li_rori_1: 2296; RV32I: # %bb.0: 2297; RV32I-NEXT: lui a0, 1048567 2298; RV32I-NEXT: addi a1, a0, 2047 2299; RV32I-NEXT: li a0, -1 2300; RV32I-NEXT: ret 2301; 2302; RV64I-LABEL: li_rori_1: 2303; RV64I: # %bb.0: 2304; RV64I-NEXT: li a0, -17 2305; RV64I-NEXT: slli a0, a0, 43 2306; RV64I-NEXT: addi a0, a0, -1 2307; RV64I-NEXT: ret 2308; 2309; RV64IZBA-LABEL: li_rori_1: 2310; RV64IZBA: # %bb.0: 2311; RV64IZBA-NEXT: li a0, -17 2312; RV64IZBA-NEXT: slli a0, a0, 43 2313; RV64IZBA-NEXT: addi a0, a0, -1 2314; RV64IZBA-NEXT: ret 2315; 2316; RV64IZBB-LABEL: li_rori_1: 2317; RV64IZBB: # %bb.0: 2318; RV64IZBB-NEXT: li a0, -18 2319; RV64IZBB-NEXT: rori a0, a0, 21 2320; RV64IZBB-NEXT: ret 2321; 2322; RV64IZBS-LABEL: li_rori_1: 2323; RV64IZBS: # %bb.0: 2324; RV64IZBS-NEXT: li a0, -17 2325; RV64IZBS-NEXT: slli a0, a0, 43 2326; RV64IZBS-NEXT: addi a0, a0, -1 2327; RV64IZBS-NEXT: ret 2328 ret i64 -149533581377537 2329} 2330 2331define i64 @li_rori_2() { 2332; RV32I-LABEL: li_rori_2: 2333; RV32I: # %bb.0: 2334; RV32I-NEXT: lui a0, 720896 2335; RV32I-NEXT: addi a1, a0, -1 2336; RV32I-NEXT: li a0, -6 2337; RV32I-NEXT: ret 2338; 2339; RV64I-LABEL: li_rori_2: 2340; RV64I: # %bb.0: 2341; RV64I-NEXT: li a0, -5 2342; RV64I-NEXT: slli a0, a0, 60 2343; RV64I-NEXT: addi a0, a0, -6 2344; RV64I-NEXT: ret 2345; 2346; RV64IZBA-LABEL: li_rori_2: 2347; RV64IZBA: # %bb.0: 2348; RV64IZBA-NEXT: li a0, -5 2349; RV64IZBA-NEXT: slli a0, a0, 60 2350; RV64IZBA-NEXT: addi a0, a0, -6 2351; RV64IZBA-NEXT: ret 2352; 2353; RV64IZBB-LABEL: li_rori_2: 2354; RV64IZBB: # %bb.0: 2355; RV64IZBB-NEXT: li a0, -86 2356; RV64IZBB-NEXT: rori a0, a0, 4 2357; RV64IZBB-NEXT: ret 2358; 2359; RV64IZBS-LABEL: li_rori_2: 2360; RV64IZBS: # %bb.0: 2361; RV64IZBS-NEXT: li a0, -5 2362; RV64IZBS-NEXT: slli a0, a0, 60 2363; RV64IZBS-NEXT: addi a0, a0, -6 2364; RV64IZBS-NEXT: ret 2365 ret i64 -5764607523034234886 2366} 2367 2368define i64 @li_rori_3() { 2369; RV32I-LABEL: li_rori_3: 2370; RV32I: # %bb.0: 2371; RV32I-NEXT: lui a0, 491520 2372; RV32I-NEXT: addi a0, a0, -1 2373; RV32I-NEXT: li a1, -1 2374; RV32I-NEXT: ret 2375; 2376; RV64I-LABEL: li_rori_3: 2377; RV64I: # %bb.0: 2378; RV64I-NEXT: li a0, -17 2379; RV64I-NEXT: slli a0, a0, 27 2380; RV64I-NEXT: addi a0, a0, -1 2381; RV64I-NEXT: ret 2382; 2383; RV64IZBA-LABEL: li_rori_3: 2384; RV64IZBA: # %bb.0: 2385; RV64IZBA-NEXT: li a0, -17 2386; RV64IZBA-NEXT: slli a0, a0, 27 2387; RV64IZBA-NEXT: addi a0, a0, -1 2388; RV64IZBA-NEXT: ret 2389; 2390; RV64IZBB-LABEL: li_rori_3: 2391; RV64IZBB: # %bb.0: 2392; RV64IZBB-NEXT: li a0, -18 2393; RV64IZBB-NEXT: rori a0, a0, 37 2394; RV64IZBB-NEXT: ret 2395; 2396; RV64IZBS-LABEL: li_rori_3: 2397; RV64IZBS: # %bb.0: 2398; RV64IZBS-NEXT: li a0, -17 2399; RV64IZBS-NEXT: slli a0, a0, 27 2400; RV64IZBS-NEXT: addi a0, a0, -1 2401; RV64IZBS-NEXT: ret 2402 ret i64 -2281701377 2403} 2404