1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
4; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh -verify-machineinstrs \
5; RUN:   -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
6; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
7; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
8; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh -verify-machineinstrs \
9; RUN:   -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
10
11define i16 @fcvt_si_h(half %a) nounwind {
12; RV32IZFH-LABEL: fcvt_si_h:
13; RV32IZFH:       # %bb.0:
14; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
15; RV32IZFH-NEXT:    ret
16;
17; RV32IDZFH-LABEL: fcvt_si_h:
18; RV32IDZFH:       # %bb.0:
19; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
20; RV32IDZFH-NEXT:    ret
21;
22; RV64IZFH-LABEL: fcvt_si_h:
23; RV64IZFH:       # %bb.0:
24; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
25; RV64IZFH-NEXT:    ret
26;
27; RV64IDZFH-LABEL: fcvt_si_h:
28; RV64IDZFH:       # %bb.0:
29; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
30; RV64IDZFH-NEXT:    ret
31  %1 = fptosi half %a to i16
32  ret i16 %1
33}
34
35define i16 @fcvt_si_h_sat(half %a) nounwind {
36; RV32IZFH-LABEL: fcvt_si_h_sat:
37; RV32IZFH:       # %bb.0: # %start
38; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
39; RV32IZFH-NEXT:    feq.s a0, ft0, ft0
40; RV32IZFH-NEXT:    bnez a0, .LBB1_2
41; RV32IZFH-NEXT:  # %bb.1: # %start
42; RV32IZFH-NEXT:    mv a0, zero
43; RV32IZFH-NEXT:    ret
44; RV32IZFH-NEXT:  .LBB1_2:
45; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
46; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
47; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_1)
48; RV32IZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
49; RV32IZFH-NEXT:    fmax.s ft0, ft0, ft1
50; RV32IZFH-NEXT:    fmin.s ft0, ft0, ft2
51; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
52; RV32IZFH-NEXT:    ret
53;
54; RV32IDZFH-LABEL: fcvt_si_h_sat:
55; RV32IDZFH:       # %bb.0: # %start
56; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
57; RV32IDZFH-NEXT:    feq.s a0, ft0, ft0
58; RV32IDZFH-NEXT:    bnez a0, .LBB1_2
59; RV32IDZFH-NEXT:  # %bb.1: # %start
60; RV32IDZFH-NEXT:    mv a0, zero
61; RV32IDZFH-NEXT:    ret
62; RV32IDZFH-NEXT:  .LBB1_2:
63; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI1_0)
64; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
65; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI1_1)
66; RV32IDZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
67; RV32IDZFH-NEXT:    fmax.s ft0, ft0, ft1
68; RV32IDZFH-NEXT:    fmin.s ft0, ft0, ft2
69; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
70; RV32IDZFH-NEXT:    ret
71;
72; RV64IZFH-LABEL: fcvt_si_h_sat:
73; RV64IZFH:       # %bb.0: # %start
74; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
75; RV64IZFH-NEXT:    feq.s a0, ft0, ft0
76; RV64IZFH-NEXT:    bnez a0, .LBB1_2
77; RV64IZFH-NEXT:  # %bb.1: # %start
78; RV64IZFH-NEXT:    mv a0, zero
79; RV64IZFH-NEXT:    ret
80; RV64IZFH-NEXT:  .LBB1_2:
81; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
82; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
83; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_1)
84; RV64IZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
85; RV64IZFH-NEXT:    fmax.s ft0, ft0, ft1
86; RV64IZFH-NEXT:    fmin.s ft0, ft0, ft2
87; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
88; RV64IZFH-NEXT:    ret
89;
90; RV64IDZFH-LABEL: fcvt_si_h_sat:
91; RV64IDZFH:       # %bb.0: # %start
92; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
93; RV64IDZFH-NEXT:    feq.s a0, ft0, ft0
94; RV64IDZFH-NEXT:    bnez a0, .LBB1_2
95; RV64IDZFH-NEXT:  # %bb.1: # %start
96; RV64IDZFH-NEXT:    mv a0, zero
97; RV64IDZFH-NEXT:    ret
98; RV64IDZFH-NEXT:  .LBB1_2:
99; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI1_0)
100; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
101; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI1_1)
102; RV64IDZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
103; RV64IDZFH-NEXT:    fmax.s ft0, ft0, ft1
104; RV64IDZFH-NEXT:    fmin.s ft0, ft0, ft2
105; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
106; RV64IDZFH-NEXT:    ret
107start:
108  %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
109  ret i16 %0
110}
111declare i16 @llvm.fptosi.sat.i16.f16(half)
112
113define i16 @fcvt_ui_h(half %a) nounwind {
114; RV32IZFH-LABEL: fcvt_ui_h:
115; RV32IZFH:       # %bb.0:
116; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
117; RV32IZFH-NEXT:    ret
118;
119; RV32IDZFH-LABEL: fcvt_ui_h:
120; RV32IDZFH:       # %bb.0:
121; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
122; RV32IDZFH-NEXT:    ret
123;
124; RV64IZFH-LABEL: fcvt_ui_h:
125; RV64IZFH:       # %bb.0:
126; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
127; RV64IZFH-NEXT:    ret
128;
129; RV64IDZFH-LABEL: fcvt_ui_h:
130; RV64IDZFH:       # %bb.0:
131; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
132; RV64IDZFH-NEXT:    ret
133  %1 = fptoui half %a to i16
134  ret i16 %1
135}
136
137; Test where the fptoui has multiple uses, one of which causes a sext to be
138; inserted on RV64.
139; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
140define i32 @fcvt_ui_h_multiple_use(half %x, i32* %y) {
141; RV32IZFH-LABEL: fcvt_ui_h_multiple_use:
142; RV32IZFH:       # %bb.0:
143; RV32IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
144; RV32IZFH-NEXT:    addi a0, zero, 1
145; RV32IZFH-NEXT:    beqz a1, .LBB3_2
146; RV32IZFH-NEXT:  # %bb.1:
147; RV32IZFH-NEXT:    mv a0, a1
148; RV32IZFH-NEXT:  .LBB3_2:
149; RV32IZFH-NEXT:    ret
150;
151; RV32IDZFH-LABEL: fcvt_ui_h_multiple_use:
152; RV32IDZFH:       # %bb.0:
153; RV32IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
154; RV32IDZFH-NEXT:    addi a0, zero, 1
155; RV32IDZFH-NEXT:    beqz a1, .LBB3_2
156; RV32IDZFH-NEXT:  # %bb.1:
157; RV32IDZFH-NEXT:    mv a0, a1
158; RV32IDZFH-NEXT:  .LBB3_2:
159; RV32IDZFH-NEXT:    ret
160;
161; RV64IZFH-LABEL: fcvt_ui_h_multiple_use:
162; RV64IZFH:       # %bb.0:
163; RV64IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
164; RV64IZFH-NEXT:    addi a0, zero, 1
165; RV64IZFH-NEXT:    beqz a1, .LBB3_2
166; RV64IZFH-NEXT:  # %bb.1:
167; RV64IZFH-NEXT:    mv a0, a1
168; RV64IZFH-NEXT:  .LBB3_2:
169; RV64IZFH-NEXT:    ret
170;
171; RV64IDZFH-LABEL: fcvt_ui_h_multiple_use:
172; RV64IDZFH:       # %bb.0:
173; RV64IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
174; RV64IDZFH-NEXT:    addi a0, zero, 1
175; RV64IDZFH-NEXT:    beqz a1, .LBB3_2
176; RV64IDZFH-NEXT:  # %bb.1:
177; RV64IDZFH-NEXT:    mv a0, a1
178; RV64IDZFH-NEXT:  .LBB3_2:
179; RV64IDZFH-NEXT:    ret
180  %a = fptoui half %x to i32
181  %b = icmp eq i32 %a, 0
182  %c = select i1 %b, i32 1, i32 %a
183  ret i32 %c
184}
185
186define i16 @fcvt_ui_h_sat(half %a) nounwind {
187; RV32IZFH-LABEL: fcvt_ui_h_sat:
188; RV32IZFH:       # %bb.0: # %start
189; RV32IZFH-NEXT:    lui a0, %hi(.LCPI4_0)
190; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
191; RV32IZFH-NEXT:    fcvt.s.h ft1, fa0
192; RV32IZFH-NEXT:    fmv.w.x ft2, zero
193; RV32IZFH-NEXT:    fmax.s ft1, ft1, ft2
194; RV32IZFH-NEXT:    fmin.s ft0, ft1, ft0
195; RV32IZFH-NEXT:    fcvt.wu.s a0, ft0, rtz
196; RV32IZFH-NEXT:    ret
197;
198; RV32IDZFH-LABEL: fcvt_ui_h_sat:
199; RV32IDZFH:       # %bb.0: # %start
200; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI4_0)
201; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
202; RV32IDZFH-NEXT:    fcvt.s.h ft1, fa0
203; RV32IDZFH-NEXT:    fmv.w.x ft2, zero
204; RV32IDZFH-NEXT:    fmax.s ft1, ft1, ft2
205; RV32IDZFH-NEXT:    fmin.s ft0, ft1, ft0
206; RV32IDZFH-NEXT:    fcvt.wu.s a0, ft0, rtz
207; RV32IDZFH-NEXT:    ret
208;
209; RV64IZFH-LABEL: fcvt_ui_h_sat:
210; RV64IZFH:       # %bb.0: # %start
211; RV64IZFH-NEXT:    lui a0, %hi(.LCPI4_0)
212; RV64IZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
213; RV64IZFH-NEXT:    fcvt.s.h ft1, fa0
214; RV64IZFH-NEXT:    fmv.w.x ft2, zero
215; RV64IZFH-NEXT:    fmax.s ft1, ft1, ft2
216; RV64IZFH-NEXT:    fmin.s ft0, ft1, ft0
217; RV64IZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
218; RV64IZFH-NEXT:    ret
219;
220; RV64IDZFH-LABEL: fcvt_ui_h_sat:
221; RV64IDZFH:       # %bb.0: # %start
222; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI4_0)
223; RV64IDZFH-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
224; RV64IDZFH-NEXT:    fcvt.s.h ft1, fa0
225; RV64IDZFH-NEXT:    fmv.w.x ft2, zero
226; RV64IDZFH-NEXT:    fmax.s ft1, ft1, ft2
227; RV64IDZFH-NEXT:    fmin.s ft0, ft1, ft0
228; RV64IDZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
229; RV64IDZFH-NEXT:    ret
230start:
231  %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
232  ret i16 %0
233}
234declare i16 @llvm.fptoui.sat.i16.f16(half)
235
236define i32 @fcvt_w_h(half %a) nounwind {
237; RV32IZFH-LABEL: fcvt_w_h:
238; RV32IZFH:       # %bb.0:
239; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
240; RV32IZFH-NEXT:    ret
241;
242; RV32IDZFH-LABEL: fcvt_w_h:
243; RV32IDZFH:       # %bb.0:
244; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
245; RV32IDZFH-NEXT:    ret
246;
247; RV64IZFH-LABEL: fcvt_w_h:
248; RV64IZFH:       # %bb.0:
249; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
250; RV64IZFH-NEXT:    ret
251;
252; RV64IDZFH-LABEL: fcvt_w_h:
253; RV64IDZFH:       # %bb.0:
254; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
255; RV64IDZFH-NEXT:    ret
256  %1 = fptosi half %a to i32
257  ret i32 %1
258}
259
260define i32 @fcvt_w_h_sat(half %a) nounwind {
261; RV32IZFH-LABEL: fcvt_w_h_sat:
262; RV32IZFH:       # %bb.0: # %start
263; RV32IZFH-NEXT:    lui a0, %hi(.LCPI6_0)
264; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
265; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
266; RV32IZFH-NEXT:    fle.s a0, ft1, ft0
267; RV32IZFH-NEXT:    lui a1, 524288
268; RV32IZFH-NEXT:    bnez a0, .LBB6_2
269; RV32IZFH-NEXT:  # %bb.1: # %start
270; RV32IZFH-NEXT:    lui a0, 524288
271; RV32IZFH-NEXT:    j .LBB6_3
272; RV32IZFH-NEXT:  .LBB6_2:
273; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
274; RV32IZFH-NEXT:  .LBB6_3: # %start
275; RV32IZFH-NEXT:    lui a2, %hi(.LCPI6_1)
276; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
277; RV32IZFH-NEXT:    flt.s a2, ft1, ft0
278; RV32IZFH-NEXT:    bnez a2, .LBB6_6
279; RV32IZFH-NEXT:  # %bb.4: # %start
280; RV32IZFH-NEXT:    feq.s a1, ft0, ft0
281; RV32IZFH-NEXT:    beqz a1, .LBB6_7
282; RV32IZFH-NEXT:  .LBB6_5: # %start
283; RV32IZFH-NEXT:    ret
284; RV32IZFH-NEXT:  .LBB6_6:
285; RV32IZFH-NEXT:    addi a0, a1, -1
286; RV32IZFH-NEXT:    feq.s a1, ft0, ft0
287; RV32IZFH-NEXT:    bnez a1, .LBB6_5
288; RV32IZFH-NEXT:  .LBB6_7: # %start
289; RV32IZFH-NEXT:    mv a0, zero
290; RV32IZFH-NEXT:    ret
291;
292; RV32IDZFH-LABEL: fcvt_w_h_sat:
293; RV32IDZFH:       # %bb.0: # %start
294; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI6_0)
295; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
296; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
297; RV32IDZFH-NEXT:    fle.s a0, ft1, ft0
298; RV32IDZFH-NEXT:    lui a1, 524288
299; RV32IDZFH-NEXT:    bnez a0, .LBB6_2
300; RV32IDZFH-NEXT:  # %bb.1: # %start
301; RV32IDZFH-NEXT:    lui a0, 524288
302; RV32IDZFH-NEXT:    j .LBB6_3
303; RV32IDZFH-NEXT:  .LBB6_2:
304; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
305; RV32IDZFH-NEXT:  .LBB6_3: # %start
306; RV32IDZFH-NEXT:    lui a2, %hi(.LCPI6_1)
307; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
308; RV32IDZFH-NEXT:    flt.s a2, ft1, ft0
309; RV32IDZFH-NEXT:    bnez a2, .LBB6_6
310; RV32IDZFH-NEXT:  # %bb.4: # %start
311; RV32IDZFH-NEXT:    feq.s a1, ft0, ft0
312; RV32IDZFH-NEXT:    beqz a1, .LBB6_7
313; RV32IDZFH-NEXT:  .LBB6_5: # %start
314; RV32IDZFH-NEXT:    ret
315; RV32IDZFH-NEXT:  .LBB6_6:
316; RV32IDZFH-NEXT:    addi a0, a1, -1
317; RV32IDZFH-NEXT:    feq.s a1, ft0, ft0
318; RV32IDZFH-NEXT:    bnez a1, .LBB6_5
319; RV32IDZFH-NEXT:  .LBB6_7: # %start
320; RV32IDZFH-NEXT:    mv a0, zero
321; RV32IDZFH-NEXT:    ret
322;
323; RV64IZFH-LABEL: fcvt_w_h_sat:
324; RV64IZFH:       # %bb.0: # %start
325; RV64IZFH-NEXT:    lui a0, %hi(.LCPI6_0)
326; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
327; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
328; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
329; RV64IZFH-NEXT:    lui a1, 524288
330; RV64IZFH-NEXT:    bnez a0, .LBB6_2
331; RV64IZFH-NEXT:  # %bb.1: # %start
332; RV64IZFH-NEXT:    lui a0, 524288
333; RV64IZFH-NEXT:    j .LBB6_3
334; RV64IZFH-NEXT:  .LBB6_2:
335; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
336; RV64IZFH-NEXT:  .LBB6_3: # %start
337; RV64IZFH-NEXT:    lui a2, %hi(.LCPI6_1)
338; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
339; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
340; RV64IZFH-NEXT:    bnez a2, .LBB6_6
341; RV64IZFH-NEXT:  # %bb.4: # %start
342; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
343; RV64IZFH-NEXT:    beqz a1, .LBB6_7
344; RV64IZFH-NEXT:  .LBB6_5: # %start
345; RV64IZFH-NEXT:    ret
346; RV64IZFH-NEXT:  .LBB6_6:
347; RV64IZFH-NEXT:    addiw a0, a1, -1
348; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
349; RV64IZFH-NEXT:    bnez a1, .LBB6_5
350; RV64IZFH-NEXT:  .LBB6_7: # %start
351; RV64IZFH-NEXT:    mv a0, zero
352; RV64IZFH-NEXT:    ret
353;
354; RV64IDZFH-LABEL: fcvt_w_h_sat:
355; RV64IDZFH:       # %bb.0: # %start
356; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI6_0)
357; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI6_0)(a0)
358; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
359; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
360; RV64IDZFH-NEXT:    lui a1, 524288
361; RV64IDZFH-NEXT:    bnez a0, .LBB6_2
362; RV64IDZFH-NEXT:  # %bb.1: # %start
363; RV64IDZFH-NEXT:    lui a0, 524288
364; RV64IDZFH-NEXT:    j .LBB6_3
365; RV64IDZFH-NEXT:  .LBB6_2:
366; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
367; RV64IDZFH-NEXT:  .LBB6_3: # %start
368; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI6_1)
369; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI6_1)(a2)
370; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
371; RV64IDZFH-NEXT:    bnez a2, .LBB6_6
372; RV64IDZFH-NEXT:  # %bb.4: # %start
373; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
374; RV64IDZFH-NEXT:    beqz a1, .LBB6_7
375; RV64IDZFH-NEXT:  .LBB6_5: # %start
376; RV64IDZFH-NEXT:    ret
377; RV64IDZFH-NEXT:  .LBB6_6:
378; RV64IDZFH-NEXT:    addiw a0, a1, -1
379; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
380; RV64IDZFH-NEXT:    bnez a1, .LBB6_5
381; RV64IDZFH-NEXT:  .LBB6_7: # %start
382; RV64IDZFH-NEXT:    mv a0, zero
383; RV64IDZFH-NEXT:    ret
384start:
385  %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
386  ret i32 %0
387}
388declare i32 @llvm.fptosi.sat.i32.f16(half)
389
390define i32 @fcvt_wu_h(half %a) nounwind {
391; RV32IZFH-LABEL: fcvt_wu_h:
392; RV32IZFH:       # %bb.0:
393; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
394; RV32IZFH-NEXT:    ret
395;
396; RV32IDZFH-LABEL: fcvt_wu_h:
397; RV32IDZFH:       # %bb.0:
398; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
399; RV32IDZFH-NEXT:    ret
400;
401; RV64IZFH-LABEL: fcvt_wu_h:
402; RV64IZFH:       # %bb.0:
403; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
404; RV64IZFH-NEXT:    ret
405;
406; RV64IDZFH-LABEL: fcvt_wu_h:
407; RV64IDZFH:       # %bb.0:
408; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
409; RV64IDZFH-NEXT:    ret
410  %1 = fptoui half %a to i32
411  ret i32 %1
412}
413
414define i32 @fcvt_wu_h_sat(half %a) nounwind {
415; RV32IZFH-LABEL: fcvt_wu_h_sat:
416; RV32IZFH:       # %bb.0: # %start
417; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
418; RV32IZFH-NEXT:    fmv.w.x ft1, zero
419; RV32IZFH-NEXT:    fle.s a0, ft1, ft0
420; RV32IZFH-NEXT:    bnez a0, .LBB8_2
421; RV32IZFH-NEXT:  # %bb.1: # %start
422; RV32IZFH-NEXT:    mv a1, zero
423; RV32IZFH-NEXT:    j .LBB8_3
424; RV32IZFH-NEXT:  .LBB8_2:
425; RV32IZFH-NEXT:    fcvt.wu.s a1, ft0, rtz
426; RV32IZFH-NEXT:  .LBB8_3: # %start
427; RV32IZFH-NEXT:    lui a0, %hi(.LCPI8_0)
428; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a0)
429; RV32IZFH-NEXT:    flt.s a2, ft1, ft0
430; RV32IZFH-NEXT:    addi a0, zero, -1
431; RV32IZFH-NEXT:    bnez a2, .LBB8_5
432; RV32IZFH-NEXT:  # %bb.4: # %start
433; RV32IZFH-NEXT:    mv a0, a1
434; RV32IZFH-NEXT:  .LBB8_5: # %start
435; RV32IZFH-NEXT:    ret
436;
437; RV32IDZFH-LABEL: fcvt_wu_h_sat:
438; RV32IDZFH:       # %bb.0: # %start
439; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
440; RV32IDZFH-NEXT:    fmv.w.x ft1, zero
441; RV32IDZFH-NEXT:    fle.s a0, ft1, ft0
442; RV32IDZFH-NEXT:    bnez a0, .LBB8_2
443; RV32IDZFH-NEXT:  # %bb.1: # %start
444; RV32IDZFH-NEXT:    mv a1, zero
445; RV32IDZFH-NEXT:    j .LBB8_3
446; RV32IDZFH-NEXT:  .LBB8_2:
447; RV32IDZFH-NEXT:    fcvt.wu.s a1, ft0, rtz
448; RV32IDZFH-NEXT:  .LBB8_3: # %start
449; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI8_0)
450; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a0)
451; RV32IDZFH-NEXT:    flt.s a2, ft1, ft0
452; RV32IDZFH-NEXT:    addi a0, zero, -1
453; RV32IDZFH-NEXT:    bnez a2, .LBB8_5
454; RV32IDZFH-NEXT:  # %bb.4: # %start
455; RV32IDZFH-NEXT:    mv a0, a1
456; RV32IDZFH-NEXT:  .LBB8_5: # %start
457; RV32IDZFH-NEXT:    ret
458;
459; RV64IZFH-LABEL: fcvt_wu_h_sat:
460; RV64IZFH:       # %bb.0: # %start
461; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
462; RV64IZFH-NEXT:    fmv.w.x ft1, zero
463; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
464; RV64IZFH-NEXT:    bnez a0, .LBB8_2
465; RV64IZFH-NEXT:  # %bb.1: # %start
466; RV64IZFH-NEXT:    mv a0, zero
467; RV64IZFH-NEXT:    j .LBB8_3
468; RV64IZFH-NEXT:  .LBB8_2:
469; RV64IZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
470; RV64IZFH-NEXT:  .LBB8_3: # %start
471; RV64IZFH-NEXT:    lui a1, %hi(.LCPI8_0)
472; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a1)
473; RV64IZFH-NEXT:    flt.s a1, ft1, ft0
474; RV64IZFH-NEXT:    beqz a1, .LBB8_5
475; RV64IZFH-NEXT:  # %bb.4:
476; RV64IZFH-NEXT:    addi a0, zero, -1
477; RV64IZFH-NEXT:    srli a0, a0, 32
478; RV64IZFH-NEXT:  .LBB8_5: # %start
479; RV64IZFH-NEXT:    ret
480;
481; RV64IDZFH-LABEL: fcvt_wu_h_sat:
482; RV64IDZFH:       # %bb.0: # %start
483; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
484; RV64IDZFH-NEXT:    fmv.w.x ft1, zero
485; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
486; RV64IDZFH-NEXT:    bnez a0, .LBB8_2
487; RV64IDZFH-NEXT:  # %bb.1: # %start
488; RV64IDZFH-NEXT:    mv a0, zero
489; RV64IDZFH-NEXT:    j .LBB8_3
490; RV64IDZFH-NEXT:  .LBB8_2:
491; RV64IDZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
492; RV64IDZFH-NEXT:  .LBB8_3: # %start
493; RV64IDZFH-NEXT:    lui a1, %hi(.LCPI8_0)
494; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI8_0)(a1)
495; RV64IDZFH-NEXT:    flt.s a1, ft1, ft0
496; RV64IDZFH-NEXT:    beqz a1, .LBB8_5
497; RV64IDZFH-NEXT:  # %bb.4:
498; RV64IDZFH-NEXT:    addi a0, zero, -1
499; RV64IDZFH-NEXT:    srli a0, a0, 32
500; RV64IDZFH-NEXT:  .LBB8_5: # %start
501; RV64IDZFH-NEXT:    ret
502start:
503  %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
504  ret i32 %0
505}
506declare i32 @llvm.fptoui.sat.i32.f16(half)
507
508define i64 @fcvt_l_h(half %a) nounwind {
509; RV32IZFH-LABEL: fcvt_l_h:
510; RV32IZFH:       # %bb.0:
511; RV32IZFH-NEXT:    addi sp, sp, -16
512; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
513; RV32IZFH-NEXT:    call __fixhfdi@plt
514; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
515; RV32IZFH-NEXT:    addi sp, sp, 16
516; RV32IZFH-NEXT:    ret
517;
518; RV32IDZFH-LABEL: fcvt_l_h:
519; RV32IDZFH:       # %bb.0:
520; RV32IDZFH-NEXT:    addi sp, sp, -16
521; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
522; RV32IDZFH-NEXT:    call __fixhfdi@plt
523; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
524; RV32IDZFH-NEXT:    addi sp, sp, 16
525; RV32IDZFH-NEXT:    ret
526;
527; RV64IZFH-LABEL: fcvt_l_h:
528; RV64IZFH:       # %bb.0:
529; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
530; RV64IZFH-NEXT:    ret
531;
532; RV64IDZFH-LABEL: fcvt_l_h:
533; RV64IDZFH:       # %bb.0:
534; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
535; RV64IDZFH-NEXT:    ret
536  %1 = fptosi half %a to i64
537  ret i64 %1
538}
539
540define i64 @fcvt_l_h_sat(half %a) nounwind {
541; RV32IZFH-LABEL: fcvt_l_h_sat:
542; RV32IZFH:       # %bb.0: # %start
543; RV32IZFH-NEXT:    addi sp, sp, -16
544; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
545; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
546; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
547; RV32IZFH-NEXT:    lui a0, %hi(.LCPI10_0)
548; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
549; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
550; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
551; RV32IZFH-NEXT:    fmv.s fa0, fs0
552; RV32IZFH-NEXT:    call __fixsfdi@plt
553; RV32IZFH-NEXT:    mv a2, a0
554; RV32IZFH-NEXT:    bnez s0, .LBB10_2
555; RV32IZFH-NEXT:  # %bb.1: # %start
556; RV32IZFH-NEXT:    mv a2, zero
557; RV32IZFH-NEXT:  .LBB10_2: # %start
558; RV32IZFH-NEXT:    lui a0, %hi(.LCPI10_1)
559; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a0)
560; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
561; RV32IZFH-NEXT:    addi a0, zero, -1
562; RV32IZFH-NEXT:    beqz a3, .LBB10_9
563; RV32IZFH-NEXT:  # %bb.3: # %start
564; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
565; RV32IZFH-NEXT:    beqz a2, .LBB10_10
566; RV32IZFH-NEXT:  .LBB10_4: # %start
567; RV32IZFH-NEXT:    lui a4, 524288
568; RV32IZFH-NEXT:    beqz s0, .LBB10_11
569; RV32IZFH-NEXT:  .LBB10_5: # %start
570; RV32IZFH-NEXT:    bnez a3, .LBB10_12
571; RV32IZFH-NEXT:  .LBB10_6: # %start
572; RV32IZFH-NEXT:    bnez a2, .LBB10_8
573; RV32IZFH-NEXT:  .LBB10_7: # %start
574; RV32IZFH-NEXT:    mv a1, zero
575; RV32IZFH-NEXT:  .LBB10_8: # %start
576; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
577; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
578; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
579; RV32IZFH-NEXT:    addi sp, sp, 16
580; RV32IZFH-NEXT:    ret
581; RV32IZFH-NEXT:  .LBB10_9: # %start
582; RV32IZFH-NEXT:    mv a0, a2
583; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
584; RV32IZFH-NEXT:    bnez a2, .LBB10_4
585; RV32IZFH-NEXT:  .LBB10_10: # %start
586; RV32IZFH-NEXT:    mv a0, zero
587; RV32IZFH-NEXT:    lui a4, 524288
588; RV32IZFH-NEXT:    bnez s0, .LBB10_5
589; RV32IZFH-NEXT:  .LBB10_11: # %start
590; RV32IZFH-NEXT:    lui a1, 524288
591; RV32IZFH-NEXT:    beqz a3, .LBB10_6
592; RV32IZFH-NEXT:  .LBB10_12:
593; RV32IZFH-NEXT:    addi a1, a4, -1
594; RV32IZFH-NEXT:    beqz a2, .LBB10_7
595; RV32IZFH-NEXT:    j .LBB10_8
596;
597; RV32IDZFH-LABEL: fcvt_l_h_sat:
598; RV32IDZFH:       # %bb.0: # %start
599; RV32IDZFH-NEXT:    addi sp, sp, -16
600; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
601; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
602; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
603; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI10_0)
604; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
605; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
606; RV32IDZFH-NEXT:    fle.s s0, ft0, fs0
607; RV32IDZFH-NEXT:    fmv.s fa0, fs0
608; RV32IDZFH-NEXT:    call __fixsfdi@plt
609; RV32IDZFH-NEXT:    mv a2, a0
610; RV32IDZFH-NEXT:    bnez s0, .LBB10_2
611; RV32IDZFH-NEXT:  # %bb.1: # %start
612; RV32IDZFH-NEXT:    mv a2, zero
613; RV32IDZFH-NEXT:  .LBB10_2: # %start
614; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI10_1)
615; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a0)
616; RV32IDZFH-NEXT:    flt.s a3, ft0, fs0
617; RV32IDZFH-NEXT:    addi a0, zero, -1
618; RV32IDZFH-NEXT:    beqz a3, .LBB10_9
619; RV32IDZFH-NEXT:  # %bb.3: # %start
620; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
621; RV32IDZFH-NEXT:    beqz a2, .LBB10_10
622; RV32IDZFH-NEXT:  .LBB10_4: # %start
623; RV32IDZFH-NEXT:    lui a4, 524288
624; RV32IDZFH-NEXT:    beqz s0, .LBB10_11
625; RV32IDZFH-NEXT:  .LBB10_5: # %start
626; RV32IDZFH-NEXT:    bnez a3, .LBB10_12
627; RV32IDZFH-NEXT:  .LBB10_6: # %start
628; RV32IDZFH-NEXT:    bnez a2, .LBB10_8
629; RV32IDZFH-NEXT:  .LBB10_7: # %start
630; RV32IDZFH-NEXT:    mv a1, zero
631; RV32IDZFH-NEXT:  .LBB10_8: # %start
632; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
633; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
634; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
635; RV32IDZFH-NEXT:    addi sp, sp, 16
636; RV32IDZFH-NEXT:    ret
637; RV32IDZFH-NEXT:  .LBB10_9: # %start
638; RV32IDZFH-NEXT:    mv a0, a2
639; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
640; RV32IDZFH-NEXT:    bnez a2, .LBB10_4
641; RV32IDZFH-NEXT:  .LBB10_10: # %start
642; RV32IDZFH-NEXT:    mv a0, zero
643; RV32IDZFH-NEXT:    lui a4, 524288
644; RV32IDZFH-NEXT:    bnez s0, .LBB10_5
645; RV32IDZFH-NEXT:  .LBB10_11: # %start
646; RV32IDZFH-NEXT:    lui a1, 524288
647; RV32IDZFH-NEXT:    beqz a3, .LBB10_6
648; RV32IDZFH-NEXT:  .LBB10_12:
649; RV32IDZFH-NEXT:    addi a1, a4, -1
650; RV32IDZFH-NEXT:    beqz a2, .LBB10_7
651; RV32IDZFH-NEXT:    j .LBB10_8
652;
653; RV64IZFH-LABEL: fcvt_l_h_sat:
654; RV64IZFH:       # %bb.0: # %start
655; RV64IZFH-NEXT:    lui a0, %hi(.LCPI10_0)
656; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI10_0)(a0)
657; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
658; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
659; RV64IZFH-NEXT:    addi a1, zero, -1
660; RV64IZFH-NEXT:    bnez a0, .LBB10_2
661; RV64IZFH-NEXT:  # %bb.1: # %start
662; RV64IZFH-NEXT:    slli a0, a1, 63
663; RV64IZFH-NEXT:    j .LBB10_3
664; RV64IZFH-NEXT:  .LBB10_2:
665; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
666; RV64IZFH-NEXT:  .LBB10_3: # %start
667; RV64IZFH-NEXT:    lui a2, %hi(.LCPI10_1)
668; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI10_1)(a2)
669; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
670; RV64IZFH-NEXT:    bnez a2, .LBB10_6
671; RV64IZFH-NEXT:  # %bb.4: # %start
672; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
673; RV64IZFH-NEXT:    beqz a1, .LBB10_7
674; RV64IZFH-NEXT:  .LBB10_5: # %start
675; RV64IZFH-NEXT:    ret
676; RV64IZFH-NEXT:  .LBB10_6:
677; RV64IZFH-NEXT:    srli a0, a1, 1
678; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
679; RV64IZFH-NEXT:    bnez a1, .LBB10_5
680; RV64IZFH-NEXT:  .LBB10_7: # %start
681; RV64IZFH-NEXT:    mv a0, zero
682; RV64IZFH-NEXT:    ret
683;
684; RV64IDZFH-LABEL: fcvt_l_h_sat:
685; RV64IDZFH:       # %bb.0: # %start
686; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI10_0)
687; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI10_0)(a0)
688; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
689; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
690; RV64IDZFH-NEXT:    addi a1, zero, -1
691; RV64IDZFH-NEXT:    bnez a0, .LBB10_2
692; RV64IDZFH-NEXT:  # %bb.1: # %start
693; RV64IDZFH-NEXT:    slli a0, a1, 63
694; RV64IDZFH-NEXT:    j .LBB10_3
695; RV64IDZFH-NEXT:  .LBB10_2:
696; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
697; RV64IDZFH-NEXT:  .LBB10_3: # %start
698; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI10_1)
699; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI10_1)(a2)
700; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
701; RV64IDZFH-NEXT:    bnez a2, .LBB10_6
702; RV64IDZFH-NEXT:  # %bb.4: # %start
703; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
704; RV64IDZFH-NEXT:    beqz a1, .LBB10_7
705; RV64IDZFH-NEXT:  .LBB10_5: # %start
706; RV64IDZFH-NEXT:    ret
707; RV64IDZFH-NEXT:  .LBB10_6:
708; RV64IDZFH-NEXT:    srli a0, a1, 1
709; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
710; RV64IDZFH-NEXT:    bnez a1, .LBB10_5
711; RV64IDZFH-NEXT:  .LBB10_7: # %start
712; RV64IDZFH-NEXT:    mv a0, zero
713; RV64IDZFH-NEXT:    ret
714start:
715  %0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a)
716  ret i64 %0
717}
718declare i64 @llvm.fptosi.sat.i64.f16(half)
719
720define i64 @fcvt_lu_h(half %a) nounwind {
721; RV32IZFH-LABEL: fcvt_lu_h:
722; RV32IZFH:       # %bb.0:
723; RV32IZFH-NEXT:    addi sp, sp, -16
724; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
725; RV32IZFH-NEXT:    call __fixunshfdi@plt
726; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
727; RV32IZFH-NEXT:    addi sp, sp, 16
728; RV32IZFH-NEXT:    ret
729;
730; RV32IDZFH-LABEL: fcvt_lu_h:
731; RV32IDZFH:       # %bb.0:
732; RV32IDZFH-NEXT:    addi sp, sp, -16
733; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
734; RV32IDZFH-NEXT:    call __fixunshfdi@plt
735; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
736; RV32IDZFH-NEXT:    addi sp, sp, 16
737; RV32IDZFH-NEXT:    ret
738;
739; RV64IZFH-LABEL: fcvt_lu_h:
740; RV64IZFH:       # %bb.0:
741; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
742; RV64IZFH-NEXT:    ret
743;
744; RV64IDZFH-LABEL: fcvt_lu_h:
745; RV64IDZFH:       # %bb.0:
746; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
747; RV64IDZFH-NEXT:    ret
748  %1 = fptoui half %a to i64
749  ret i64 %1
750}
751
752define i64 @fcvt_lu_h_sat(half %a) nounwind {
753; RV32IZFH-LABEL: fcvt_lu_h_sat:
754; RV32IZFH:       # %bb.0: # %start
755; RV32IZFH-NEXT:    addi sp, sp, -16
756; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
757; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
758; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
759; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
760; RV32IZFH-NEXT:    fmv.w.x ft0, zero
761; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
762; RV32IZFH-NEXT:    fmv.s fa0, fs0
763; RV32IZFH-NEXT:    call __fixunssfdi@plt
764; RV32IZFH-NEXT:    mv a3, a0
765; RV32IZFH-NEXT:    bnez s0, .LBB12_2
766; RV32IZFH-NEXT:  # %bb.1: # %start
767; RV32IZFH-NEXT:    mv a3, zero
768; RV32IZFH-NEXT:  .LBB12_2: # %start
769; RV32IZFH-NEXT:    lui a0, %hi(.LCPI12_0)
770; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
771; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
772; RV32IZFH-NEXT:    addi a2, zero, -1
773; RV32IZFH-NEXT:    addi a0, zero, -1
774; RV32IZFH-NEXT:    beqz a4, .LBB12_7
775; RV32IZFH-NEXT:  # %bb.3: # %start
776; RV32IZFH-NEXT:    beqz s0, .LBB12_8
777; RV32IZFH-NEXT:  .LBB12_4: # %start
778; RV32IZFH-NEXT:    bnez a4, .LBB12_6
779; RV32IZFH-NEXT:  .LBB12_5: # %start
780; RV32IZFH-NEXT:    mv a2, a1
781; RV32IZFH-NEXT:  .LBB12_6: # %start
782; RV32IZFH-NEXT:    mv a1, a2
783; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
784; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
785; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
786; RV32IZFH-NEXT:    addi sp, sp, 16
787; RV32IZFH-NEXT:    ret
788; RV32IZFH-NEXT:  .LBB12_7: # %start
789; RV32IZFH-NEXT:    mv a0, a3
790; RV32IZFH-NEXT:    bnez s0, .LBB12_4
791; RV32IZFH-NEXT:  .LBB12_8: # %start
792; RV32IZFH-NEXT:    mv a1, zero
793; RV32IZFH-NEXT:    beqz a4, .LBB12_5
794; RV32IZFH-NEXT:    j .LBB12_6
795;
796; RV32IDZFH-LABEL: fcvt_lu_h_sat:
797; RV32IDZFH:       # %bb.0: # %start
798; RV32IDZFH-NEXT:    addi sp, sp, -16
799; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
800; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
801; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
802; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
803; RV32IDZFH-NEXT:    fmv.w.x ft0, zero
804; RV32IDZFH-NEXT:    fle.s s0, ft0, fs0
805; RV32IDZFH-NEXT:    fmv.s fa0, fs0
806; RV32IDZFH-NEXT:    call __fixunssfdi@plt
807; RV32IDZFH-NEXT:    mv a3, a0
808; RV32IDZFH-NEXT:    bnez s0, .LBB12_2
809; RV32IDZFH-NEXT:  # %bb.1: # %start
810; RV32IDZFH-NEXT:    mv a3, zero
811; RV32IDZFH-NEXT:  .LBB12_2: # %start
812; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI12_0)
813; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
814; RV32IDZFH-NEXT:    flt.s a4, ft0, fs0
815; RV32IDZFH-NEXT:    addi a2, zero, -1
816; RV32IDZFH-NEXT:    addi a0, zero, -1
817; RV32IDZFH-NEXT:    beqz a4, .LBB12_7
818; RV32IDZFH-NEXT:  # %bb.3: # %start
819; RV32IDZFH-NEXT:    beqz s0, .LBB12_8
820; RV32IDZFH-NEXT:  .LBB12_4: # %start
821; RV32IDZFH-NEXT:    bnez a4, .LBB12_6
822; RV32IDZFH-NEXT:  .LBB12_5: # %start
823; RV32IDZFH-NEXT:    mv a2, a1
824; RV32IDZFH-NEXT:  .LBB12_6: # %start
825; RV32IDZFH-NEXT:    mv a1, a2
826; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
827; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
828; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
829; RV32IDZFH-NEXT:    addi sp, sp, 16
830; RV32IDZFH-NEXT:    ret
831; RV32IDZFH-NEXT:  .LBB12_7: # %start
832; RV32IDZFH-NEXT:    mv a0, a3
833; RV32IDZFH-NEXT:    bnez s0, .LBB12_4
834; RV32IDZFH-NEXT:  .LBB12_8: # %start
835; RV32IDZFH-NEXT:    mv a1, zero
836; RV32IDZFH-NEXT:    beqz a4, .LBB12_5
837; RV32IDZFH-NEXT:    j .LBB12_6
838;
839; RV64IZFH-LABEL: fcvt_lu_h_sat:
840; RV64IZFH:       # %bb.0: # %start
841; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
842; RV64IZFH-NEXT:    fmv.w.x ft1, zero
843; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
844; RV64IZFH-NEXT:    bnez a0, .LBB12_2
845; RV64IZFH-NEXT:  # %bb.1: # %start
846; RV64IZFH-NEXT:    mv a1, zero
847; RV64IZFH-NEXT:    j .LBB12_3
848; RV64IZFH-NEXT:  .LBB12_2:
849; RV64IZFH-NEXT:    fcvt.lu.s a1, ft0, rtz
850; RV64IZFH-NEXT:  .LBB12_3: # %start
851; RV64IZFH-NEXT:    lui a0, %hi(.LCPI12_0)
852; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI12_0)(a0)
853; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
854; RV64IZFH-NEXT:    addi a0, zero, -1
855; RV64IZFH-NEXT:    bnez a2, .LBB12_5
856; RV64IZFH-NEXT:  # %bb.4: # %start
857; RV64IZFH-NEXT:    mv a0, a1
858; RV64IZFH-NEXT:  .LBB12_5: # %start
859; RV64IZFH-NEXT:    ret
860;
861; RV64IDZFH-LABEL: fcvt_lu_h_sat:
862; RV64IDZFH:       # %bb.0: # %start
863; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
864; RV64IDZFH-NEXT:    fmv.w.x ft1, zero
865; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
866; RV64IDZFH-NEXT:    bnez a0, .LBB12_2
867; RV64IDZFH-NEXT:  # %bb.1: # %start
868; RV64IDZFH-NEXT:    mv a1, zero
869; RV64IDZFH-NEXT:    j .LBB12_3
870; RV64IDZFH-NEXT:  .LBB12_2:
871; RV64IDZFH-NEXT:    fcvt.lu.s a1, ft0, rtz
872; RV64IDZFH-NEXT:  .LBB12_3: # %start
873; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI12_0)
874; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI12_0)(a0)
875; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
876; RV64IDZFH-NEXT:    addi a0, zero, -1
877; RV64IDZFH-NEXT:    bnez a2, .LBB12_5
878; RV64IDZFH-NEXT:  # %bb.4: # %start
879; RV64IDZFH-NEXT:    mv a0, a1
880; RV64IDZFH-NEXT:  .LBB12_5: # %start
881; RV64IDZFH-NEXT:    ret
882start:
883  %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)
884  ret i64 %0
885}
886declare i64 @llvm.fptoui.sat.i64.f16(half)
887
888define half @fcvt_h_si(i16 %a) nounwind {
889; RV32IZFH-LABEL: fcvt_h_si:
890; RV32IZFH:       # %bb.0:
891; RV32IZFH-NEXT:    slli a0, a0, 16
892; RV32IZFH-NEXT:    srai a0, a0, 16
893; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
894; RV32IZFH-NEXT:    ret
895;
896; RV32IDZFH-LABEL: fcvt_h_si:
897; RV32IDZFH:       # %bb.0:
898; RV32IDZFH-NEXT:    slli a0, a0, 16
899; RV32IDZFH-NEXT:    srai a0, a0, 16
900; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
901; RV32IDZFH-NEXT:    ret
902;
903; RV64IZFH-LABEL: fcvt_h_si:
904; RV64IZFH:       # %bb.0:
905; RV64IZFH-NEXT:    slli a0, a0, 48
906; RV64IZFH-NEXT:    srai a0, a0, 48
907; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
908; RV64IZFH-NEXT:    ret
909;
910; RV64IDZFH-LABEL: fcvt_h_si:
911; RV64IDZFH:       # %bb.0:
912; RV64IDZFH-NEXT:    slli a0, a0, 48
913; RV64IDZFH-NEXT:    srai a0, a0, 48
914; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
915; RV64IDZFH-NEXT:    ret
916  %1 = sitofp i16 %a to half
917  ret half %1
918}
919
920define half @fcvt_h_si_signext(i16 signext %a) nounwind {
921; RV32IZFH-LABEL: fcvt_h_si_signext:
922; RV32IZFH:       # %bb.0:
923; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
924; RV32IZFH-NEXT:    ret
925;
926; RV32IDZFH-LABEL: fcvt_h_si_signext:
927; RV32IDZFH:       # %bb.0:
928; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
929; RV32IDZFH-NEXT:    ret
930;
931; RV64IZFH-LABEL: fcvt_h_si_signext:
932; RV64IZFH:       # %bb.0:
933; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
934; RV64IZFH-NEXT:    ret
935;
936; RV64IDZFH-LABEL: fcvt_h_si_signext:
937; RV64IDZFH:       # %bb.0:
938; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
939; RV64IDZFH-NEXT:    ret
940  %1 = sitofp i16 %a to half
941  ret half %1
942}
943
944define half @fcvt_h_ui(i16 %a) nounwind {
945; RV32IZFH-LABEL: fcvt_h_ui:
946; RV32IZFH:       # %bb.0:
947; RV32IZFH-NEXT:    lui a1, 16
948; RV32IZFH-NEXT:    addi a1, a1, -1
949; RV32IZFH-NEXT:    and a0, a0, a1
950; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
951; RV32IZFH-NEXT:    ret
952;
953; RV32IDZFH-LABEL: fcvt_h_ui:
954; RV32IDZFH:       # %bb.0:
955; RV32IDZFH-NEXT:    lui a1, 16
956; RV32IDZFH-NEXT:    addi a1, a1, -1
957; RV32IDZFH-NEXT:    and a0, a0, a1
958; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
959; RV32IDZFH-NEXT:    ret
960;
961; RV64IZFH-LABEL: fcvt_h_ui:
962; RV64IZFH:       # %bb.0:
963; RV64IZFH-NEXT:    lui a1, 16
964; RV64IZFH-NEXT:    addiw a1, a1, -1
965; RV64IZFH-NEXT:    and a0, a0, a1
966; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
967; RV64IZFH-NEXT:    ret
968;
969; RV64IDZFH-LABEL: fcvt_h_ui:
970; RV64IDZFH:       # %bb.0:
971; RV64IDZFH-NEXT:    lui a1, 16
972; RV64IDZFH-NEXT:    addiw a1, a1, -1
973; RV64IDZFH-NEXT:    and a0, a0, a1
974; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
975; RV64IDZFH-NEXT:    ret
976  %1 = uitofp i16 %a to half
977  ret half %1
978}
979
980define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
981; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
982; RV32IZFH:       # %bb.0:
983; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
984; RV32IZFH-NEXT:    ret
985;
986; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
987; RV32IDZFH:       # %bb.0:
988; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
989; RV32IDZFH-NEXT:    ret
990;
991; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
992; RV64IZFH:       # %bb.0:
993; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
994; RV64IZFH-NEXT:    ret
995;
996; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
997; RV64IDZFH:       # %bb.0:
998; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
999; RV64IDZFH-NEXT:    ret
1000  %1 = uitofp i16 %a to half
1001  ret half %1
1002}
1003
1004define half @fcvt_h_w(i32 %a) nounwind {
1005; RV32IZFH-LABEL: fcvt_h_w:
1006; RV32IZFH:       # %bb.0:
1007; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
1008; RV32IZFH-NEXT:    ret
1009;
1010; RV32IDZFH-LABEL: fcvt_h_w:
1011; RV32IDZFH:       # %bb.0:
1012; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
1013; RV32IDZFH-NEXT:    ret
1014;
1015; RV64IZFH-LABEL: fcvt_h_w:
1016; RV64IZFH:       # %bb.0:
1017; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
1018; RV64IZFH-NEXT:    ret
1019;
1020; RV64IDZFH-LABEL: fcvt_h_w:
1021; RV64IDZFH:       # %bb.0:
1022; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
1023; RV64IDZFH-NEXT:    ret
1024  %1 = sitofp i32 %a to half
1025  ret half %1
1026}
1027
1028define half @fcvt_h_w_load(i32* %p) nounwind {
1029; RV32IZFH-LABEL: fcvt_h_w_load:
1030; RV32IZFH:       # %bb.0:
1031; RV32IZFH-NEXT:    lw a0, 0(a0)
1032; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
1033; RV32IZFH-NEXT:    ret
1034;
1035; RV32IDZFH-LABEL: fcvt_h_w_load:
1036; RV32IDZFH:       # %bb.0:
1037; RV32IDZFH-NEXT:    lw a0, 0(a0)
1038; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
1039; RV32IDZFH-NEXT:    ret
1040;
1041; RV64IZFH-LABEL: fcvt_h_w_load:
1042; RV64IZFH:       # %bb.0:
1043; RV64IZFH-NEXT:    lw a0, 0(a0)
1044; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
1045; RV64IZFH-NEXT:    ret
1046;
1047; RV64IDZFH-LABEL: fcvt_h_w_load:
1048; RV64IDZFH:       # %bb.0:
1049; RV64IDZFH-NEXT:    lw a0, 0(a0)
1050; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
1051; RV64IDZFH-NEXT:    ret
1052  %a = load i32, i32* %p
1053  %1 = sitofp i32 %a to half
1054  ret half %1
1055}
1056
1057define half @fcvt_h_wu(i32 %a) nounwind {
1058; RV32IZFH-LABEL: fcvt_h_wu:
1059; RV32IZFH:       # %bb.0:
1060; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
1061; RV32IZFH-NEXT:    ret
1062;
1063; RV32IDZFH-LABEL: fcvt_h_wu:
1064; RV32IDZFH:       # %bb.0:
1065; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
1066; RV32IDZFH-NEXT:    ret
1067;
1068; RV64IZFH-LABEL: fcvt_h_wu:
1069; RV64IZFH:       # %bb.0:
1070; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
1071; RV64IZFH-NEXT:    ret
1072;
1073; RV64IDZFH-LABEL: fcvt_h_wu:
1074; RV64IDZFH:       # %bb.0:
1075; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
1076; RV64IDZFH-NEXT:    ret
1077  %1 = uitofp i32 %a to half
1078  ret half %1
1079}
1080
1081define half @fcvt_h_wu_load(i32* %p) nounwind {
1082; RV32IZFH-LABEL: fcvt_h_wu_load:
1083; RV32IZFH:       # %bb.0:
1084; RV32IZFH-NEXT:    lw a0, 0(a0)
1085; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
1086; RV32IZFH-NEXT:    ret
1087;
1088; RV32IDZFH-LABEL: fcvt_h_wu_load:
1089; RV32IDZFH:       # %bb.0:
1090; RV32IDZFH-NEXT:    lw a0, 0(a0)
1091; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
1092; RV32IDZFH-NEXT:    ret
1093;
1094; RV64IZFH-LABEL: fcvt_h_wu_load:
1095; RV64IZFH:       # %bb.0:
1096; RV64IZFH-NEXT:    lwu a0, 0(a0)
1097; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
1098; RV64IZFH-NEXT:    ret
1099;
1100; RV64IDZFH-LABEL: fcvt_h_wu_load:
1101; RV64IDZFH:       # %bb.0:
1102; RV64IDZFH-NEXT:    lwu a0, 0(a0)
1103; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
1104; RV64IDZFH-NEXT:    ret
1105  %a = load i32, i32* %p
1106  %1 = uitofp i32 %a to half
1107  ret half %1
1108}
1109
1110define half @fcvt_h_l(i64 %a) nounwind {
1111; RV32IZFH-LABEL: fcvt_h_l:
1112; RV32IZFH:       # %bb.0:
1113; RV32IZFH-NEXT:    addi sp, sp, -16
1114; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1115; RV32IZFH-NEXT:    call __floatdihf@plt
1116; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1117; RV32IZFH-NEXT:    addi sp, sp, 16
1118; RV32IZFH-NEXT:    ret
1119;
1120; RV32IDZFH-LABEL: fcvt_h_l:
1121; RV32IDZFH:       # %bb.0:
1122; RV32IDZFH-NEXT:    addi sp, sp, -16
1123; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1124; RV32IDZFH-NEXT:    call __floatdihf@plt
1125; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1126; RV32IDZFH-NEXT:    addi sp, sp, 16
1127; RV32IDZFH-NEXT:    ret
1128;
1129; RV64IZFH-LABEL: fcvt_h_l:
1130; RV64IZFH:       # %bb.0:
1131; RV64IZFH-NEXT:    fcvt.h.l fa0, a0
1132; RV64IZFH-NEXT:    ret
1133;
1134; RV64IDZFH-LABEL: fcvt_h_l:
1135; RV64IDZFH:       # %bb.0:
1136; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
1137; RV64IDZFH-NEXT:    ret
1138  %1 = sitofp i64 %a to half
1139  ret half %1
1140}
1141
1142define half @fcvt_h_lu(i64 %a) nounwind {
1143; RV32IZFH-LABEL: fcvt_h_lu:
1144; RV32IZFH:       # %bb.0:
1145; RV32IZFH-NEXT:    addi sp, sp, -16
1146; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1147; RV32IZFH-NEXT:    call __floatundihf@plt
1148; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1149; RV32IZFH-NEXT:    addi sp, sp, 16
1150; RV32IZFH-NEXT:    ret
1151;
1152; RV32IDZFH-LABEL: fcvt_h_lu:
1153; RV32IDZFH:       # %bb.0:
1154; RV32IDZFH-NEXT:    addi sp, sp, -16
1155; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1156; RV32IDZFH-NEXT:    call __floatundihf@plt
1157; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1158; RV32IDZFH-NEXT:    addi sp, sp, 16
1159; RV32IDZFH-NEXT:    ret
1160;
1161; RV64IZFH-LABEL: fcvt_h_lu:
1162; RV64IZFH:       # %bb.0:
1163; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0
1164; RV64IZFH-NEXT:    ret
1165;
1166; RV64IDZFH-LABEL: fcvt_h_lu:
1167; RV64IDZFH:       # %bb.0:
1168; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
1169; RV64IDZFH-NEXT:    ret
1170  %1 = uitofp i64 %a to half
1171  ret half %1
1172}
1173
1174define half @fcvt_h_s(float %a) nounwind {
1175; RV32IZFH-LABEL: fcvt_h_s:
1176; RV32IZFH:       # %bb.0:
1177; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
1178; RV32IZFH-NEXT:    ret
1179;
1180; RV32IDZFH-LABEL: fcvt_h_s:
1181; RV32IDZFH:       # %bb.0:
1182; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
1183; RV32IDZFH-NEXT:    ret
1184;
1185; RV64IZFH-LABEL: fcvt_h_s:
1186; RV64IZFH:       # %bb.0:
1187; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
1188; RV64IZFH-NEXT:    ret
1189;
1190; RV64IDZFH-LABEL: fcvt_h_s:
1191; RV64IDZFH:       # %bb.0:
1192; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0
1193; RV64IDZFH-NEXT:    ret
1194  %1 = fptrunc float %a to half
1195  ret half %1
1196}
1197
1198define float @fcvt_s_h(half %a) nounwind {
1199; RV32IZFH-LABEL: fcvt_s_h:
1200; RV32IZFH:       # %bb.0:
1201; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
1202; RV32IZFH-NEXT:    ret
1203;
1204; RV32IDZFH-LABEL: fcvt_s_h:
1205; RV32IDZFH:       # %bb.0:
1206; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
1207; RV32IDZFH-NEXT:    ret
1208;
1209; RV64IZFH-LABEL: fcvt_s_h:
1210; RV64IZFH:       # %bb.0:
1211; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
1212; RV64IZFH-NEXT:    ret
1213;
1214; RV64IDZFH-LABEL: fcvt_s_h:
1215; RV64IDZFH:       # %bb.0:
1216; RV64IDZFH-NEXT:    fcvt.s.h fa0, fa0
1217; RV64IDZFH-NEXT:    ret
1218  %1 = fpext half %a to float
1219  ret float %1
1220}
1221
1222define half @fcvt_h_d(double %a) nounwind {
1223; RV32IZFH-LABEL: fcvt_h_d:
1224; RV32IZFH:       # %bb.0:
1225; RV32IZFH-NEXT:    addi sp, sp, -16
1226; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1227; RV32IZFH-NEXT:    call __truncdfhf2@plt
1228; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1229; RV32IZFH-NEXT:    addi sp, sp, 16
1230; RV32IZFH-NEXT:    ret
1231;
1232; RV32IDZFH-LABEL: fcvt_h_d:
1233; RV32IDZFH:       # %bb.0:
1234; RV32IDZFH-NEXT:    fcvt.h.d fa0, fa0
1235; RV32IDZFH-NEXT:    ret
1236;
1237; RV64IZFH-LABEL: fcvt_h_d:
1238; RV64IZFH:       # %bb.0:
1239; RV64IZFH-NEXT:    addi sp, sp, -16
1240; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1241; RV64IZFH-NEXT:    call __truncdfhf2@plt
1242; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1243; RV64IZFH-NEXT:    addi sp, sp, 16
1244; RV64IZFH-NEXT:    ret
1245;
1246; RV64IDZFH-LABEL: fcvt_h_d:
1247; RV64IDZFH:       # %bb.0:
1248; RV64IDZFH-NEXT:    fcvt.h.d fa0, fa0
1249; RV64IDZFH-NEXT:    ret
1250  %1 = fptrunc double %a to half
1251  ret half %1
1252}
1253
1254define double @fcvt_d_h(half %a) nounwind {
1255; RV32IZFH-LABEL: fcvt_d_h:
1256; RV32IZFH:       # %bb.0:
1257; RV32IZFH-NEXT:    addi sp, sp, -16
1258; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1259; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
1260; RV32IZFH-NEXT:    call __extendsfdf2@plt
1261; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1262; RV32IZFH-NEXT:    addi sp, sp, 16
1263; RV32IZFH-NEXT:    ret
1264;
1265; RV32IDZFH-LABEL: fcvt_d_h:
1266; RV32IDZFH:       # %bb.0:
1267; RV32IDZFH-NEXT:    fcvt.d.h fa0, fa0
1268; RV32IDZFH-NEXT:    ret
1269;
1270; RV64IZFH-LABEL: fcvt_d_h:
1271; RV64IZFH:       # %bb.0:
1272; RV64IZFH-NEXT:    addi sp, sp, -16
1273; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1274; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
1275; RV64IZFH-NEXT:    call __extendsfdf2@plt
1276; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1277; RV64IZFH-NEXT:    addi sp, sp, 16
1278; RV64IZFH-NEXT:    ret
1279;
1280; RV64IDZFH-LABEL: fcvt_d_h:
1281; RV64IDZFH:       # %bb.0:
1282; RV64IDZFH-NEXT:    fcvt.d.h fa0, fa0
1283; RV64IDZFH-NEXT:    ret
1284  %1 = fpext half %a to double
1285  ret double %1
1286}
1287
1288define half @bitcast_h_i16(i16 %a) nounwind {
1289; RV32IZFH-LABEL: bitcast_h_i16:
1290; RV32IZFH:       # %bb.0:
1291; RV32IZFH-NEXT:    fmv.h.x fa0, a0
1292; RV32IZFH-NEXT:    ret
1293;
1294; RV32IDZFH-LABEL: bitcast_h_i16:
1295; RV32IDZFH:       # %bb.0:
1296; RV32IDZFH-NEXT:    fmv.h.x fa0, a0
1297; RV32IDZFH-NEXT:    ret
1298;
1299; RV64IZFH-LABEL: bitcast_h_i16:
1300; RV64IZFH:       # %bb.0:
1301; RV64IZFH-NEXT:    fmv.h.x fa0, a0
1302; RV64IZFH-NEXT:    ret
1303;
1304; RV64IDZFH-LABEL: bitcast_h_i16:
1305; RV64IDZFH:       # %bb.0:
1306; RV64IDZFH-NEXT:    fmv.h.x fa0, a0
1307; RV64IDZFH-NEXT:    ret
1308  %1 = bitcast i16 %a to half
1309  ret half %1
1310}
1311
1312define i16 @bitcast_i16_h(half %a) nounwind {
1313; RV32IZFH-LABEL: bitcast_i16_h:
1314; RV32IZFH:       # %bb.0:
1315; RV32IZFH-NEXT:    fmv.x.h a0, fa0
1316; RV32IZFH-NEXT:    ret
1317;
1318; RV32IDZFH-LABEL: bitcast_i16_h:
1319; RV32IDZFH:       # %bb.0:
1320; RV32IDZFH-NEXT:    fmv.x.h a0, fa0
1321; RV32IDZFH-NEXT:    ret
1322;
1323; RV64IZFH-LABEL: bitcast_i16_h:
1324; RV64IZFH:       # %bb.0:
1325; RV64IZFH-NEXT:    fmv.x.h a0, fa0
1326; RV64IZFH-NEXT:    ret
1327;
1328; RV64IDZFH-LABEL: bitcast_i16_h:
1329; RV64IDZFH:       # %bb.0:
1330; RV64IDZFH-NEXT:    fmv.x.h a0, fa0
1331; RV64IDZFH-NEXT:    ret
1332  %1 = bitcast half %a to i16
1333  ret i16 %1
1334}
1335