1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
4; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh -verify-machineinstrs \
5; RUN:   -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
6; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
7; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
8; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh -verify-machineinstrs \
9; RUN:   -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
10
11define i16 @fcvt_si_h(half %a) nounwind {
12; RV32IZFH-LABEL: fcvt_si_h:
13; RV32IZFH:       # %bb.0:
14; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
15; RV32IZFH-NEXT:    ret
16;
17; RV32IDZFH-LABEL: fcvt_si_h:
18; RV32IDZFH:       # %bb.0:
19; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
20; RV32IDZFH-NEXT:    ret
21;
22; RV64IZFH-LABEL: fcvt_si_h:
23; RV64IZFH:       # %bb.0:
24; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
25; RV64IZFH-NEXT:    ret
26;
27; RV64IDZFH-LABEL: fcvt_si_h:
28; RV64IDZFH:       # %bb.0:
29; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
30; RV64IDZFH-NEXT:    ret
31  %1 = fptosi half %a to i16
32  ret i16 %1
33}
34
35define i16 @fcvt_si_h_sat(half %a) nounwind {
36; RV32IZFH-LABEL: fcvt_si_h_sat:
37; RV32IZFH:       # %bb.0: # %start
38; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
39; RV32IZFH-NEXT:    feq.s a0, ft0, ft0
40; RV32IZFH-NEXT:    bnez a0, .LBB1_2
41; RV32IZFH-NEXT:  # %bb.1: # %start
42; RV32IZFH-NEXT:    mv a0, zero
43; RV32IZFH-NEXT:    ret
44; RV32IZFH-NEXT:  .LBB1_2:
45; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
46; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
47; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_1)
48; RV32IZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
49; RV32IZFH-NEXT:    fmax.s ft0, ft0, ft1
50; RV32IZFH-NEXT:    fmin.s ft0, ft0, ft2
51; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
52; RV32IZFH-NEXT:    ret
53;
54; RV32IDZFH-LABEL: fcvt_si_h_sat:
55; RV32IDZFH:       # %bb.0: # %start
56; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
57; RV32IDZFH-NEXT:    feq.s a0, ft0, ft0
58; RV32IDZFH-NEXT:    bnez a0, .LBB1_2
59; RV32IDZFH-NEXT:  # %bb.1: # %start
60; RV32IDZFH-NEXT:    mv a0, zero
61; RV32IDZFH-NEXT:    ret
62; RV32IDZFH-NEXT:  .LBB1_2:
63; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI1_0)
64; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
65; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI1_1)
66; RV32IDZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
67; RV32IDZFH-NEXT:    fmax.s ft0, ft0, ft1
68; RV32IDZFH-NEXT:    fmin.s ft0, ft0, ft2
69; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
70; RV32IDZFH-NEXT:    ret
71;
72; RV64IZFH-LABEL: fcvt_si_h_sat:
73; RV64IZFH:       # %bb.0: # %start
74; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
75; RV64IZFH-NEXT:    feq.s a0, ft0, ft0
76; RV64IZFH-NEXT:    bnez a0, .LBB1_2
77; RV64IZFH-NEXT:  # %bb.1: # %start
78; RV64IZFH-NEXT:    mv a0, zero
79; RV64IZFH-NEXT:    ret
80; RV64IZFH-NEXT:  .LBB1_2:
81; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
82; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
83; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_1)
84; RV64IZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
85; RV64IZFH-NEXT:    fmax.s ft0, ft0, ft1
86; RV64IZFH-NEXT:    fmin.s ft0, ft0, ft2
87; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
88; RV64IZFH-NEXT:    ret
89;
90; RV64IDZFH-LABEL: fcvt_si_h_sat:
91; RV64IDZFH:       # %bb.0: # %start
92; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
93; RV64IDZFH-NEXT:    feq.s a0, ft0, ft0
94; RV64IDZFH-NEXT:    bnez a0, .LBB1_2
95; RV64IDZFH-NEXT:  # %bb.1: # %start
96; RV64IDZFH-NEXT:    mv a0, zero
97; RV64IDZFH-NEXT:    ret
98; RV64IDZFH-NEXT:  .LBB1_2:
99; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI1_0)
100; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
101; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI1_1)
102; RV64IDZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
103; RV64IDZFH-NEXT:    fmax.s ft0, ft0, ft1
104; RV64IDZFH-NEXT:    fmin.s ft0, ft0, ft2
105; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
106; RV64IDZFH-NEXT:    ret
107start:
108  %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
109  ret i16 %0
110}
111declare i16 @llvm.fptosi.sat.i16.f16(half)
112
113define i16 @fcvt_ui_h(half %a) nounwind {
114; RV32IZFH-LABEL: fcvt_ui_h:
115; RV32IZFH:       # %bb.0:
116; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
117; RV32IZFH-NEXT:    ret
118;
119; RV32IDZFH-LABEL: fcvt_ui_h:
120; RV32IDZFH:       # %bb.0:
121; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
122; RV32IDZFH-NEXT:    ret
123;
124; RV64IZFH-LABEL: fcvt_ui_h:
125; RV64IZFH:       # %bb.0:
126; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
127; RV64IZFH-NEXT:    ret
128;
129; RV64IDZFH-LABEL: fcvt_ui_h:
130; RV64IDZFH:       # %bb.0:
131; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
132; RV64IDZFH-NEXT:    ret
133  %1 = fptoui half %a to i16
134  ret i16 %1
135}
136
137define i16 @fcvt_ui_h_sat(half %a) nounwind {
138; RV32IZFH-LABEL: fcvt_ui_h_sat:
139; RV32IZFH:       # %bb.0: # %start
140; RV32IZFH-NEXT:    lui a0, %hi(.LCPI3_0)
141; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
142; RV32IZFH-NEXT:    fcvt.s.h ft1, fa0
143; RV32IZFH-NEXT:    fmv.w.x ft2, zero
144; RV32IZFH-NEXT:    fmax.s ft1, ft1, ft2
145; RV32IZFH-NEXT:    fmin.s ft0, ft1, ft0
146; RV32IZFH-NEXT:    fcvt.wu.s a0, ft0, rtz
147; RV32IZFH-NEXT:    ret
148;
149; RV32IDZFH-LABEL: fcvt_ui_h_sat:
150; RV32IDZFH:       # %bb.0: # %start
151; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI3_0)
152; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
153; RV32IDZFH-NEXT:    fcvt.s.h ft1, fa0
154; RV32IDZFH-NEXT:    fmv.w.x ft2, zero
155; RV32IDZFH-NEXT:    fmax.s ft1, ft1, ft2
156; RV32IDZFH-NEXT:    fmin.s ft0, ft1, ft0
157; RV32IDZFH-NEXT:    fcvt.wu.s a0, ft0, rtz
158; RV32IDZFH-NEXT:    ret
159;
160; RV64IZFH-LABEL: fcvt_ui_h_sat:
161; RV64IZFH:       # %bb.0: # %start
162; RV64IZFH-NEXT:    lui a0, %hi(.LCPI3_0)
163; RV64IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
164; RV64IZFH-NEXT:    fcvt.s.h ft1, fa0
165; RV64IZFH-NEXT:    fmv.w.x ft2, zero
166; RV64IZFH-NEXT:    fmax.s ft1, ft1, ft2
167; RV64IZFH-NEXT:    fmin.s ft0, ft1, ft0
168; RV64IZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
169; RV64IZFH-NEXT:    ret
170;
171; RV64IDZFH-LABEL: fcvt_ui_h_sat:
172; RV64IDZFH:       # %bb.0: # %start
173; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI3_0)
174; RV64IDZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
175; RV64IDZFH-NEXT:    fcvt.s.h ft1, fa0
176; RV64IDZFH-NEXT:    fmv.w.x ft2, zero
177; RV64IDZFH-NEXT:    fmax.s ft1, ft1, ft2
178; RV64IDZFH-NEXT:    fmin.s ft0, ft1, ft0
179; RV64IDZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
180; RV64IDZFH-NEXT:    ret
181start:
182  %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
183  ret i16 %0
184}
185declare i16 @llvm.fptoui.sat.i16.f16(half)
186
187define i32 @fcvt_w_h(half %a) nounwind {
188; RV32IZFH-LABEL: fcvt_w_h:
189; RV32IZFH:       # %bb.0:
190; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
191; RV32IZFH-NEXT:    ret
192;
193; RV32IDZFH-LABEL: fcvt_w_h:
194; RV32IDZFH:       # %bb.0:
195; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
196; RV32IDZFH-NEXT:    ret
197;
198; RV64IZFH-LABEL: fcvt_w_h:
199; RV64IZFH:       # %bb.0:
200; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
201; RV64IZFH-NEXT:    ret
202;
203; RV64IDZFH-LABEL: fcvt_w_h:
204; RV64IDZFH:       # %bb.0:
205; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
206; RV64IDZFH-NEXT:    ret
207  %1 = fptosi half %a to i32
208  ret i32 %1
209}
210
211define i32 @fcvt_w_h_sat(half %a) nounwind {
212; RV32IZFH-LABEL: fcvt_w_h_sat:
213; RV32IZFH:       # %bb.0: # %start
214; RV32IZFH-NEXT:    lui a0, %hi(.LCPI5_0)
215; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
216; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
217; RV32IZFH-NEXT:    fle.s a0, ft1, ft0
218; RV32IZFH-NEXT:    lui a1, 524288
219; RV32IZFH-NEXT:    bnez a0, .LBB5_2
220; RV32IZFH-NEXT:  # %bb.1: # %start
221; RV32IZFH-NEXT:    lui a0, 524288
222; RV32IZFH-NEXT:    j .LBB5_3
223; RV32IZFH-NEXT:  .LBB5_2:
224; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
225; RV32IZFH-NEXT:  .LBB5_3: # %start
226; RV32IZFH-NEXT:    lui a2, %hi(.LCPI5_1)
227; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
228; RV32IZFH-NEXT:    flt.s a2, ft1, ft0
229; RV32IZFH-NEXT:    bnez a2, .LBB5_6
230; RV32IZFH-NEXT:  # %bb.4: # %start
231; RV32IZFH-NEXT:    feq.s a1, ft0, ft0
232; RV32IZFH-NEXT:    beqz a1, .LBB5_7
233; RV32IZFH-NEXT:  .LBB5_5: # %start
234; RV32IZFH-NEXT:    ret
235; RV32IZFH-NEXT:  .LBB5_6:
236; RV32IZFH-NEXT:    addi a0, a1, -1
237; RV32IZFH-NEXT:    feq.s a1, ft0, ft0
238; RV32IZFH-NEXT:    bnez a1, .LBB5_5
239; RV32IZFH-NEXT:  .LBB5_7: # %start
240; RV32IZFH-NEXT:    mv a0, zero
241; RV32IZFH-NEXT:    ret
242;
243; RV32IDZFH-LABEL: fcvt_w_h_sat:
244; RV32IDZFH:       # %bb.0: # %start
245; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI5_0)
246; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
247; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
248; RV32IDZFH-NEXT:    fle.s a0, ft1, ft0
249; RV32IDZFH-NEXT:    lui a1, 524288
250; RV32IDZFH-NEXT:    bnez a0, .LBB5_2
251; RV32IDZFH-NEXT:  # %bb.1: # %start
252; RV32IDZFH-NEXT:    lui a0, 524288
253; RV32IDZFH-NEXT:    j .LBB5_3
254; RV32IDZFH-NEXT:  .LBB5_2:
255; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
256; RV32IDZFH-NEXT:  .LBB5_3: # %start
257; RV32IDZFH-NEXT:    lui a2, %hi(.LCPI5_1)
258; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
259; RV32IDZFH-NEXT:    flt.s a2, ft1, ft0
260; RV32IDZFH-NEXT:    bnez a2, .LBB5_6
261; RV32IDZFH-NEXT:  # %bb.4: # %start
262; RV32IDZFH-NEXT:    feq.s a1, ft0, ft0
263; RV32IDZFH-NEXT:    beqz a1, .LBB5_7
264; RV32IDZFH-NEXT:  .LBB5_5: # %start
265; RV32IDZFH-NEXT:    ret
266; RV32IDZFH-NEXT:  .LBB5_6:
267; RV32IDZFH-NEXT:    addi a0, a1, -1
268; RV32IDZFH-NEXT:    feq.s a1, ft0, ft0
269; RV32IDZFH-NEXT:    bnez a1, .LBB5_5
270; RV32IDZFH-NEXT:  .LBB5_7: # %start
271; RV32IDZFH-NEXT:    mv a0, zero
272; RV32IDZFH-NEXT:    ret
273;
274; RV64IZFH-LABEL: fcvt_w_h_sat:
275; RV64IZFH:       # %bb.0: # %start
276; RV64IZFH-NEXT:    lui a0, %hi(.LCPI5_0)
277; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
278; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
279; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
280; RV64IZFH-NEXT:    lui a1, 524288
281; RV64IZFH-NEXT:    bnez a0, .LBB5_2
282; RV64IZFH-NEXT:  # %bb.1: # %start
283; RV64IZFH-NEXT:    lui a0, 524288
284; RV64IZFH-NEXT:    j .LBB5_3
285; RV64IZFH-NEXT:  .LBB5_2:
286; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
287; RV64IZFH-NEXT:  .LBB5_3: # %start
288; RV64IZFH-NEXT:    lui a2, %hi(.LCPI5_1)
289; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
290; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
291; RV64IZFH-NEXT:    bnez a2, .LBB5_6
292; RV64IZFH-NEXT:  # %bb.4: # %start
293; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
294; RV64IZFH-NEXT:    beqz a1, .LBB5_7
295; RV64IZFH-NEXT:  .LBB5_5: # %start
296; RV64IZFH-NEXT:    ret
297; RV64IZFH-NEXT:  .LBB5_6:
298; RV64IZFH-NEXT:    addiw a0, a1, -1
299; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
300; RV64IZFH-NEXT:    bnez a1, .LBB5_5
301; RV64IZFH-NEXT:  .LBB5_7: # %start
302; RV64IZFH-NEXT:    mv a0, zero
303; RV64IZFH-NEXT:    ret
304;
305; RV64IDZFH-LABEL: fcvt_w_h_sat:
306; RV64IDZFH:       # %bb.0: # %start
307; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI5_0)
308; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI5_0)(a0)
309; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
310; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
311; RV64IDZFH-NEXT:    lui a1, 524288
312; RV64IDZFH-NEXT:    bnez a0, .LBB5_2
313; RV64IDZFH-NEXT:  # %bb.1: # %start
314; RV64IDZFH-NEXT:    lui a0, 524288
315; RV64IDZFH-NEXT:    j .LBB5_3
316; RV64IDZFH-NEXT:  .LBB5_2:
317; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
318; RV64IDZFH-NEXT:  .LBB5_3: # %start
319; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI5_1)
320; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI5_1)(a2)
321; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
322; RV64IDZFH-NEXT:    bnez a2, .LBB5_6
323; RV64IDZFH-NEXT:  # %bb.4: # %start
324; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
325; RV64IDZFH-NEXT:    beqz a1, .LBB5_7
326; RV64IDZFH-NEXT:  .LBB5_5: # %start
327; RV64IDZFH-NEXT:    ret
328; RV64IDZFH-NEXT:  .LBB5_6:
329; RV64IDZFH-NEXT:    addiw a0, a1, -1
330; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
331; RV64IDZFH-NEXT:    bnez a1, .LBB5_5
332; RV64IDZFH-NEXT:  .LBB5_7: # %start
333; RV64IDZFH-NEXT:    mv a0, zero
334; RV64IDZFH-NEXT:    ret
335start:
336  %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
337  ret i32 %0
338}
339declare i32 @llvm.fptosi.sat.i32.f16(half)
340
341define i32 @fcvt_wu_h(half %a) nounwind {
342; RV32IZFH-LABEL: fcvt_wu_h:
343; RV32IZFH:       # %bb.0:
344; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
345; RV32IZFH-NEXT:    ret
346;
347; RV32IDZFH-LABEL: fcvt_wu_h:
348; RV32IDZFH:       # %bb.0:
349; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
350; RV32IDZFH-NEXT:    ret
351;
352; RV64IZFH-LABEL: fcvt_wu_h:
353; RV64IZFH:       # %bb.0:
354; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
355; RV64IZFH-NEXT:    ret
356;
357; RV64IDZFH-LABEL: fcvt_wu_h:
358; RV64IDZFH:       # %bb.0:
359; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
360; RV64IDZFH-NEXT:    ret
361  %1 = fptoui half %a to i32
362  ret i32 %1
363}
364
365define i32 @fcvt_wu_h_sat(half %a) nounwind {
366; RV32IZFH-LABEL: fcvt_wu_h_sat:
367; RV32IZFH:       # %bb.0: # %start
368; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
369; RV32IZFH-NEXT:    fmv.w.x ft1, zero
370; RV32IZFH-NEXT:    fle.s a0, ft1, ft0
371; RV32IZFH-NEXT:    bnez a0, .LBB7_2
372; RV32IZFH-NEXT:  # %bb.1: # %start
373; RV32IZFH-NEXT:    mv a1, zero
374; RV32IZFH-NEXT:    j .LBB7_3
375; RV32IZFH-NEXT:  .LBB7_2:
376; RV32IZFH-NEXT:    fcvt.wu.s a1, ft0, rtz
377; RV32IZFH-NEXT:  .LBB7_3: # %start
378; RV32IZFH-NEXT:    lui a0, %hi(.LCPI7_0)
379; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
380; RV32IZFH-NEXT:    flt.s a2, ft1, ft0
381; RV32IZFH-NEXT:    addi a0, zero, -1
382; RV32IZFH-NEXT:    bnez a2, .LBB7_5
383; RV32IZFH-NEXT:  # %bb.4: # %start
384; RV32IZFH-NEXT:    mv a0, a1
385; RV32IZFH-NEXT:  .LBB7_5: # %start
386; RV32IZFH-NEXT:    ret
387;
388; RV32IDZFH-LABEL: fcvt_wu_h_sat:
389; RV32IDZFH:       # %bb.0: # %start
390; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
391; RV32IDZFH-NEXT:    fmv.w.x ft1, zero
392; RV32IDZFH-NEXT:    fle.s a0, ft1, ft0
393; RV32IDZFH-NEXT:    bnez a0, .LBB7_2
394; RV32IDZFH-NEXT:  # %bb.1: # %start
395; RV32IDZFH-NEXT:    mv a1, zero
396; RV32IDZFH-NEXT:    j .LBB7_3
397; RV32IDZFH-NEXT:  .LBB7_2:
398; RV32IDZFH-NEXT:    fcvt.wu.s a1, ft0, rtz
399; RV32IDZFH-NEXT:  .LBB7_3: # %start
400; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI7_0)
401; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a0)
402; RV32IDZFH-NEXT:    flt.s a2, ft1, ft0
403; RV32IDZFH-NEXT:    addi a0, zero, -1
404; RV32IDZFH-NEXT:    bnez a2, .LBB7_5
405; RV32IDZFH-NEXT:  # %bb.4: # %start
406; RV32IDZFH-NEXT:    mv a0, a1
407; RV32IDZFH-NEXT:  .LBB7_5: # %start
408; RV32IDZFH-NEXT:    ret
409;
410; RV64IZFH-LABEL: fcvt_wu_h_sat:
411; RV64IZFH:       # %bb.0: # %start
412; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
413; RV64IZFH-NEXT:    fmv.w.x ft1, zero
414; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
415; RV64IZFH-NEXT:    bnez a0, .LBB7_2
416; RV64IZFH-NEXT:  # %bb.1: # %start
417; RV64IZFH-NEXT:    mv a0, zero
418; RV64IZFH-NEXT:    j .LBB7_3
419; RV64IZFH-NEXT:  .LBB7_2:
420; RV64IZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
421; RV64IZFH-NEXT:  .LBB7_3: # %start
422; RV64IZFH-NEXT:    lui a1, %hi(.LCPI7_0)
423; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a1)
424; RV64IZFH-NEXT:    flt.s a1, ft1, ft0
425; RV64IZFH-NEXT:    beqz a1, .LBB7_5
426; RV64IZFH-NEXT:  # %bb.4:
427; RV64IZFH-NEXT:    addi a0, zero, -1
428; RV64IZFH-NEXT:    srli a0, a0, 32
429; RV64IZFH-NEXT:  .LBB7_5: # %start
430; RV64IZFH-NEXT:    ret
431;
432; RV64IDZFH-LABEL: fcvt_wu_h_sat:
433; RV64IDZFH:       # %bb.0: # %start
434; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
435; RV64IDZFH-NEXT:    fmv.w.x ft1, zero
436; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
437; RV64IDZFH-NEXT:    bnez a0, .LBB7_2
438; RV64IDZFH-NEXT:  # %bb.1: # %start
439; RV64IDZFH-NEXT:    mv a0, zero
440; RV64IDZFH-NEXT:    j .LBB7_3
441; RV64IDZFH-NEXT:  .LBB7_2:
442; RV64IDZFH-NEXT:    fcvt.lu.s a0, ft0, rtz
443; RV64IDZFH-NEXT:  .LBB7_3: # %start
444; RV64IDZFH-NEXT:    lui a1, %hi(.LCPI7_0)
445; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI7_0)(a1)
446; RV64IDZFH-NEXT:    flt.s a1, ft1, ft0
447; RV64IDZFH-NEXT:    beqz a1, .LBB7_5
448; RV64IDZFH-NEXT:  # %bb.4:
449; RV64IDZFH-NEXT:    addi a0, zero, -1
450; RV64IDZFH-NEXT:    srli a0, a0, 32
451; RV64IDZFH-NEXT:  .LBB7_5: # %start
452; RV64IDZFH-NEXT:    ret
453start:
454  %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
455  ret i32 %0
456}
457declare i32 @llvm.fptoui.sat.i32.f16(half)
458
459define i64 @fcvt_l_h(half %a) nounwind {
460; RV32IZFH-LABEL: fcvt_l_h:
461; RV32IZFH:       # %bb.0:
462; RV32IZFH-NEXT:    addi sp, sp, -16
463; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
464; RV32IZFH-NEXT:    call __fixhfdi@plt
465; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
466; RV32IZFH-NEXT:    addi sp, sp, 16
467; RV32IZFH-NEXT:    ret
468;
469; RV32IDZFH-LABEL: fcvt_l_h:
470; RV32IDZFH:       # %bb.0:
471; RV32IDZFH-NEXT:    addi sp, sp, -16
472; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
473; RV32IDZFH-NEXT:    call __fixhfdi@plt
474; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
475; RV32IDZFH-NEXT:    addi sp, sp, 16
476; RV32IDZFH-NEXT:    ret
477;
478; RV64IZFH-LABEL: fcvt_l_h:
479; RV64IZFH:       # %bb.0:
480; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
481; RV64IZFH-NEXT:    ret
482;
483; RV64IDZFH-LABEL: fcvt_l_h:
484; RV64IDZFH:       # %bb.0:
485; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
486; RV64IDZFH-NEXT:    ret
487  %1 = fptosi half %a to i64
488  ret i64 %1
489}
490
491define i64 @fcvt_l_h_sat(half %a) nounwind {
492; RV32IZFH-LABEL: fcvt_l_h_sat:
493; RV32IZFH:       # %bb.0: # %start
494; RV32IZFH-NEXT:    addi sp, sp, -16
495; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
496; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
497; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
498; RV32IZFH-NEXT:    lui a0, %hi(.LCPI9_0)
499; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
500; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
501; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
502; RV32IZFH-NEXT:    fmv.s fa0, fs0
503; RV32IZFH-NEXT:    call __fixsfdi@plt
504; RV32IZFH-NEXT:    mv a2, a0
505; RV32IZFH-NEXT:    bnez s0, .LBB9_2
506; RV32IZFH-NEXT:  # %bb.1: # %start
507; RV32IZFH-NEXT:    mv a2, zero
508; RV32IZFH-NEXT:  .LBB9_2: # %start
509; RV32IZFH-NEXT:    lui a0, %hi(.LCPI9_1)
510; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
511; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
512; RV32IZFH-NEXT:    addi a0, zero, -1
513; RV32IZFH-NEXT:    beqz a3, .LBB9_9
514; RV32IZFH-NEXT:  # %bb.3: # %start
515; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
516; RV32IZFH-NEXT:    beqz a2, .LBB9_10
517; RV32IZFH-NEXT:  .LBB9_4: # %start
518; RV32IZFH-NEXT:    lui a4, 524288
519; RV32IZFH-NEXT:    beqz s0, .LBB9_11
520; RV32IZFH-NEXT:  .LBB9_5: # %start
521; RV32IZFH-NEXT:    bnez a3, .LBB9_12
522; RV32IZFH-NEXT:  .LBB9_6: # %start
523; RV32IZFH-NEXT:    bnez a2, .LBB9_8
524; RV32IZFH-NEXT:  .LBB9_7: # %start
525; RV32IZFH-NEXT:    mv a1, zero
526; RV32IZFH-NEXT:  .LBB9_8: # %start
527; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
528; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
529; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
530; RV32IZFH-NEXT:    addi sp, sp, 16
531; RV32IZFH-NEXT:    ret
532; RV32IZFH-NEXT:  .LBB9_9: # %start
533; RV32IZFH-NEXT:    mv a0, a2
534; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
535; RV32IZFH-NEXT:    bnez a2, .LBB9_4
536; RV32IZFH-NEXT:  .LBB9_10: # %start
537; RV32IZFH-NEXT:    mv a0, zero
538; RV32IZFH-NEXT:    lui a4, 524288
539; RV32IZFH-NEXT:    bnez s0, .LBB9_5
540; RV32IZFH-NEXT:  .LBB9_11: # %start
541; RV32IZFH-NEXT:    lui a1, 524288
542; RV32IZFH-NEXT:    beqz a3, .LBB9_6
543; RV32IZFH-NEXT:  .LBB9_12:
544; RV32IZFH-NEXT:    addi a1, a4, -1
545; RV32IZFH-NEXT:    beqz a2, .LBB9_7
546; RV32IZFH-NEXT:    j .LBB9_8
547;
548; RV32IDZFH-LABEL: fcvt_l_h_sat:
549; RV32IDZFH:       # %bb.0: # %start
550; RV32IDZFH-NEXT:    addi sp, sp, -16
551; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
552; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
553; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
554; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI9_0)
555; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
556; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
557; RV32IDZFH-NEXT:    fle.s s0, ft0, fs0
558; RV32IDZFH-NEXT:    fmv.s fa0, fs0
559; RV32IDZFH-NEXT:    call __fixsfdi@plt
560; RV32IDZFH-NEXT:    mv a2, a0
561; RV32IDZFH-NEXT:    bnez s0, .LBB9_2
562; RV32IDZFH-NEXT:  # %bb.1: # %start
563; RV32IDZFH-NEXT:    mv a2, zero
564; RV32IDZFH-NEXT:  .LBB9_2: # %start
565; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI9_1)
566; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
567; RV32IDZFH-NEXT:    flt.s a3, ft0, fs0
568; RV32IDZFH-NEXT:    addi a0, zero, -1
569; RV32IDZFH-NEXT:    beqz a3, .LBB9_9
570; RV32IDZFH-NEXT:  # %bb.3: # %start
571; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
572; RV32IDZFH-NEXT:    beqz a2, .LBB9_10
573; RV32IDZFH-NEXT:  .LBB9_4: # %start
574; RV32IDZFH-NEXT:    lui a4, 524288
575; RV32IDZFH-NEXT:    beqz s0, .LBB9_11
576; RV32IDZFH-NEXT:  .LBB9_5: # %start
577; RV32IDZFH-NEXT:    bnez a3, .LBB9_12
578; RV32IDZFH-NEXT:  .LBB9_6: # %start
579; RV32IDZFH-NEXT:    bnez a2, .LBB9_8
580; RV32IDZFH-NEXT:  .LBB9_7: # %start
581; RV32IDZFH-NEXT:    mv a1, zero
582; RV32IDZFH-NEXT:  .LBB9_8: # %start
583; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
584; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
585; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
586; RV32IDZFH-NEXT:    addi sp, sp, 16
587; RV32IDZFH-NEXT:    ret
588; RV32IDZFH-NEXT:  .LBB9_9: # %start
589; RV32IDZFH-NEXT:    mv a0, a2
590; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
591; RV32IDZFH-NEXT:    bnez a2, .LBB9_4
592; RV32IDZFH-NEXT:  .LBB9_10: # %start
593; RV32IDZFH-NEXT:    mv a0, zero
594; RV32IDZFH-NEXT:    lui a4, 524288
595; RV32IDZFH-NEXT:    bnez s0, .LBB9_5
596; RV32IDZFH-NEXT:  .LBB9_11: # %start
597; RV32IDZFH-NEXT:    lui a1, 524288
598; RV32IDZFH-NEXT:    beqz a3, .LBB9_6
599; RV32IDZFH-NEXT:  .LBB9_12:
600; RV32IDZFH-NEXT:    addi a1, a4, -1
601; RV32IDZFH-NEXT:    beqz a2, .LBB9_7
602; RV32IDZFH-NEXT:    j .LBB9_8
603;
604; RV64IZFH-LABEL: fcvt_l_h_sat:
605; RV64IZFH:       # %bb.0: # %start
606; RV64IZFH-NEXT:    lui a0, %hi(.LCPI9_0)
607; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
608; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
609; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
610; RV64IZFH-NEXT:    addi a1, zero, -1
611; RV64IZFH-NEXT:    bnez a0, .LBB9_2
612; RV64IZFH-NEXT:  # %bb.1: # %start
613; RV64IZFH-NEXT:    slli a0, a1, 63
614; RV64IZFH-NEXT:    j .LBB9_3
615; RV64IZFH-NEXT:  .LBB9_2:
616; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
617; RV64IZFH-NEXT:  .LBB9_3: # %start
618; RV64IZFH-NEXT:    lui a2, %hi(.LCPI9_1)
619; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI9_1)(a2)
620; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
621; RV64IZFH-NEXT:    bnez a2, .LBB9_6
622; RV64IZFH-NEXT:  # %bb.4: # %start
623; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
624; RV64IZFH-NEXT:    beqz a1, .LBB9_7
625; RV64IZFH-NEXT:  .LBB9_5: # %start
626; RV64IZFH-NEXT:    ret
627; RV64IZFH-NEXT:  .LBB9_6:
628; RV64IZFH-NEXT:    srli a0, a1, 1
629; RV64IZFH-NEXT:    feq.s a1, ft0, ft0
630; RV64IZFH-NEXT:    bnez a1, .LBB9_5
631; RV64IZFH-NEXT:  .LBB9_7: # %start
632; RV64IZFH-NEXT:    mv a0, zero
633; RV64IZFH-NEXT:    ret
634;
635; RV64IDZFH-LABEL: fcvt_l_h_sat:
636; RV64IDZFH:       # %bb.0: # %start
637; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI9_0)
638; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI9_0)(a0)
639; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
640; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
641; RV64IDZFH-NEXT:    addi a1, zero, -1
642; RV64IDZFH-NEXT:    bnez a0, .LBB9_2
643; RV64IDZFH-NEXT:  # %bb.1: # %start
644; RV64IDZFH-NEXT:    slli a0, a1, 63
645; RV64IDZFH-NEXT:    j .LBB9_3
646; RV64IDZFH-NEXT:  .LBB9_2:
647; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
648; RV64IDZFH-NEXT:  .LBB9_3: # %start
649; RV64IDZFH-NEXT:    lui a2, %hi(.LCPI9_1)
650; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI9_1)(a2)
651; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
652; RV64IDZFH-NEXT:    bnez a2, .LBB9_6
653; RV64IDZFH-NEXT:  # %bb.4: # %start
654; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
655; RV64IDZFH-NEXT:    beqz a1, .LBB9_7
656; RV64IDZFH-NEXT:  .LBB9_5: # %start
657; RV64IDZFH-NEXT:    ret
658; RV64IDZFH-NEXT:  .LBB9_6:
659; RV64IDZFH-NEXT:    srli a0, a1, 1
660; RV64IDZFH-NEXT:    feq.s a1, ft0, ft0
661; RV64IDZFH-NEXT:    bnez a1, .LBB9_5
662; RV64IDZFH-NEXT:  .LBB9_7: # %start
663; RV64IDZFH-NEXT:    mv a0, zero
664; RV64IDZFH-NEXT:    ret
665start:
666  %0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a)
667  ret i64 %0
668}
669declare i64 @llvm.fptosi.sat.i64.f16(half)
670
671define i64 @fcvt_lu_h(half %a) nounwind {
672; RV32IZFH-LABEL: fcvt_lu_h:
673; RV32IZFH:       # %bb.0:
674; RV32IZFH-NEXT:    addi sp, sp, -16
675; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
676; RV32IZFH-NEXT:    call __fixunshfdi@plt
677; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
678; RV32IZFH-NEXT:    addi sp, sp, 16
679; RV32IZFH-NEXT:    ret
680;
681; RV32IDZFH-LABEL: fcvt_lu_h:
682; RV32IDZFH:       # %bb.0:
683; RV32IDZFH-NEXT:    addi sp, sp, -16
684; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
685; RV32IDZFH-NEXT:    call __fixunshfdi@plt
686; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
687; RV32IDZFH-NEXT:    addi sp, sp, 16
688; RV32IDZFH-NEXT:    ret
689;
690; RV64IZFH-LABEL: fcvt_lu_h:
691; RV64IZFH:       # %bb.0:
692; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
693; RV64IZFH-NEXT:    ret
694;
695; RV64IDZFH-LABEL: fcvt_lu_h:
696; RV64IDZFH:       # %bb.0:
697; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
698; RV64IDZFH-NEXT:    ret
699  %1 = fptoui half %a to i64
700  ret i64 %1
701}
702
703define i64 @fcvt_lu_h_sat(half %a) nounwind {
704; RV32IZFH-LABEL: fcvt_lu_h_sat:
705; RV32IZFH:       # %bb.0: # %start
706; RV32IZFH-NEXT:    addi sp, sp, -16
707; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
708; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
709; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
710; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
711; RV32IZFH-NEXT:    fmv.w.x ft0, zero
712; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
713; RV32IZFH-NEXT:    fmv.s fa0, fs0
714; RV32IZFH-NEXT:    call __fixunssfdi@plt
715; RV32IZFH-NEXT:    mv a3, a0
716; RV32IZFH-NEXT:    bnez s0, .LBB11_2
717; RV32IZFH-NEXT:  # %bb.1: # %start
718; RV32IZFH-NEXT:    mv a3, zero
719; RV32IZFH-NEXT:  .LBB11_2: # %start
720; RV32IZFH-NEXT:    lui a0, %hi(.LCPI11_0)
721; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
722; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
723; RV32IZFH-NEXT:    addi a2, zero, -1
724; RV32IZFH-NEXT:    addi a0, zero, -1
725; RV32IZFH-NEXT:    beqz a4, .LBB11_7
726; RV32IZFH-NEXT:  # %bb.3: # %start
727; RV32IZFH-NEXT:    beqz s0, .LBB11_8
728; RV32IZFH-NEXT:  .LBB11_4: # %start
729; RV32IZFH-NEXT:    bnez a4, .LBB11_6
730; RV32IZFH-NEXT:  .LBB11_5: # %start
731; RV32IZFH-NEXT:    mv a2, a1
732; RV32IZFH-NEXT:  .LBB11_6: # %start
733; RV32IZFH-NEXT:    mv a1, a2
734; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
735; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
736; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
737; RV32IZFH-NEXT:    addi sp, sp, 16
738; RV32IZFH-NEXT:    ret
739; RV32IZFH-NEXT:  .LBB11_7: # %start
740; RV32IZFH-NEXT:    mv a0, a3
741; RV32IZFH-NEXT:    bnez s0, .LBB11_4
742; RV32IZFH-NEXT:  .LBB11_8: # %start
743; RV32IZFH-NEXT:    mv a1, zero
744; RV32IZFH-NEXT:    beqz a4, .LBB11_5
745; RV32IZFH-NEXT:    j .LBB11_6
746;
747; RV32IDZFH-LABEL: fcvt_lu_h_sat:
748; RV32IDZFH:       # %bb.0: # %start
749; RV32IDZFH-NEXT:    addi sp, sp, -16
750; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
751; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
752; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
753; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
754; RV32IDZFH-NEXT:    fmv.w.x ft0, zero
755; RV32IDZFH-NEXT:    fle.s s0, ft0, fs0
756; RV32IDZFH-NEXT:    fmv.s fa0, fs0
757; RV32IDZFH-NEXT:    call __fixunssfdi@plt
758; RV32IDZFH-NEXT:    mv a3, a0
759; RV32IDZFH-NEXT:    bnez s0, .LBB11_2
760; RV32IDZFH-NEXT:  # %bb.1: # %start
761; RV32IDZFH-NEXT:    mv a3, zero
762; RV32IDZFH-NEXT:  .LBB11_2: # %start
763; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI11_0)
764; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
765; RV32IDZFH-NEXT:    flt.s a4, ft0, fs0
766; RV32IDZFH-NEXT:    addi a2, zero, -1
767; RV32IDZFH-NEXT:    addi a0, zero, -1
768; RV32IDZFH-NEXT:    beqz a4, .LBB11_7
769; RV32IDZFH-NEXT:  # %bb.3: # %start
770; RV32IDZFH-NEXT:    beqz s0, .LBB11_8
771; RV32IDZFH-NEXT:  .LBB11_4: # %start
772; RV32IDZFH-NEXT:    bnez a4, .LBB11_6
773; RV32IDZFH-NEXT:  .LBB11_5: # %start
774; RV32IDZFH-NEXT:    mv a2, a1
775; RV32IDZFH-NEXT:  .LBB11_6: # %start
776; RV32IDZFH-NEXT:    mv a1, a2
777; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
778; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
779; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
780; RV32IDZFH-NEXT:    addi sp, sp, 16
781; RV32IDZFH-NEXT:    ret
782; RV32IDZFH-NEXT:  .LBB11_7: # %start
783; RV32IDZFH-NEXT:    mv a0, a3
784; RV32IDZFH-NEXT:    bnez s0, .LBB11_4
785; RV32IDZFH-NEXT:  .LBB11_8: # %start
786; RV32IDZFH-NEXT:    mv a1, zero
787; RV32IDZFH-NEXT:    beqz a4, .LBB11_5
788; RV32IDZFH-NEXT:    j .LBB11_6
789;
790; RV64IZFH-LABEL: fcvt_lu_h_sat:
791; RV64IZFH:       # %bb.0: # %start
792; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
793; RV64IZFH-NEXT:    fmv.w.x ft1, zero
794; RV64IZFH-NEXT:    fle.s a0, ft1, ft0
795; RV64IZFH-NEXT:    bnez a0, .LBB11_2
796; RV64IZFH-NEXT:  # %bb.1: # %start
797; RV64IZFH-NEXT:    mv a1, zero
798; RV64IZFH-NEXT:    j .LBB11_3
799; RV64IZFH-NEXT:  .LBB11_2:
800; RV64IZFH-NEXT:    fcvt.lu.s a1, ft0, rtz
801; RV64IZFH-NEXT:  .LBB11_3: # %start
802; RV64IZFH-NEXT:    lui a0, %hi(.LCPI11_0)
803; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
804; RV64IZFH-NEXT:    flt.s a2, ft1, ft0
805; RV64IZFH-NEXT:    addi a0, zero, -1
806; RV64IZFH-NEXT:    bnez a2, .LBB11_5
807; RV64IZFH-NEXT:  # %bb.4: # %start
808; RV64IZFH-NEXT:    mv a0, a1
809; RV64IZFH-NEXT:  .LBB11_5: # %start
810; RV64IZFH-NEXT:    ret
811;
812; RV64IDZFH-LABEL: fcvt_lu_h_sat:
813; RV64IDZFH:       # %bb.0: # %start
814; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
815; RV64IDZFH-NEXT:    fmv.w.x ft1, zero
816; RV64IDZFH-NEXT:    fle.s a0, ft1, ft0
817; RV64IDZFH-NEXT:    bnez a0, .LBB11_2
818; RV64IDZFH-NEXT:  # %bb.1: # %start
819; RV64IDZFH-NEXT:    mv a1, zero
820; RV64IDZFH-NEXT:    j .LBB11_3
821; RV64IDZFH-NEXT:  .LBB11_2:
822; RV64IDZFH-NEXT:    fcvt.lu.s a1, ft0, rtz
823; RV64IDZFH-NEXT:  .LBB11_3: # %start
824; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI11_0)
825; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
826; RV64IDZFH-NEXT:    flt.s a2, ft1, ft0
827; RV64IDZFH-NEXT:    addi a0, zero, -1
828; RV64IDZFH-NEXT:    bnez a2, .LBB11_5
829; RV64IDZFH-NEXT:  # %bb.4: # %start
830; RV64IDZFH-NEXT:    mv a0, a1
831; RV64IDZFH-NEXT:  .LBB11_5: # %start
832; RV64IDZFH-NEXT:    ret
833start:
834  %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)
835  ret i64 %0
836}
837declare i64 @llvm.fptoui.sat.i64.f16(half)
838
839define half @fcvt_h_si(i16 %a) nounwind {
840; RV32IZFH-LABEL: fcvt_h_si:
841; RV32IZFH:       # %bb.0:
842; RV32IZFH-NEXT:    slli a0, a0, 16
843; RV32IZFH-NEXT:    srai a0, a0, 16
844; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
845; RV32IZFH-NEXT:    ret
846;
847; RV32IDZFH-LABEL: fcvt_h_si:
848; RV32IDZFH:       # %bb.0:
849; RV32IDZFH-NEXT:    slli a0, a0, 16
850; RV32IDZFH-NEXT:    srai a0, a0, 16
851; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
852; RV32IDZFH-NEXT:    ret
853;
854; RV64IZFH-LABEL: fcvt_h_si:
855; RV64IZFH:       # %bb.0:
856; RV64IZFH-NEXT:    slli a0, a0, 48
857; RV64IZFH-NEXT:    srai a0, a0, 48
858; RV64IZFH-NEXT:    fcvt.h.l fa0, a0
859; RV64IZFH-NEXT:    ret
860;
861; RV64IDZFH-LABEL: fcvt_h_si:
862; RV64IDZFH:       # %bb.0:
863; RV64IDZFH-NEXT:    slli a0, a0, 48
864; RV64IDZFH-NEXT:    srai a0, a0, 48
865; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
866; RV64IDZFH-NEXT:    ret
867  %1 = sitofp i16 %a to half
868  ret half %1
869}
870
871define half @fcvt_h_si_signext(i16 signext %a) nounwind {
872; RV32IZFH-LABEL: fcvt_h_si_signext:
873; RV32IZFH:       # %bb.0:
874; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
875; RV32IZFH-NEXT:    ret
876;
877; RV32IDZFH-LABEL: fcvt_h_si_signext:
878; RV32IDZFH:       # %bb.0:
879; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
880; RV32IDZFH-NEXT:    ret
881;
882; RV64IZFH-LABEL: fcvt_h_si_signext:
883; RV64IZFH:       # %bb.0:
884; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
885; RV64IZFH-NEXT:    ret
886;
887; RV64IDZFH-LABEL: fcvt_h_si_signext:
888; RV64IDZFH:       # %bb.0:
889; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
890; RV64IDZFH-NEXT:    ret
891  %1 = sitofp i16 %a to half
892  ret half %1
893}
894
895define half @fcvt_h_ui(i16 %a) nounwind {
896; RV32IZFH-LABEL: fcvt_h_ui:
897; RV32IZFH:       # %bb.0:
898; RV32IZFH-NEXT:    lui a1, 16
899; RV32IZFH-NEXT:    addi a1, a1, -1
900; RV32IZFH-NEXT:    and a0, a0, a1
901; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
902; RV32IZFH-NEXT:    ret
903;
904; RV32IDZFH-LABEL: fcvt_h_ui:
905; RV32IDZFH:       # %bb.0:
906; RV32IDZFH-NEXT:    lui a1, 16
907; RV32IDZFH-NEXT:    addi a1, a1, -1
908; RV32IDZFH-NEXT:    and a0, a0, a1
909; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
910; RV32IDZFH-NEXT:    ret
911;
912; RV64IZFH-LABEL: fcvt_h_ui:
913; RV64IZFH:       # %bb.0:
914; RV64IZFH-NEXT:    lui a1, 16
915; RV64IZFH-NEXT:    addiw a1, a1, -1
916; RV64IZFH-NEXT:    and a0, a0, a1
917; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0
918; RV64IZFH-NEXT:    ret
919;
920; RV64IDZFH-LABEL: fcvt_h_ui:
921; RV64IDZFH:       # %bb.0:
922; RV64IDZFH-NEXT:    lui a1, 16
923; RV64IDZFH-NEXT:    addiw a1, a1, -1
924; RV64IDZFH-NEXT:    and a0, a0, a1
925; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
926; RV64IDZFH-NEXT:    ret
927  %1 = uitofp i16 %a to half
928  ret half %1
929}
930
931define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
932; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
933; RV32IZFH:       # %bb.0:
934; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
935; RV32IZFH-NEXT:    ret
936;
937; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
938; RV32IDZFH:       # %bb.0:
939; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
940; RV32IDZFH-NEXT:    ret
941;
942; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
943; RV64IZFH:       # %bb.0:
944; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
945; RV64IZFH-NEXT:    ret
946;
947; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
948; RV64IDZFH:       # %bb.0:
949; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
950; RV64IDZFH-NEXT:    ret
951  %1 = uitofp i16 %a to half
952  ret half %1
953}
954
955define half @fcvt_h_w(i32 %a) nounwind {
956; RV32IZFH-LABEL: fcvt_h_w:
957; RV32IZFH:       # %bb.0:
958; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
959; RV32IZFH-NEXT:    ret
960;
961; RV32IDZFH-LABEL: fcvt_h_w:
962; RV32IDZFH:       # %bb.0:
963; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
964; RV32IDZFH-NEXT:    ret
965;
966; RV64IZFH-LABEL: fcvt_h_w:
967; RV64IZFH:       # %bb.0:
968; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
969; RV64IZFH-NEXT:    ret
970;
971; RV64IDZFH-LABEL: fcvt_h_w:
972; RV64IDZFH:       # %bb.0:
973; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
974; RV64IDZFH-NEXT:    ret
975  %1 = sitofp i32 %a to half
976  ret half %1
977}
978
979define half @fcvt_h_wu(i32 %a) nounwind {
980; RV32IZFH-LABEL: fcvt_h_wu:
981; RV32IZFH:       # %bb.0:
982; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
983; RV32IZFH-NEXT:    ret
984;
985; RV32IDZFH-LABEL: fcvt_h_wu:
986; RV32IDZFH:       # %bb.0:
987; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
988; RV32IDZFH-NEXT:    ret
989;
990; RV64IZFH-LABEL: fcvt_h_wu:
991; RV64IZFH:       # %bb.0:
992; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
993; RV64IZFH-NEXT:    ret
994;
995; RV64IDZFH-LABEL: fcvt_h_wu:
996; RV64IDZFH:       # %bb.0:
997; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
998; RV64IDZFH-NEXT:    ret
999  %1 = uitofp i32 %a to half
1000  ret half %1
1001}
1002
1003define half @fcvt_h_l(i64 %a) nounwind {
1004; RV32IZFH-LABEL: fcvt_h_l:
1005; RV32IZFH:       # %bb.0:
1006; RV32IZFH-NEXT:    addi sp, sp, -16
1007; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1008; RV32IZFH-NEXT:    call __floatdihf@plt
1009; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1010; RV32IZFH-NEXT:    addi sp, sp, 16
1011; RV32IZFH-NEXT:    ret
1012;
1013; RV32IDZFH-LABEL: fcvt_h_l:
1014; RV32IDZFH:       # %bb.0:
1015; RV32IDZFH-NEXT:    addi sp, sp, -16
1016; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1017; RV32IDZFH-NEXT:    call __floatdihf@plt
1018; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1019; RV32IDZFH-NEXT:    addi sp, sp, 16
1020; RV32IDZFH-NEXT:    ret
1021;
1022; RV64IZFH-LABEL: fcvt_h_l:
1023; RV64IZFH:       # %bb.0:
1024; RV64IZFH-NEXT:    fcvt.h.l fa0, a0
1025; RV64IZFH-NEXT:    ret
1026;
1027; RV64IDZFH-LABEL: fcvt_h_l:
1028; RV64IDZFH:       # %bb.0:
1029; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
1030; RV64IDZFH-NEXT:    ret
1031  %1 = sitofp i64 %a to half
1032  ret half %1
1033}
1034
1035define half @fcvt_h_lu(i64 %a) nounwind {
1036; RV32IZFH-LABEL: fcvt_h_lu:
1037; RV32IZFH:       # %bb.0:
1038; RV32IZFH-NEXT:    addi sp, sp, -16
1039; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1040; RV32IZFH-NEXT:    call __floatundihf@plt
1041; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1042; RV32IZFH-NEXT:    addi sp, sp, 16
1043; RV32IZFH-NEXT:    ret
1044;
1045; RV32IDZFH-LABEL: fcvt_h_lu:
1046; RV32IDZFH:       # %bb.0:
1047; RV32IDZFH-NEXT:    addi sp, sp, -16
1048; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1049; RV32IDZFH-NEXT:    call __floatundihf@plt
1050; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1051; RV32IDZFH-NEXT:    addi sp, sp, 16
1052; RV32IDZFH-NEXT:    ret
1053;
1054; RV64IZFH-LABEL: fcvt_h_lu:
1055; RV64IZFH:       # %bb.0:
1056; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0
1057; RV64IZFH-NEXT:    ret
1058;
1059; RV64IDZFH-LABEL: fcvt_h_lu:
1060; RV64IDZFH:       # %bb.0:
1061; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
1062; RV64IDZFH-NEXT:    ret
1063  %1 = uitofp i64 %a to half
1064  ret half %1
1065}
1066
1067define half @fcvt_h_s(float %a) nounwind {
1068; RV32IZFH-LABEL: fcvt_h_s:
1069; RV32IZFH:       # %bb.0:
1070; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
1071; RV32IZFH-NEXT:    ret
1072;
1073; RV32IDZFH-LABEL: fcvt_h_s:
1074; RV32IDZFH:       # %bb.0:
1075; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
1076; RV32IDZFH-NEXT:    ret
1077;
1078; RV64IZFH-LABEL: fcvt_h_s:
1079; RV64IZFH:       # %bb.0:
1080; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
1081; RV64IZFH-NEXT:    ret
1082;
1083; RV64IDZFH-LABEL: fcvt_h_s:
1084; RV64IDZFH:       # %bb.0:
1085; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0
1086; RV64IDZFH-NEXT:    ret
1087  %1 = fptrunc float %a to half
1088  ret half %1
1089}
1090
1091define float @fcvt_s_h(half %a) nounwind {
1092; RV32IZFH-LABEL: fcvt_s_h:
1093; RV32IZFH:       # %bb.0:
1094; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
1095; RV32IZFH-NEXT:    ret
1096;
1097; RV32IDZFH-LABEL: fcvt_s_h:
1098; RV32IDZFH:       # %bb.0:
1099; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
1100; RV32IDZFH-NEXT:    ret
1101;
1102; RV64IZFH-LABEL: fcvt_s_h:
1103; RV64IZFH:       # %bb.0:
1104; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
1105; RV64IZFH-NEXT:    ret
1106;
1107; RV64IDZFH-LABEL: fcvt_s_h:
1108; RV64IDZFH:       # %bb.0:
1109; RV64IDZFH-NEXT:    fcvt.s.h fa0, fa0
1110; RV64IDZFH-NEXT:    ret
1111  %1 = fpext half %a to float
1112  ret float %1
1113}
1114
1115define half @fcvt_h_d(double %a) nounwind {
1116; RV32IZFH-LABEL: fcvt_h_d:
1117; RV32IZFH:       # %bb.0:
1118; RV32IZFH-NEXT:    addi sp, sp, -16
1119; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1120; RV32IZFH-NEXT:    call __truncdfhf2@plt
1121; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1122; RV32IZFH-NEXT:    addi sp, sp, 16
1123; RV32IZFH-NEXT:    ret
1124;
1125; RV32IDZFH-LABEL: fcvt_h_d:
1126; RV32IDZFH:       # %bb.0:
1127; RV32IDZFH-NEXT:    fcvt.h.d fa0, fa0
1128; RV32IDZFH-NEXT:    ret
1129;
1130; RV64IZFH-LABEL: fcvt_h_d:
1131; RV64IZFH:       # %bb.0:
1132; RV64IZFH-NEXT:    addi sp, sp, -16
1133; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1134; RV64IZFH-NEXT:    call __truncdfhf2@plt
1135; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1136; RV64IZFH-NEXT:    addi sp, sp, 16
1137; RV64IZFH-NEXT:    ret
1138;
1139; RV64IDZFH-LABEL: fcvt_h_d:
1140; RV64IDZFH:       # %bb.0:
1141; RV64IDZFH-NEXT:    fcvt.h.d fa0, fa0
1142; RV64IDZFH-NEXT:    ret
1143  %1 = fptrunc double %a to half
1144  ret half %1
1145}
1146
1147define double @fcvt_d_h(half %a) nounwind {
1148; RV32IZFH-LABEL: fcvt_d_h:
1149; RV32IZFH:       # %bb.0:
1150; RV32IZFH-NEXT:    addi sp, sp, -16
1151; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1152; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
1153; RV32IZFH-NEXT:    call __extendsfdf2@plt
1154; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1155; RV32IZFH-NEXT:    addi sp, sp, 16
1156; RV32IZFH-NEXT:    ret
1157;
1158; RV32IDZFH-LABEL: fcvt_d_h:
1159; RV32IDZFH:       # %bb.0:
1160; RV32IDZFH-NEXT:    fcvt.d.h fa0, fa0
1161; RV32IDZFH-NEXT:    ret
1162;
1163; RV64IZFH-LABEL: fcvt_d_h:
1164; RV64IZFH:       # %bb.0:
1165; RV64IZFH-NEXT:    addi sp, sp, -16
1166; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1167; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
1168; RV64IZFH-NEXT:    call __extendsfdf2@plt
1169; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1170; RV64IZFH-NEXT:    addi sp, sp, 16
1171; RV64IZFH-NEXT:    ret
1172;
1173; RV64IDZFH-LABEL: fcvt_d_h:
1174; RV64IDZFH:       # %bb.0:
1175; RV64IDZFH-NEXT:    fcvt.d.h fa0, fa0
1176; RV64IDZFH-NEXT:    ret
1177  %1 = fpext half %a to double
1178  ret double %1
1179}
1180
1181define half @bitcast_h_i16(i16 %a) nounwind {
1182; RV32IZFH-LABEL: bitcast_h_i16:
1183; RV32IZFH:       # %bb.0:
1184; RV32IZFH-NEXT:    fmv.h.x fa0, a0
1185; RV32IZFH-NEXT:    ret
1186;
1187; RV32IDZFH-LABEL: bitcast_h_i16:
1188; RV32IDZFH:       # %bb.0:
1189; RV32IDZFH-NEXT:    fmv.h.x fa0, a0
1190; RV32IDZFH-NEXT:    ret
1191;
1192; RV64IZFH-LABEL: bitcast_h_i16:
1193; RV64IZFH:       # %bb.0:
1194; RV64IZFH-NEXT:    fmv.h.x fa0, a0
1195; RV64IZFH-NEXT:    ret
1196;
1197; RV64IDZFH-LABEL: bitcast_h_i16:
1198; RV64IDZFH:       # %bb.0:
1199; RV64IDZFH-NEXT:    fmv.h.x fa0, a0
1200; RV64IDZFH-NEXT:    ret
1201  %1 = bitcast i16 %a to half
1202  ret half %1
1203}
1204
1205define i16 @bitcast_i16_h(half %a) nounwind {
1206; RV32IZFH-LABEL: bitcast_i16_h:
1207; RV32IZFH:       # %bb.0:
1208; RV32IZFH-NEXT:    fmv.x.h a0, fa0
1209; RV32IZFH-NEXT:    ret
1210;
1211; RV32IDZFH-LABEL: bitcast_i16_h:
1212; RV32IDZFH:       # %bb.0:
1213; RV32IDZFH-NEXT:    fmv.x.h a0, fa0
1214; RV32IDZFH-NEXT:    ret
1215;
1216; RV64IZFH-LABEL: bitcast_i16_h:
1217; RV64IZFH:       # %bb.0:
1218; RV64IZFH-NEXT:    fmv.x.h a0, fa0
1219; RV64IZFH-NEXT:    ret
1220;
1221; RV64IDZFH-LABEL: bitcast_i16_h:
1222; RV64IDZFH:       # %bb.0:
1223; RV64IDZFH-NEXT:    fmv.x.h a0, fa0
1224; RV64IDZFH-NEXT:    ret
1225  %1 = bitcast half %a to i16
1226  ret i16 %1
1227}
1228