1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
6
7define signext i32 @test_floor_si32(float %x) {
8; RV32IF-LABEL: test_floor_si32:
9; RV32IF:       # %bb.0:
10; RV32IF-NEXT:    feq.s a0, fa0, fa0
11; RV32IF-NEXT:    beqz a0, .LBB0_2
12; RV32IF-NEXT:  # %bb.1:
13; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
14; RV32IF-NEXT:  .LBB0_2:
15; RV32IF-NEXT:    ret
16;
17; RV64IF-LABEL: test_floor_si32:
18; RV64IF:       # %bb.0:
19; RV64IF-NEXT:    feq.s a0, fa0, fa0
20; RV64IF-NEXT:    beqz a0, .LBB0_2
21; RV64IF-NEXT:  # %bb.1:
22; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
23; RV64IF-NEXT:  .LBB0_2:
24; RV64IF-NEXT:    ret
25  %a = call float @llvm.floor.f32(float %x)
26  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
27  ret i32 %b
28}
29
30define i64 @test_floor_si64(float %x) nounwind {
31; RV32IF-LABEL: test_floor_si64:
32; RV32IF:       # %bb.0:
33; RV32IF-NEXT:    addi sp, sp, -16
34; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
35; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
36; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
37; RV32IF-NEXT:    call floorf@plt
38; RV32IF-NEXT:    lui a0, %hi(.LCPI1_0)
39; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
40; RV32IF-NEXT:    fmv.s fs0, fa0
41; RV32IF-NEXT:    fle.s s0, ft0, fa0
42; RV32IF-NEXT:    call __fixsfdi@plt
43; RV32IF-NEXT:    mv a2, a0
44; RV32IF-NEXT:    bnez s0, .LBB1_2
45; RV32IF-NEXT:  # %bb.1:
46; RV32IF-NEXT:    li a2, 0
47; RV32IF-NEXT:  .LBB1_2:
48; RV32IF-NEXT:    lui a0, %hi(.LCPI1_1)
49; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_1)(a0)
50; RV32IF-NEXT:    flt.s a3, ft0, fs0
51; RV32IF-NEXT:    li a0, -1
52; RV32IF-NEXT:    beqz a3, .LBB1_9
53; RV32IF-NEXT:  # %bb.3:
54; RV32IF-NEXT:    feq.s a2, fs0, fs0
55; RV32IF-NEXT:    beqz a2, .LBB1_10
56; RV32IF-NEXT:  .LBB1_4:
57; RV32IF-NEXT:    lui a4, 524288
58; RV32IF-NEXT:    beqz s0, .LBB1_11
59; RV32IF-NEXT:  .LBB1_5:
60; RV32IF-NEXT:    bnez a3, .LBB1_12
61; RV32IF-NEXT:  .LBB1_6:
62; RV32IF-NEXT:    bnez a2, .LBB1_8
63; RV32IF-NEXT:  .LBB1_7:
64; RV32IF-NEXT:    li a1, 0
65; RV32IF-NEXT:  .LBB1_8:
66; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
67; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
68; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
69; RV32IF-NEXT:    addi sp, sp, 16
70; RV32IF-NEXT:    ret
71; RV32IF-NEXT:  .LBB1_9:
72; RV32IF-NEXT:    mv a0, a2
73; RV32IF-NEXT:    feq.s a2, fs0, fs0
74; RV32IF-NEXT:    bnez a2, .LBB1_4
75; RV32IF-NEXT:  .LBB1_10:
76; RV32IF-NEXT:    li a0, 0
77; RV32IF-NEXT:    lui a4, 524288
78; RV32IF-NEXT:    bnez s0, .LBB1_5
79; RV32IF-NEXT:  .LBB1_11:
80; RV32IF-NEXT:    lui a1, 524288
81; RV32IF-NEXT:    beqz a3, .LBB1_6
82; RV32IF-NEXT:  .LBB1_12:
83; RV32IF-NEXT:    addi a1, a4, -1
84; RV32IF-NEXT:    beqz a2, .LBB1_7
85; RV32IF-NEXT:    j .LBB1_8
86;
87; RV64IF-LABEL: test_floor_si64:
88; RV64IF:       # %bb.0:
89; RV64IF-NEXT:    feq.s a0, fa0, fa0
90; RV64IF-NEXT:    beqz a0, .LBB1_2
91; RV64IF-NEXT:  # %bb.1:
92; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
93; RV64IF-NEXT:  .LBB1_2:
94; RV64IF-NEXT:    ret
95  %a = call float @llvm.floor.f32(float %x)
96  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
97  ret i64 %b
98}
99
100define signext i32 @test_floor_ui32(float %x) {
101; RV32IF-LABEL: test_floor_ui32:
102; RV32IF:       # %bb.0:
103; RV32IF-NEXT:    feq.s a0, fa0, fa0
104; RV32IF-NEXT:    beqz a0, .LBB2_2
105; RV32IF-NEXT:  # %bb.1:
106; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
107; RV32IF-NEXT:  .LBB2_2:
108; RV32IF-NEXT:    ret
109;
110; RV64IF-LABEL: test_floor_ui32:
111; RV64IF:       # %bb.0:
112; RV64IF-NEXT:    feq.s a0, fa0, fa0
113; RV64IF-NEXT:    beqz a0, .LBB2_2
114; RV64IF-NEXT:  # %bb.1:
115; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
116; RV64IF-NEXT:  .LBB2_2:
117; RV64IF-NEXT:    ret
118  %a = call float @llvm.floor.f32(float %x)
119  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
120  ret i32 %b
121}
122
123define i64 @test_floor_ui64(float %x) nounwind {
124; RV32IF-LABEL: test_floor_ui64:
125; RV32IF:       # %bb.0:
126; RV32IF-NEXT:    addi sp, sp, -16
127; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
128; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
129; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
130; RV32IF-NEXT:    call floorf@plt
131; RV32IF-NEXT:    fmv.s fs0, fa0
132; RV32IF-NEXT:    fmv.w.x ft0, zero
133; RV32IF-NEXT:    fle.s s0, ft0, fa0
134; RV32IF-NEXT:    call __fixunssfdi@plt
135; RV32IF-NEXT:    mv a3, a0
136; RV32IF-NEXT:    bnez s0, .LBB3_2
137; RV32IF-NEXT:  # %bb.1:
138; RV32IF-NEXT:    li a3, 0
139; RV32IF-NEXT:  .LBB3_2:
140; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
141; RV32IF-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
142; RV32IF-NEXT:    flt.s a4, ft0, fs0
143; RV32IF-NEXT:    li a2, -1
144; RV32IF-NEXT:    li a0, -1
145; RV32IF-NEXT:    beqz a4, .LBB3_7
146; RV32IF-NEXT:  # %bb.3:
147; RV32IF-NEXT:    beqz s0, .LBB3_8
148; RV32IF-NEXT:  .LBB3_4:
149; RV32IF-NEXT:    bnez a4, .LBB3_6
150; RV32IF-NEXT:  .LBB3_5:
151; RV32IF-NEXT:    mv a2, a1
152; RV32IF-NEXT:  .LBB3_6:
153; RV32IF-NEXT:    mv a1, a2
154; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
155; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
156; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
157; RV32IF-NEXT:    addi sp, sp, 16
158; RV32IF-NEXT:    ret
159; RV32IF-NEXT:  .LBB3_7:
160; RV32IF-NEXT:    mv a0, a3
161; RV32IF-NEXT:    bnez s0, .LBB3_4
162; RV32IF-NEXT:  .LBB3_8:
163; RV32IF-NEXT:    li a1, 0
164; RV32IF-NEXT:    beqz a4, .LBB3_5
165; RV32IF-NEXT:    j .LBB3_6
166;
167; RV64IF-LABEL: test_floor_ui64:
168; RV64IF:       # %bb.0:
169; RV64IF-NEXT:    feq.s a0, fa0, fa0
170; RV64IF-NEXT:    beqz a0, .LBB3_2
171; RV64IF-NEXT:  # %bb.1:
172; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
173; RV64IF-NEXT:  .LBB3_2:
174; RV64IF-NEXT:    ret
175  %a = call float @llvm.floor.f32(float %x)
176  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
177  ret i64 %b
178}
179
180define signext i32 @test_ceil_si32(float %x) {
181; RV32IF-LABEL: test_ceil_si32:
182; RV32IF:       # %bb.0:
183; RV32IF-NEXT:    feq.s a0, fa0, fa0
184; RV32IF-NEXT:    beqz a0, .LBB4_2
185; RV32IF-NEXT:  # %bb.1:
186; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
187; RV32IF-NEXT:  .LBB4_2:
188; RV32IF-NEXT:    ret
189;
190; RV64IF-LABEL: test_ceil_si32:
191; RV64IF:       # %bb.0:
192; RV64IF-NEXT:    feq.s a0, fa0, fa0
193; RV64IF-NEXT:    beqz a0, .LBB4_2
194; RV64IF-NEXT:  # %bb.1:
195; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
196; RV64IF-NEXT:  .LBB4_2:
197; RV64IF-NEXT:    ret
198  %a = call float @llvm.ceil.f32(float %x)
199  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
200  ret i32 %b
201}
202
203define i64 @test_ceil_si64(float %x) nounwind {
204; RV32IF-LABEL: test_ceil_si64:
205; RV32IF:       # %bb.0:
206; RV32IF-NEXT:    addi sp, sp, -16
207; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
208; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
209; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
210; RV32IF-NEXT:    call ceilf@plt
211; RV32IF-NEXT:    lui a0, %hi(.LCPI5_0)
212; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_0)(a0)
213; RV32IF-NEXT:    fmv.s fs0, fa0
214; RV32IF-NEXT:    fle.s s0, ft0, fa0
215; RV32IF-NEXT:    call __fixsfdi@plt
216; RV32IF-NEXT:    mv a2, a0
217; RV32IF-NEXT:    bnez s0, .LBB5_2
218; RV32IF-NEXT:  # %bb.1:
219; RV32IF-NEXT:    li a2, 0
220; RV32IF-NEXT:  .LBB5_2:
221; RV32IF-NEXT:    lui a0, %hi(.LCPI5_1)
222; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_1)(a0)
223; RV32IF-NEXT:    flt.s a3, ft0, fs0
224; RV32IF-NEXT:    li a0, -1
225; RV32IF-NEXT:    beqz a3, .LBB5_9
226; RV32IF-NEXT:  # %bb.3:
227; RV32IF-NEXT:    feq.s a2, fs0, fs0
228; RV32IF-NEXT:    beqz a2, .LBB5_10
229; RV32IF-NEXT:  .LBB5_4:
230; RV32IF-NEXT:    lui a4, 524288
231; RV32IF-NEXT:    beqz s0, .LBB5_11
232; RV32IF-NEXT:  .LBB5_5:
233; RV32IF-NEXT:    bnez a3, .LBB5_12
234; RV32IF-NEXT:  .LBB5_6:
235; RV32IF-NEXT:    bnez a2, .LBB5_8
236; RV32IF-NEXT:  .LBB5_7:
237; RV32IF-NEXT:    li a1, 0
238; RV32IF-NEXT:  .LBB5_8:
239; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
240; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
241; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
242; RV32IF-NEXT:    addi sp, sp, 16
243; RV32IF-NEXT:    ret
244; RV32IF-NEXT:  .LBB5_9:
245; RV32IF-NEXT:    mv a0, a2
246; RV32IF-NEXT:    feq.s a2, fs0, fs0
247; RV32IF-NEXT:    bnez a2, .LBB5_4
248; RV32IF-NEXT:  .LBB5_10:
249; RV32IF-NEXT:    li a0, 0
250; RV32IF-NEXT:    lui a4, 524288
251; RV32IF-NEXT:    bnez s0, .LBB5_5
252; RV32IF-NEXT:  .LBB5_11:
253; RV32IF-NEXT:    lui a1, 524288
254; RV32IF-NEXT:    beqz a3, .LBB5_6
255; RV32IF-NEXT:  .LBB5_12:
256; RV32IF-NEXT:    addi a1, a4, -1
257; RV32IF-NEXT:    beqz a2, .LBB5_7
258; RV32IF-NEXT:    j .LBB5_8
259;
260; RV64IF-LABEL: test_ceil_si64:
261; RV64IF:       # %bb.0:
262; RV64IF-NEXT:    feq.s a0, fa0, fa0
263; RV64IF-NEXT:    beqz a0, .LBB5_2
264; RV64IF-NEXT:  # %bb.1:
265; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
266; RV64IF-NEXT:  .LBB5_2:
267; RV64IF-NEXT:    ret
268  %a = call float @llvm.ceil.f32(float %x)
269  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
270  ret i64 %b
271}
272
273define signext i32 @test_ceil_ui32(float %x) {
274; RV32IF-LABEL: test_ceil_ui32:
275; RV32IF:       # %bb.0:
276; RV32IF-NEXT:    feq.s a0, fa0, fa0
277; RV32IF-NEXT:    beqz a0, .LBB6_2
278; RV32IF-NEXT:  # %bb.1:
279; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
280; RV32IF-NEXT:  .LBB6_2:
281; RV32IF-NEXT:    ret
282;
283; RV64IF-LABEL: test_ceil_ui32:
284; RV64IF:       # %bb.0:
285; RV64IF-NEXT:    feq.s a0, fa0, fa0
286; RV64IF-NEXT:    beqz a0, .LBB6_2
287; RV64IF-NEXT:  # %bb.1:
288; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
289; RV64IF-NEXT:  .LBB6_2:
290; RV64IF-NEXT:    ret
291  %a = call float @llvm.ceil.f32(float %x)
292  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
293  ret i32 %b
294}
295
296define i64 @test_ceil_ui64(float %x) nounwind {
297; RV32IF-LABEL: test_ceil_ui64:
298; RV32IF:       # %bb.0:
299; RV32IF-NEXT:    addi sp, sp, -16
300; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
301; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
302; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
303; RV32IF-NEXT:    call ceilf@plt
304; RV32IF-NEXT:    fmv.s fs0, fa0
305; RV32IF-NEXT:    fmv.w.x ft0, zero
306; RV32IF-NEXT:    fle.s s0, ft0, fa0
307; RV32IF-NEXT:    call __fixunssfdi@plt
308; RV32IF-NEXT:    mv a3, a0
309; RV32IF-NEXT:    bnez s0, .LBB7_2
310; RV32IF-NEXT:  # %bb.1:
311; RV32IF-NEXT:    li a3, 0
312; RV32IF-NEXT:  .LBB7_2:
313; RV32IF-NEXT:    lui a0, %hi(.LCPI7_0)
314; RV32IF-NEXT:    flw ft0, %lo(.LCPI7_0)(a0)
315; RV32IF-NEXT:    flt.s a4, ft0, fs0
316; RV32IF-NEXT:    li a2, -1
317; RV32IF-NEXT:    li a0, -1
318; RV32IF-NEXT:    beqz a4, .LBB7_7
319; RV32IF-NEXT:  # %bb.3:
320; RV32IF-NEXT:    beqz s0, .LBB7_8
321; RV32IF-NEXT:  .LBB7_4:
322; RV32IF-NEXT:    bnez a4, .LBB7_6
323; RV32IF-NEXT:  .LBB7_5:
324; RV32IF-NEXT:    mv a2, a1
325; RV32IF-NEXT:  .LBB7_6:
326; RV32IF-NEXT:    mv a1, a2
327; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
328; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
329; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
330; RV32IF-NEXT:    addi sp, sp, 16
331; RV32IF-NEXT:    ret
332; RV32IF-NEXT:  .LBB7_7:
333; RV32IF-NEXT:    mv a0, a3
334; RV32IF-NEXT:    bnez s0, .LBB7_4
335; RV32IF-NEXT:  .LBB7_8:
336; RV32IF-NEXT:    li a1, 0
337; RV32IF-NEXT:    beqz a4, .LBB7_5
338; RV32IF-NEXT:    j .LBB7_6
339;
340; RV64IF-LABEL: test_ceil_ui64:
341; RV64IF:       # %bb.0:
342; RV64IF-NEXT:    feq.s a0, fa0, fa0
343; RV64IF-NEXT:    beqz a0, .LBB7_2
344; RV64IF-NEXT:  # %bb.1:
345; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
346; RV64IF-NEXT:  .LBB7_2:
347; RV64IF-NEXT:    ret
348  %a = call float @llvm.ceil.f32(float %x)
349  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
350  ret i64 %b
351}
352
353define signext i32 @test_trunc_si32(float %x) {
354; RV32IF-LABEL: test_trunc_si32:
355; RV32IF:       # %bb.0:
356; RV32IF-NEXT:    feq.s a0, fa0, fa0
357; RV32IF-NEXT:    beqz a0, .LBB8_2
358; RV32IF-NEXT:  # %bb.1:
359; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
360; RV32IF-NEXT:  .LBB8_2:
361; RV32IF-NEXT:    ret
362;
363; RV64IF-LABEL: test_trunc_si32:
364; RV64IF:       # %bb.0:
365; RV64IF-NEXT:    feq.s a0, fa0, fa0
366; RV64IF-NEXT:    beqz a0, .LBB8_2
367; RV64IF-NEXT:  # %bb.1:
368; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
369; RV64IF-NEXT:  .LBB8_2:
370; RV64IF-NEXT:    ret
371  %a = call float @llvm.trunc.f32(float %x)
372  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
373  ret i32 %b
374}
375
376define i64 @test_trunc_si64(float %x) nounwind {
377; RV32IF-LABEL: test_trunc_si64:
378; RV32IF:       # %bb.0:
379; RV32IF-NEXT:    addi sp, sp, -16
380; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
381; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
382; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
383; RV32IF-NEXT:    call truncf@plt
384; RV32IF-NEXT:    lui a0, %hi(.LCPI9_0)
385; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
386; RV32IF-NEXT:    fmv.s fs0, fa0
387; RV32IF-NEXT:    fle.s s0, ft0, fa0
388; RV32IF-NEXT:    call __fixsfdi@plt
389; RV32IF-NEXT:    mv a2, a0
390; RV32IF-NEXT:    bnez s0, .LBB9_2
391; RV32IF-NEXT:  # %bb.1:
392; RV32IF-NEXT:    li a2, 0
393; RV32IF-NEXT:  .LBB9_2:
394; RV32IF-NEXT:    lui a0, %hi(.LCPI9_1)
395; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
396; RV32IF-NEXT:    flt.s a3, ft0, fs0
397; RV32IF-NEXT:    li a0, -1
398; RV32IF-NEXT:    beqz a3, .LBB9_9
399; RV32IF-NEXT:  # %bb.3:
400; RV32IF-NEXT:    feq.s a2, fs0, fs0
401; RV32IF-NEXT:    beqz a2, .LBB9_10
402; RV32IF-NEXT:  .LBB9_4:
403; RV32IF-NEXT:    lui a4, 524288
404; RV32IF-NEXT:    beqz s0, .LBB9_11
405; RV32IF-NEXT:  .LBB9_5:
406; RV32IF-NEXT:    bnez a3, .LBB9_12
407; RV32IF-NEXT:  .LBB9_6:
408; RV32IF-NEXT:    bnez a2, .LBB9_8
409; RV32IF-NEXT:  .LBB9_7:
410; RV32IF-NEXT:    li a1, 0
411; RV32IF-NEXT:  .LBB9_8:
412; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
413; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
414; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
415; RV32IF-NEXT:    addi sp, sp, 16
416; RV32IF-NEXT:    ret
417; RV32IF-NEXT:  .LBB9_9:
418; RV32IF-NEXT:    mv a0, a2
419; RV32IF-NEXT:    feq.s a2, fs0, fs0
420; RV32IF-NEXT:    bnez a2, .LBB9_4
421; RV32IF-NEXT:  .LBB9_10:
422; RV32IF-NEXT:    li a0, 0
423; RV32IF-NEXT:    lui a4, 524288
424; RV32IF-NEXT:    bnez s0, .LBB9_5
425; RV32IF-NEXT:  .LBB9_11:
426; RV32IF-NEXT:    lui a1, 524288
427; RV32IF-NEXT:    beqz a3, .LBB9_6
428; RV32IF-NEXT:  .LBB9_12:
429; RV32IF-NEXT:    addi a1, a4, -1
430; RV32IF-NEXT:    beqz a2, .LBB9_7
431; RV32IF-NEXT:    j .LBB9_8
432;
433; RV64IF-LABEL: test_trunc_si64:
434; RV64IF:       # %bb.0:
435; RV64IF-NEXT:    feq.s a0, fa0, fa0
436; RV64IF-NEXT:    beqz a0, .LBB9_2
437; RV64IF-NEXT:  # %bb.1:
438; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
439; RV64IF-NEXT:  .LBB9_2:
440; RV64IF-NEXT:    ret
441  %a = call float @llvm.trunc.f32(float %x)
442  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
443  ret i64 %b
444}
445
446define signext i32 @test_trunc_ui32(float %x) {
447; RV32IF-LABEL: test_trunc_ui32:
448; RV32IF:       # %bb.0:
449; RV32IF-NEXT:    feq.s a0, fa0, fa0
450; RV32IF-NEXT:    beqz a0, .LBB10_2
451; RV32IF-NEXT:  # %bb.1:
452; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
453; RV32IF-NEXT:  .LBB10_2:
454; RV32IF-NEXT:    ret
455;
456; RV64IF-LABEL: test_trunc_ui32:
457; RV64IF:       # %bb.0:
458; RV64IF-NEXT:    feq.s a0, fa0, fa0
459; RV64IF-NEXT:    beqz a0, .LBB10_2
460; RV64IF-NEXT:  # %bb.1:
461; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
462; RV64IF-NEXT:  .LBB10_2:
463; RV64IF-NEXT:    ret
464  %a = call float @llvm.trunc.f32(float %x)
465  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
466  ret i32 %b
467}
468
469define i64 @test_trunc_ui64(float %x) nounwind {
470; RV32IF-LABEL: test_trunc_ui64:
471; RV32IF:       # %bb.0:
472; RV32IF-NEXT:    addi sp, sp, -16
473; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
474; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
475; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
476; RV32IF-NEXT:    call truncf@plt
477; RV32IF-NEXT:    fmv.s fs0, fa0
478; RV32IF-NEXT:    fmv.w.x ft0, zero
479; RV32IF-NEXT:    fle.s s0, ft0, fa0
480; RV32IF-NEXT:    call __fixunssfdi@plt
481; RV32IF-NEXT:    mv a3, a0
482; RV32IF-NEXT:    bnez s0, .LBB11_2
483; RV32IF-NEXT:  # %bb.1:
484; RV32IF-NEXT:    li a3, 0
485; RV32IF-NEXT:  .LBB11_2:
486; RV32IF-NEXT:    lui a0, %hi(.LCPI11_0)
487; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
488; RV32IF-NEXT:    flt.s a4, ft0, fs0
489; RV32IF-NEXT:    li a2, -1
490; RV32IF-NEXT:    li a0, -1
491; RV32IF-NEXT:    beqz a4, .LBB11_7
492; RV32IF-NEXT:  # %bb.3:
493; RV32IF-NEXT:    beqz s0, .LBB11_8
494; RV32IF-NEXT:  .LBB11_4:
495; RV32IF-NEXT:    bnez a4, .LBB11_6
496; RV32IF-NEXT:  .LBB11_5:
497; RV32IF-NEXT:    mv a2, a1
498; RV32IF-NEXT:  .LBB11_6:
499; RV32IF-NEXT:    mv a1, a2
500; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
501; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
502; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
503; RV32IF-NEXT:    addi sp, sp, 16
504; RV32IF-NEXT:    ret
505; RV32IF-NEXT:  .LBB11_7:
506; RV32IF-NEXT:    mv a0, a3
507; RV32IF-NEXT:    bnez s0, .LBB11_4
508; RV32IF-NEXT:  .LBB11_8:
509; RV32IF-NEXT:    li a1, 0
510; RV32IF-NEXT:    beqz a4, .LBB11_5
511; RV32IF-NEXT:    j .LBB11_6
512;
513; RV64IF-LABEL: test_trunc_ui64:
514; RV64IF:       # %bb.0:
515; RV64IF-NEXT:    feq.s a0, fa0, fa0
516; RV64IF-NEXT:    beqz a0, .LBB11_2
517; RV64IF-NEXT:  # %bb.1:
518; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
519; RV64IF-NEXT:  .LBB11_2:
520; RV64IF-NEXT:    ret
521  %a = call float @llvm.trunc.f32(float %x)
522  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
523  ret i64 %b
524}
525
526define signext i32 @test_round_si32(float %x) {
527; RV32IF-LABEL: test_round_si32:
528; RV32IF:       # %bb.0:
529; RV32IF-NEXT:    feq.s a0, fa0, fa0
530; RV32IF-NEXT:    beqz a0, .LBB12_2
531; RV32IF-NEXT:  # %bb.1:
532; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
533; RV32IF-NEXT:  .LBB12_2:
534; RV32IF-NEXT:    ret
535;
536; RV64IF-LABEL: test_round_si32:
537; RV64IF:       # %bb.0:
538; RV64IF-NEXT:    feq.s a0, fa0, fa0
539; RV64IF-NEXT:    beqz a0, .LBB12_2
540; RV64IF-NEXT:  # %bb.1:
541; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
542; RV64IF-NEXT:  .LBB12_2:
543; RV64IF-NEXT:    ret
544  %a = call float @llvm.round.f32(float %x)
545  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
546  ret i32 %b
547}
548
549define i64 @test_round_si64(float %x) nounwind {
550; RV32IF-LABEL: test_round_si64:
551; RV32IF:       # %bb.0:
552; RV32IF-NEXT:    addi sp, sp, -16
553; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
554; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
555; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
556; RV32IF-NEXT:    call roundf@plt
557; RV32IF-NEXT:    lui a0, %hi(.LCPI13_0)
558; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_0)(a0)
559; RV32IF-NEXT:    fmv.s fs0, fa0
560; RV32IF-NEXT:    fle.s s0, ft0, fa0
561; RV32IF-NEXT:    call __fixsfdi@plt
562; RV32IF-NEXT:    mv a2, a0
563; RV32IF-NEXT:    bnez s0, .LBB13_2
564; RV32IF-NEXT:  # %bb.1:
565; RV32IF-NEXT:    li a2, 0
566; RV32IF-NEXT:  .LBB13_2:
567; RV32IF-NEXT:    lui a0, %hi(.LCPI13_1)
568; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_1)(a0)
569; RV32IF-NEXT:    flt.s a3, ft0, fs0
570; RV32IF-NEXT:    li a0, -1
571; RV32IF-NEXT:    beqz a3, .LBB13_9
572; RV32IF-NEXT:  # %bb.3:
573; RV32IF-NEXT:    feq.s a2, fs0, fs0
574; RV32IF-NEXT:    beqz a2, .LBB13_10
575; RV32IF-NEXT:  .LBB13_4:
576; RV32IF-NEXT:    lui a4, 524288
577; RV32IF-NEXT:    beqz s0, .LBB13_11
578; RV32IF-NEXT:  .LBB13_5:
579; RV32IF-NEXT:    bnez a3, .LBB13_12
580; RV32IF-NEXT:  .LBB13_6:
581; RV32IF-NEXT:    bnez a2, .LBB13_8
582; RV32IF-NEXT:  .LBB13_7:
583; RV32IF-NEXT:    li a1, 0
584; RV32IF-NEXT:  .LBB13_8:
585; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
586; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
587; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
588; RV32IF-NEXT:    addi sp, sp, 16
589; RV32IF-NEXT:    ret
590; RV32IF-NEXT:  .LBB13_9:
591; RV32IF-NEXT:    mv a0, a2
592; RV32IF-NEXT:    feq.s a2, fs0, fs0
593; RV32IF-NEXT:    bnez a2, .LBB13_4
594; RV32IF-NEXT:  .LBB13_10:
595; RV32IF-NEXT:    li a0, 0
596; RV32IF-NEXT:    lui a4, 524288
597; RV32IF-NEXT:    bnez s0, .LBB13_5
598; RV32IF-NEXT:  .LBB13_11:
599; RV32IF-NEXT:    lui a1, 524288
600; RV32IF-NEXT:    beqz a3, .LBB13_6
601; RV32IF-NEXT:  .LBB13_12:
602; RV32IF-NEXT:    addi a1, a4, -1
603; RV32IF-NEXT:    beqz a2, .LBB13_7
604; RV32IF-NEXT:    j .LBB13_8
605;
606; RV64IF-LABEL: test_round_si64:
607; RV64IF:       # %bb.0:
608; RV64IF-NEXT:    feq.s a0, fa0, fa0
609; RV64IF-NEXT:    beqz a0, .LBB13_2
610; RV64IF-NEXT:  # %bb.1:
611; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
612; RV64IF-NEXT:  .LBB13_2:
613; RV64IF-NEXT:    ret
614  %a = call float @llvm.round.f32(float %x)
615  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
616  ret i64 %b
617}
618
619define signext i32 @test_round_ui32(float %x) {
620; RV32IF-LABEL: test_round_ui32:
621; RV32IF:       # %bb.0:
622; RV32IF-NEXT:    feq.s a0, fa0, fa0
623; RV32IF-NEXT:    beqz a0, .LBB14_2
624; RV32IF-NEXT:  # %bb.1:
625; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
626; RV32IF-NEXT:  .LBB14_2:
627; RV32IF-NEXT:    ret
628;
629; RV64IF-LABEL: test_round_ui32:
630; RV64IF:       # %bb.0:
631; RV64IF-NEXT:    feq.s a0, fa0, fa0
632; RV64IF-NEXT:    beqz a0, .LBB14_2
633; RV64IF-NEXT:  # %bb.1:
634; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
635; RV64IF-NEXT:  .LBB14_2:
636; RV64IF-NEXT:    ret
637  %a = call float @llvm.round.f32(float %x)
638  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
639  ret i32 %b
640}
641
642define i64 @test_round_ui64(float %x) nounwind {
643; RV32IF-LABEL: test_round_ui64:
644; RV32IF:       # %bb.0:
645; RV32IF-NEXT:    addi sp, sp, -16
646; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
647; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
648; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
649; RV32IF-NEXT:    call roundf@plt
650; RV32IF-NEXT:    fmv.s fs0, fa0
651; RV32IF-NEXT:    fmv.w.x ft0, zero
652; RV32IF-NEXT:    fle.s s0, ft0, fa0
653; RV32IF-NEXT:    call __fixunssfdi@plt
654; RV32IF-NEXT:    mv a3, a0
655; RV32IF-NEXT:    bnez s0, .LBB15_2
656; RV32IF-NEXT:  # %bb.1:
657; RV32IF-NEXT:    li a3, 0
658; RV32IF-NEXT:  .LBB15_2:
659; RV32IF-NEXT:    lui a0, %hi(.LCPI15_0)
660; RV32IF-NEXT:    flw ft0, %lo(.LCPI15_0)(a0)
661; RV32IF-NEXT:    flt.s a4, ft0, fs0
662; RV32IF-NEXT:    li a2, -1
663; RV32IF-NEXT:    li a0, -1
664; RV32IF-NEXT:    beqz a4, .LBB15_7
665; RV32IF-NEXT:  # %bb.3:
666; RV32IF-NEXT:    beqz s0, .LBB15_8
667; RV32IF-NEXT:  .LBB15_4:
668; RV32IF-NEXT:    bnez a4, .LBB15_6
669; RV32IF-NEXT:  .LBB15_5:
670; RV32IF-NEXT:    mv a2, a1
671; RV32IF-NEXT:  .LBB15_6:
672; RV32IF-NEXT:    mv a1, a2
673; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
674; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
675; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
676; RV32IF-NEXT:    addi sp, sp, 16
677; RV32IF-NEXT:    ret
678; RV32IF-NEXT:  .LBB15_7:
679; RV32IF-NEXT:    mv a0, a3
680; RV32IF-NEXT:    bnez s0, .LBB15_4
681; RV32IF-NEXT:  .LBB15_8:
682; RV32IF-NEXT:    li a1, 0
683; RV32IF-NEXT:    beqz a4, .LBB15_5
684; RV32IF-NEXT:    j .LBB15_6
685;
686; RV64IF-LABEL: test_round_ui64:
687; RV64IF:       # %bb.0:
688; RV64IF-NEXT:    feq.s a0, fa0, fa0
689; RV64IF-NEXT:    beqz a0, .LBB15_2
690; RV64IF-NEXT:  # %bb.1:
691; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
692; RV64IF-NEXT:  .LBB15_2:
693; RV64IF-NEXT:    ret
694  %a = call float @llvm.round.f32(float %x)
695  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
696  ret i64 %b
697}
698
699define signext i32 @test_roundeven_si32(float %x) {
700; RV32IF-LABEL: test_roundeven_si32:
701; RV32IF:       # %bb.0:
702; RV32IF-NEXT:    feq.s a0, fa0, fa0
703; RV32IF-NEXT:    beqz a0, .LBB16_2
704; RV32IF-NEXT:  # %bb.1:
705; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
706; RV32IF-NEXT:  .LBB16_2:
707; RV32IF-NEXT:    ret
708;
709; RV64IF-LABEL: test_roundeven_si32:
710; RV64IF:       # %bb.0:
711; RV64IF-NEXT:    feq.s a0, fa0, fa0
712; RV64IF-NEXT:    beqz a0, .LBB16_2
713; RV64IF-NEXT:  # %bb.1:
714; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
715; RV64IF-NEXT:  .LBB16_2:
716; RV64IF-NEXT:    ret
717  %a = call float @llvm.roundeven.f32(float %x)
718  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
719  ret i32 %b
720}
721
722define i64 @test_roundeven_si64(float %x) nounwind {
723; RV32IF-LABEL: test_roundeven_si64:
724; RV32IF:       # %bb.0:
725; RV32IF-NEXT:    addi sp, sp, -16
726; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
727; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
728; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
729; RV32IF-NEXT:    call roundevenf@plt
730; RV32IF-NEXT:    lui a0, %hi(.LCPI17_0)
731; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_0)(a0)
732; RV32IF-NEXT:    fmv.s fs0, fa0
733; RV32IF-NEXT:    fle.s s0, ft0, fa0
734; RV32IF-NEXT:    call __fixsfdi@plt
735; RV32IF-NEXT:    mv a2, a0
736; RV32IF-NEXT:    bnez s0, .LBB17_2
737; RV32IF-NEXT:  # %bb.1:
738; RV32IF-NEXT:    li a2, 0
739; RV32IF-NEXT:  .LBB17_2:
740; RV32IF-NEXT:    lui a0, %hi(.LCPI17_1)
741; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_1)(a0)
742; RV32IF-NEXT:    flt.s a3, ft0, fs0
743; RV32IF-NEXT:    li a0, -1
744; RV32IF-NEXT:    beqz a3, .LBB17_9
745; RV32IF-NEXT:  # %bb.3:
746; RV32IF-NEXT:    feq.s a2, fs0, fs0
747; RV32IF-NEXT:    beqz a2, .LBB17_10
748; RV32IF-NEXT:  .LBB17_4:
749; RV32IF-NEXT:    lui a4, 524288
750; RV32IF-NEXT:    beqz s0, .LBB17_11
751; RV32IF-NEXT:  .LBB17_5:
752; RV32IF-NEXT:    bnez a3, .LBB17_12
753; RV32IF-NEXT:  .LBB17_6:
754; RV32IF-NEXT:    bnez a2, .LBB17_8
755; RV32IF-NEXT:  .LBB17_7:
756; RV32IF-NEXT:    li a1, 0
757; RV32IF-NEXT:  .LBB17_8:
758; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
759; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
760; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
761; RV32IF-NEXT:    addi sp, sp, 16
762; RV32IF-NEXT:    ret
763; RV32IF-NEXT:  .LBB17_9:
764; RV32IF-NEXT:    mv a0, a2
765; RV32IF-NEXT:    feq.s a2, fs0, fs0
766; RV32IF-NEXT:    bnez a2, .LBB17_4
767; RV32IF-NEXT:  .LBB17_10:
768; RV32IF-NEXT:    li a0, 0
769; RV32IF-NEXT:    lui a4, 524288
770; RV32IF-NEXT:    bnez s0, .LBB17_5
771; RV32IF-NEXT:  .LBB17_11:
772; RV32IF-NEXT:    lui a1, 524288
773; RV32IF-NEXT:    beqz a3, .LBB17_6
774; RV32IF-NEXT:  .LBB17_12:
775; RV32IF-NEXT:    addi a1, a4, -1
776; RV32IF-NEXT:    beqz a2, .LBB17_7
777; RV32IF-NEXT:    j .LBB17_8
778;
779; RV64IF-LABEL: test_roundeven_si64:
780; RV64IF:       # %bb.0:
781; RV64IF-NEXT:    feq.s a0, fa0, fa0
782; RV64IF-NEXT:    beqz a0, .LBB17_2
783; RV64IF-NEXT:  # %bb.1:
784; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
785; RV64IF-NEXT:  .LBB17_2:
786; RV64IF-NEXT:    ret
787  %a = call float @llvm.roundeven.f32(float %x)
788  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
789  ret i64 %b
790}
791
792define signext i32 @test_roundeven_ui32(float %x) {
793; RV32IF-LABEL: test_roundeven_ui32:
794; RV32IF:       # %bb.0:
795; RV32IF-NEXT:    feq.s a0, fa0, fa0
796; RV32IF-NEXT:    beqz a0, .LBB18_2
797; RV32IF-NEXT:  # %bb.1:
798; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
799; RV32IF-NEXT:  .LBB18_2:
800; RV32IF-NEXT:    ret
801;
802; RV64IF-LABEL: test_roundeven_ui32:
803; RV64IF:       # %bb.0:
804; RV64IF-NEXT:    feq.s a0, fa0, fa0
805; RV64IF-NEXT:    beqz a0, .LBB18_2
806; RV64IF-NEXT:  # %bb.1:
807; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
808; RV64IF-NEXT:  .LBB18_2:
809; RV64IF-NEXT:    ret
810  %a = call float @llvm.roundeven.f32(float %x)
811  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
812  ret i32 %b
813}
814
815define i64 @test_roundeven_ui64(float %x) nounwind {
816; RV32IF-LABEL: test_roundeven_ui64:
817; RV32IF:       # %bb.0:
818; RV32IF-NEXT:    addi sp, sp, -16
819; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
820; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
821; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
822; RV32IF-NEXT:    call roundevenf@plt
823; RV32IF-NEXT:    fmv.s fs0, fa0
824; RV32IF-NEXT:    fmv.w.x ft0, zero
825; RV32IF-NEXT:    fle.s s0, ft0, fa0
826; RV32IF-NEXT:    call __fixunssfdi@plt
827; RV32IF-NEXT:    mv a3, a0
828; RV32IF-NEXT:    bnez s0, .LBB19_2
829; RV32IF-NEXT:  # %bb.1:
830; RV32IF-NEXT:    li a3, 0
831; RV32IF-NEXT:  .LBB19_2:
832; RV32IF-NEXT:    lui a0, %hi(.LCPI19_0)
833; RV32IF-NEXT:    flw ft0, %lo(.LCPI19_0)(a0)
834; RV32IF-NEXT:    flt.s a4, ft0, fs0
835; RV32IF-NEXT:    li a2, -1
836; RV32IF-NEXT:    li a0, -1
837; RV32IF-NEXT:    beqz a4, .LBB19_7
838; RV32IF-NEXT:  # %bb.3:
839; RV32IF-NEXT:    beqz s0, .LBB19_8
840; RV32IF-NEXT:  .LBB19_4:
841; RV32IF-NEXT:    bnez a4, .LBB19_6
842; RV32IF-NEXT:  .LBB19_5:
843; RV32IF-NEXT:    mv a2, a1
844; RV32IF-NEXT:  .LBB19_6:
845; RV32IF-NEXT:    mv a1, a2
846; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
847; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
848; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
849; RV32IF-NEXT:    addi sp, sp, 16
850; RV32IF-NEXT:    ret
851; RV32IF-NEXT:  .LBB19_7:
852; RV32IF-NEXT:    mv a0, a3
853; RV32IF-NEXT:    bnez s0, .LBB19_4
854; RV32IF-NEXT:  .LBB19_8:
855; RV32IF-NEXT:    li a1, 0
856; RV32IF-NEXT:    beqz a4, .LBB19_5
857; RV32IF-NEXT:    j .LBB19_6
858;
859; RV64IF-LABEL: test_roundeven_ui64:
860; RV64IF:       # %bb.0:
861; RV64IF-NEXT:    feq.s a0, fa0, fa0
862; RV64IF-NEXT:    beqz a0, .LBB19_2
863; RV64IF-NEXT:  # %bb.1:
864; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
865; RV64IF-NEXT:  .LBB19_2:
866; RV64IF-NEXT:    ret
867  %a = call float @llvm.roundeven.f32(float %x)
868  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
869  ret i64 %b
870}
871
872declare float @llvm.floor.f32(float)
873declare float @llvm.ceil.f32(float)
874declare float @llvm.trunc.f32(float)
875declare float @llvm.round.f32(float)
876declare float @llvm.roundeven.f32(float)
877declare i32 @llvm.fptosi.sat.i32.f32(float)
878declare i64 @llvm.fptosi.sat.i64.f32(float)
879declare i32 @llvm.fptoui.sat.i32.f32(float)
880declare i64 @llvm.fptoui.sat.i64.f32(float)
881