1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
6
7define signext i32 @test_floor_si32(float %x) {
8; CHECKIF-LABEL: test_floor_si32:
9; CHECKIF:       # %bb.0:
10; CHECKIF-NEXT:    feq.s a0, fa0, fa0
11; CHECKIF-NEXT:    beqz a0, .LBB0_2
12; CHECKIF-NEXT:  # %bb.1:
13; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rdn
14; CHECKIF-NEXT:  .LBB0_2:
15; CHECKIF-NEXT:    ret
16  %a = call float @llvm.floor.f32(float %x)
17  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
18  ret i32 %b
19}
20
21define i64 @test_floor_si64(float %x) nounwind {
22; RV32IF-LABEL: test_floor_si64:
23; RV32IF:       # %bb.0:
24; RV32IF-NEXT:    addi sp, sp, -16
25; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
26; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
27; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
28; RV32IF-NEXT:    call floorf@plt
29; RV32IF-NEXT:    lui a0, %hi(.LCPI1_0)
30; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
31; RV32IF-NEXT:    fmv.s fs0, fa0
32; RV32IF-NEXT:    fle.s s0, ft0, fa0
33; RV32IF-NEXT:    call __fixsfdi@plt
34; RV32IF-NEXT:    mv a2, a0
35; RV32IF-NEXT:    bnez s0, .LBB1_2
36; RV32IF-NEXT:  # %bb.1:
37; RV32IF-NEXT:    li a2, 0
38; RV32IF-NEXT:  .LBB1_2:
39; RV32IF-NEXT:    lui a0, %hi(.LCPI1_1)
40; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_1)(a0)
41; RV32IF-NEXT:    flt.s a3, ft0, fs0
42; RV32IF-NEXT:    li a0, -1
43; RV32IF-NEXT:    beqz a3, .LBB1_9
44; RV32IF-NEXT:  # %bb.3:
45; RV32IF-NEXT:    feq.s a2, fs0, fs0
46; RV32IF-NEXT:    beqz a2, .LBB1_10
47; RV32IF-NEXT:  .LBB1_4:
48; RV32IF-NEXT:    lui a4, 524288
49; RV32IF-NEXT:    beqz s0, .LBB1_11
50; RV32IF-NEXT:  .LBB1_5:
51; RV32IF-NEXT:    bnez a3, .LBB1_12
52; RV32IF-NEXT:  .LBB1_6:
53; RV32IF-NEXT:    bnez a2, .LBB1_8
54; RV32IF-NEXT:  .LBB1_7:
55; RV32IF-NEXT:    li a1, 0
56; RV32IF-NEXT:  .LBB1_8:
57; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
58; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
59; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
60; RV32IF-NEXT:    addi sp, sp, 16
61; RV32IF-NEXT:    ret
62; RV32IF-NEXT:  .LBB1_9:
63; RV32IF-NEXT:    mv a0, a2
64; RV32IF-NEXT:    feq.s a2, fs0, fs0
65; RV32IF-NEXT:    bnez a2, .LBB1_4
66; RV32IF-NEXT:  .LBB1_10:
67; RV32IF-NEXT:    li a0, 0
68; RV32IF-NEXT:    lui a4, 524288
69; RV32IF-NEXT:    bnez s0, .LBB1_5
70; RV32IF-NEXT:  .LBB1_11:
71; RV32IF-NEXT:    lui a1, 524288
72; RV32IF-NEXT:    beqz a3, .LBB1_6
73; RV32IF-NEXT:  .LBB1_12:
74; RV32IF-NEXT:    addi a1, a4, -1
75; RV32IF-NEXT:    beqz a2, .LBB1_7
76; RV32IF-NEXT:    j .LBB1_8
77;
78; RV64IF-LABEL: test_floor_si64:
79; RV64IF:       # %bb.0:
80; RV64IF-NEXT:    feq.s a0, fa0, fa0
81; RV64IF-NEXT:    beqz a0, .LBB1_2
82; RV64IF-NEXT:  # %bb.1:
83; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
84; RV64IF-NEXT:  .LBB1_2:
85; RV64IF-NEXT:    ret
86  %a = call float @llvm.floor.f32(float %x)
87  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
88  ret i64 %b
89}
90
91define signext i32 @test_floor_ui32(float %x) {
92; CHECKIF-LABEL: test_floor_ui32:
93; CHECKIF:       # %bb.0:
94; CHECKIF-NEXT:    feq.s a0, fa0, fa0
95; CHECKIF-NEXT:    beqz a0, .LBB2_2
96; CHECKIF-NEXT:  # %bb.1:
97; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rdn
98; CHECKIF-NEXT:  .LBB2_2:
99; CHECKIF-NEXT:    ret
100  %a = call float @llvm.floor.f32(float %x)
101  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
102  ret i32 %b
103}
104
105define i64 @test_floor_ui64(float %x) nounwind {
106; RV32IF-LABEL: test_floor_ui64:
107; RV32IF:       # %bb.0:
108; RV32IF-NEXT:    addi sp, sp, -16
109; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
110; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
111; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
112; RV32IF-NEXT:    call floorf@plt
113; RV32IF-NEXT:    fmv.s fs0, fa0
114; RV32IF-NEXT:    fmv.w.x ft0, zero
115; RV32IF-NEXT:    fle.s s0, ft0, fa0
116; RV32IF-NEXT:    call __fixunssfdi@plt
117; RV32IF-NEXT:    mv a3, a0
118; RV32IF-NEXT:    bnez s0, .LBB3_2
119; RV32IF-NEXT:  # %bb.1:
120; RV32IF-NEXT:    li a3, 0
121; RV32IF-NEXT:  .LBB3_2:
122; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
123; RV32IF-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
124; RV32IF-NEXT:    flt.s a4, ft0, fs0
125; RV32IF-NEXT:    li a2, -1
126; RV32IF-NEXT:    li a0, -1
127; RV32IF-NEXT:    beqz a4, .LBB3_7
128; RV32IF-NEXT:  # %bb.3:
129; RV32IF-NEXT:    beqz s0, .LBB3_8
130; RV32IF-NEXT:  .LBB3_4:
131; RV32IF-NEXT:    bnez a4, .LBB3_6
132; RV32IF-NEXT:  .LBB3_5:
133; RV32IF-NEXT:    mv a2, a1
134; RV32IF-NEXT:  .LBB3_6:
135; RV32IF-NEXT:    mv a1, a2
136; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
137; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
138; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
139; RV32IF-NEXT:    addi sp, sp, 16
140; RV32IF-NEXT:    ret
141; RV32IF-NEXT:  .LBB3_7:
142; RV32IF-NEXT:    mv a0, a3
143; RV32IF-NEXT:    bnez s0, .LBB3_4
144; RV32IF-NEXT:  .LBB3_8:
145; RV32IF-NEXT:    li a1, 0
146; RV32IF-NEXT:    beqz a4, .LBB3_5
147; RV32IF-NEXT:    j .LBB3_6
148;
149; RV64IF-LABEL: test_floor_ui64:
150; RV64IF:       # %bb.0:
151; RV64IF-NEXT:    feq.s a0, fa0, fa0
152; RV64IF-NEXT:    beqz a0, .LBB3_2
153; RV64IF-NEXT:  # %bb.1:
154; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
155; RV64IF-NEXT:  .LBB3_2:
156; RV64IF-NEXT:    ret
157  %a = call float @llvm.floor.f32(float %x)
158  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
159  ret i64 %b
160}
161
162define signext i32 @test_ceil_si32(float %x) {
163; CHECKIF-LABEL: test_ceil_si32:
164; CHECKIF:       # %bb.0:
165; CHECKIF-NEXT:    feq.s a0, fa0, fa0
166; CHECKIF-NEXT:    beqz a0, .LBB4_2
167; CHECKIF-NEXT:  # %bb.1:
168; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rup
169; CHECKIF-NEXT:  .LBB4_2:
170; CHECKIF-NEXT:    ret
171  %a = call float @llvm.ceil.f32(float %x)
172  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
173  ret i32 %b
174}
175
176define i64 @test_ceil_si64(float %x) nounwind {
177; RV32IF-LABEL: test_ceil_si64:
178; RV32IF:       # %bb.0:
179; RV32IF-NEXT:    addi sp, sp, -16
180; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
181; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
182; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
183; RV32IF-NEXT:    call ceilf@plt
184; RV32IF-NEXT:    lui a0, %hi(.LCPI5_0)
185; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_0)(a0)
186; RV32IF-NEXT:    fmv.s fs0, fa0
187; RV32IF-NEXT:    fle.s s0, ft0, fa0
188; RV32IF-NEXT:    call __fixsfdi@plt
189; RV32IF-NEXT:    mv a2, a0
190; RV32IF-NEXT:    bnez s0, .LBB5_2
191; RV32IF-NEXT:  # %bb.1:
192; RV32IF-NEXT:    li a2, 0
193; RV32IF-NEXT:  .LBB5_2:
194; RV32IF-NEXT:    lui a0, %hi(.LCPI5_1)
195; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_1)(a0)
196; RV32IF-NEXT:    flt.s a3, ft0, fs0
197; RV32IF-NEXT:    li a0, -1
198; RV32IF-NEXT:    beqz a3, .LBB5_9
199; RV32IF-NEXT:  # %bb.3:
200; RV32IF-NEXT:    feq.s a2, fs0, fs0
201; RV32IF-NEXT:    beqz a2, .LBB5_10
202; RV32IF-NEXT:  .LBB5_4:
203; RV32IF-NEXT:    lui a4, 524288
204; RV32IF-NEXT:    beqz s0, .LBB5_11
205; RV32IF-NEXT:  .LBB5_5:
206; RV32IF-NEXT:    bnez a3, .LBB5_12
207; RV32IF-NEXT:  .LBB5_6:
208; RV32IF-NEXT:    bnez a2, .LBB5_8
209; RV32IF-NEXT:  .LBB5_7:
210; RV32IF-NEXT:    li a1, 0
211; RV32IF-NEXT:  .LBB5_8:
212; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
213; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
214; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
215; RV32IF-NEXT:    addi sp, sp, 16
216; RV32IF-NEXT:    ret
217; RV32IF-NEXT:  .LBB5_9:
218; RV32IF-NEXT:    mv a0, a2
219; RV32IF-NEXT:    feq.s a2, fs0, fs0
220; RV32IF-NEXT:    bnez a2, .LBB5_4
221; RV32IF-NEXT:  .LBB5_10:
222; RV32IF-NEXT:    li a0, 0
223; RV32IF-NEXT:    lui a4, 524288
224; RV32IF-NEXT:    bnez s0, .LBB5_5
225; RV32IF-NEXT:  .LBB5_11:
226; RV32IF-NEXT:    lui a1, 524288
227; RV32IF-NEXT:    beqz a3, .LBB5_6
228; RV32IF-NEXT:  .LBB5_12:
229; RV32IF-NEXT:    addi a1, a4, -1
230; RV32IF-NEXT:    beqz a2, .LBB5_7
231; RV32IF-NEXT:    j .LBB5_8
232;
233; RV64IF-LABEL: test_ceil_si64:
234; RV64IF:       # %bb.0:
235; RV64IF-NEXT:    feq.s a0, fa0, fa0
236; RV64IF-NEXT:    beqz a0, .LBB5_2
237; RV64IF-NEXT:  # %bb.1:
238; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
239; RV64IF-NEXT:  .LBB5_2:
240; RV64IF-NEXT:    ret
241  %a = call float @llvm.ceil.f32(float %x)
242  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
243  ret i64 %b
244}
245
246define signext i32 @test_ceil_ui32(float %x) {
247; CHECKIF-LABEL: test_ceil_ui32:
248; CHECKIF:       # %bb.0:
249; CHECKIF-NEXT:    feq.s a0, fa0, fa0
250; CHECKIF-NEXT:    beqz a0, .LBB6_2
251; CHECKIF-NEXT:  # %bb.1:
252; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rup
253; CHECKIF-NEXT:  .LBB6_2:
254; CHECKIF-NEXT:    ret
255  %a = call float @llvm.ceil.f32(float %x)
256  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
257  ret i32 %b
258}
259
260define i64 @test_ceil_ui64(float %x) nounwind {
261; RV32IF-LABEL: test_ceil_ui64:
262; RV32IF:       # %bb.0:
263; RV32IF-NEXT:    addi sp, sp, -16
264; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
265; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
266; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
267; RV32IF-NEXT:    call ceilf@plt
268; RV32IF-NEXT:    fmv.s fs0, fa0
269; RV32IF-NEXT:    fmv.w.x ft0, zero
270; RV32IF-NEXT:    fle.s s0, ft0, fa0
271; RV32IF-NEXT:    call __fixunssfdi@plt
272; RV32IF-NEXT:    mv a3, a0
273; RV32IF-NEXT:    bnez s0, .LBB7_2
274; RV32IF-NEXT:  # %bb.1:
275; RV32IF-NEXT:    li a3, 0
276; RV32IF-NEXT:  .LBB7_2:
277; RV32IF-NEXT:    lui a0, %hi(.LCPI7_0)
278; RV32IF-NEXT:    flw ft0, %lo(.LCPI7_0)(a0)
279; RV32IF-NEXT:    flt.s a4, ft0, fs0
280; RV32IF-NEXT:    li a2, -1
281; RV32IF-NEXT:    li a0, -1
282; RV32IF-NEXT:    beqz a4, .LBB7_7
283; RV32IF-NEXT:  # %bb.3:
284; RV32IF-NEXT:    beqz s0, .LBB7_8
285; RV32IF-NEXT:  .LBB7_4:
286; RV32IF-NEXT:    bnez a4, .LBB7_6
287; RV32IF-NEXT:  .LBB7_5:
288; RV32IF-NEXT:    mv a2, a1
289; RV32IF-NEXT:  .LBB7_6:
290; RV32IF-NEXT:    mv a1, a2
291; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
292; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
293; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
294; RV32IF-NEXT:    addi sp, sp, 16
295; RV32IF-NEXT:    ret
296; RV32IF-NEXT:  .LBB7_7:
297; RV32IF-NEXT:    mv a0, a3
298; RV32IF-NEXT:    bnez s0, .LBB7_4
299; RV32IF-NEXT:  .LBB7_8:
300; RV32IF-NEXT:    li a1, 0
301; RV32IF-NEXT:    beqz a4, .LBB7_5
302; RV32IF-NEXT:    j .LBB7_6
303;
304; RV64IF-LABEL: test_ceil_ui64:
305; RV64IF:       # %bb.0:
306; RV64IF-NEXT:    feq.s a0, fa0, fa0
307; RV64IF-NEXT:    beqz a0, .LBB7_2
308; RV64IF-NEXT:  # %bb.1:
309; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
310; RV64IF-NEXT:  .LBB7_2:
311; RV64IF-NEXT:    ret
312  %a = call float @llvm.ceil.f32(float %x)
313  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
314  ret i64 %b
315}
316
317define signext i32 @test_trunc_si32(float %x) {
318; CHECKIF-LABEL: test_trunc_si32:
319; CHECKIF:       # %bb.0:
320; CHECKIF-NEXT:    feq.s a0, fa0, fa0
321; CHECKIF-NEXT:    beqz a0, .LBB8_2
322; CHECKIF-NEXT:  # %bb.1:
323; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rtz
324; CHECKIF-NEXT:  .LBB8_2:
325; CHECKIF-NEXT:    ret
326  %a = call float @llvm.trunc.f32(float %x)
327  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
328  ret i32 %b
329}
330
331define i64 @test_trunc_si64(float %x) nounwind {
332; RV32IF-LABEL: test_trunc_si64:
333; RV32IF:       # %bb.0:
334; RV32IF-NEXT:    addi sp, sp, -16
335; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
336; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
337; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
338; RV32IF-NEXT:    call truncf@plt
339; RV32IF-NEXT:    lui a0, %hi(.LCPI9_0)
340; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
341; RV32IF-NEXT:    fmv.s fs0, fa0
342; RV32IF-NEXT:    fle.s s0, ft0, fa0
343; RV32IF-NEXT:    call __fixsfdi@plt
344; RV32IF-NEXT:    mv a2, a0
345; RV32IF-NEXT:    bnez s0, .LBB9_2
346; RV32IF-NEXT:  # %bb.1:
347; RV32IF-NEXT:    li a2, 0
348; RV32IF-NEXT:  .LBB9_2:
349; RV32IF-NEXT:    lui a0, %hi(.LCPI9_1)
350; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
351; RV32IF-NEXT:    flt.s a3, ft0, fs0
352; RV32IF-NEXT:    li a0, -1
353; RV32IF-NEXT:    beqz a3, .LBB9_9
354; RV32IF-NEXT:  # %bb.3:
355; RV32IF-NEXT:    feq.s a2, fs0, fs0
356; RV32IF-NEXT:    beqz a2, .LBB9_10
357; RV32IF-NEXT:  .LBB9_4:
358; RV32IF-NEXT:    lui a4, 524288
359; RV32IF-NEXT:    beqz s0, .LBB9_11
360; RV32IF-NEXT:  .LBB9_5:
361; RV32IF-NEXT:    bnez a3, .LBB9_12
362; RV32IF-NEXT:  .LBB9_6:
363; RV32IF-NEXT:    bnez a2, .LBB9_8
364; RV32IF-NEXT:  .LBB9_7:
365; RV32IF-NEXT:    li a1, 0
366; RV32IF-NEXT:  .LBB9_8:
367; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
368; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
369; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
370; RV32IF-NEXT:    addi sp, sp, 16
371; RV32IF-NEXT:    ret
372; RV32IF-NEXT:  .LBB9_9:
373; RV32IF-NEXT:    mv a0, a2
374; RV32IF-NEXT:    feq.s a2, fs0, fs0
375; RV32IF-NEXT:    bnez a2, .LBB9_4
376; RV32IF-NEXT:  .LBB9_10:
377; RV32IF-NEXT:    li a0, 0
378; RV32IF-NEXT:    lui a4, 524288
379; RV32IF-NEXT:    bnez s0, .LBB9_5
380; RV32IF-NEXT:  .LBB9_11:
381; RV32IF-NEXT:    lui a1, 524288
382; RV32IF-NEXT:    beqz a3, .LBB9_6
383; RV32IF-NEXT:  .LBB9_12:
384; RV32IF-NEXT:    addi a1, a4, -1
385; RV32IF-NEXT:    beqz a2, .LBB9_7
386; RV32IF-NEXT:    j .LBB9_8
387;
388; RV64IF-LABEL: test_trunc_si64:
389; RV64IF:       # %bb.0:
390; RV64IF-NEXT:    feq.s a0, fa0, fa0
391; RV64IF-NEXT:    beqz a0, .LBB9_2
392; RV64IF-NEXT:  # %bb.1:
393; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
394; RV64IF-NEXT:  .LBB9_2:
395; RV64IF-NEXT:    ret
396  %a = call float @llvm.trunc.f32(float %x)
397  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
398  ret i64 %b
399}
400
401define signext i32 @test_trunc_ui32(float %x) {
402; CHECKIF-LABEL: test_trunc_ui32:
403; CHECKIF:       # %bb.0:
404; CHECKIF-NEXT:    feq.s a0, fa0, fa0
405; CHECKIF-NEXT:    beqz a0, .LBB10_2
406; CHECKIF-NEXT:  # %bb.1:
407; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
408; CHECKIF-NEXT:  .LBB10_2:
409; CHECKIF-NEXT:    ret
410  %a = call float @llvm.trunc.f32(float %x)
411  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
412  ret i32 %b
413}
414
415define i64 @test_trunc_ui64(float %x) nounwind {
416; RV32IF-LABEL: test_trunc_ui64:
417; RV32IF:       # %bb.0:
418; RV32IF-NEXT:    addi sp, sp, -16
419; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
420; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
421; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
422; RV32IF-NEXT:    call truncf@plt
423; RV32IF-NEXT:    fmv.s fs0, fa0
424; RV32IF-NEXT:    fmv.w.x ft0, zero
425; RV32IF-NEXT:    fle.s s0, ft0, fa0
426; RV32IF-NEXT:    call __fixunssfdi@plt
427; RV32IF-NEXT:    mv a3, a0
428; RV32IF-NEXT:    bnez s0, .LBB11_2
429; RV32IF-NEXT:  # %bb.1:
430; RV32IF-NEXT:    li a3, 0
431; RV32IF-NEXT:  .LBB11_2:
432; RV32IF-NEXT:    lui a0, %hi(.LCPI11_0)
433; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
434; RV32IF-NEXT:    flt.s a4, ft0, fs0
435; RV32IF-NEXT:    li a2, -1
436; RV32IF-NEXT:    li a0, -1
437; RV32IF-NEXT:    beqz a4, .LBB11_7
438; RV32IF-NEXT:  # %bb.3:
439; RV32IF-NEXT:    beqz s0, .LBB11_8
440; RV32IF-NEXT:  .LBB11_4:
441; RV32IF-NEXT:    bnez a4, .LBB11_6
442; RV32IF-NEXT:  .LBB11_5:
443; RV32IF-NEXT:    mv a2, a1
444; RV32IF-NEXT:  .LBB11_6:
445; RV32IF-NEXT:    mv a1, a2
446; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
447; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
448; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
449; RV32IF-NEXT:    addi sp, sp, 16
450; RV32IF-NEXT:    ret
451; RV32IF-NEXT:  .LBB11_7:
452; RV32IF-NEXT:    mv a0, a3
453; RV32IF-NEXT:    bnez s0, .LBB11_4
454; RV32IF-NEXT:  .LBB11_8:
455; RV32IF-NEXT:    li a1, 0
456; RV32IF-NEXT:    beqz a4, .LBB11_5
457; RV32IF-NEXT:    j .LBB11_6
458;
459; RV64IF-LABEL: test_trunc_ui64:
460; RV64IF:       # %bb.0:
461; RV64IF-NEXT:    feq.s a0, fa0, fa0
462; RV64IF-NEXT:    beqz a0, .LBB11_2
463; RV64IF-NEXT:  # %bb.1:
464; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
465; RV64IF-NEXT:  .LBB11_2:
466; RV64IF-NEXT:    ret
467  %a = call float @llvm.trunc.f32(float %x)
468  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
469  ret i64 %b
470}
471
472define signext i32 @test_round_si32(float %x) {
473; CHECKIF-LABEL: test_round_si32:
474; CHECKIF:       # %bb.0:
475; CHECKIF-NEXT:    feq.s a0, fa0, fa0
476; CHECKIF-NEXT:    beqz a0, .LBB12_2
477; CHECKIF-NEXT:  # %bb.1:
478; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rmm
479; CHECKIF-NEXT:  .LBB12_2:
480; CHECKIF-NEXT:    ret
481  %a = call float @llvm.round.f32(float %x)
482  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
483  ret i32 %b
484}
485
486define i64 @test_round_si64(float %x) nounwind {
487; RV32IF-LABEL: test_round_si64:
488; RV32IF:       # %bb.0:
489; RV32IF-NEXT:    addi sp, sp, -16
490; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
491; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
492; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
493; RV32IF-NEXT:    call roundf@plt
494; RV32IF-NEXT:    lui a0, %hi(.LCPI13_0)
495; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_0)(a0)
496; RV32IF-NEXT:    fmv.s fs0, fa0
497; RV32IF-NEXT:    fle.s s0, ft0, fa0
498; RV32IF-NEXT:    call __fixsfdi@plt
499; RV32IF-NEXT:    mv a2, a0
500; RV32IF-NEXT:    bnez s0, .LBB13_2
501; RV32IF-NEXT:  # %bb.1:
502; RV32IF-NEXT:    li a2, 0
503; RV32IF-NEXT:  .LBB13_2:
504; RV32IF-NEXT:    lui a0, %hi(.LCPI13_1)
505; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_1)(a0)
506; RV32IF-NEXT:    flt.s a3, ft0, fs0
507; RV32IF-NEXT:    li a0, -1
508; RV32IF-NEXT:    beqz a3, .LBB13_9
509; RV32IF-NEXT:  # %bb.3:
510; RV32IF-NEXT:    feq.s a2, fs0, fs0
511; RV32IF-NEXT:    beqz a2, .LBB13_10
512; RV32IF-NEXT:  .LBB13_4:
513; RV32IF-NEXT:    lui a4, 524288
514; RV32IF-NEXT:    beqz s0, .LBB13_11
515; RV32IF-NEXT:  .LBB13_5:
516; RV32IF-NEXT:    bnez a3, .LBB13_12
517; RV32IF-NEXT:  .LBB13_6:
518; RV32IF-NEXT:    bnez a2, .LBB13_8
519; RV32IF-NEXT:  .LBB13_7:
520; RV32IF-NEXT:    li a1, 0
521; RV32IF-NEXT:  .LBB13_8:
522; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
523; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
524; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
525; RV32IF-NEXT:    addi sp, sp, 16
526; RV32IF-NEXT:    ret
527; RV32IF-NEXT:  .LBB13_9:
528; RV32IF-NEXT:    mv a0, a2
529; RV32IF-NEXT:    feq.s a2, fs0, fs0
530; RV32IF-NEXT:    bnez a2, .LBB13_4
531; RV32IF-NEXT:  .LBB13_10:
532; RV32IF-NEXT:    li a0, 0
533; RV32IF-NEXT:    lui a4, 524288
534; RV32IF-NEXT:    bnez s0, .LBB13_5
535; RV32IF-NEXT:  .LBB13_11:
536; RV32IF-NEXT:    lui a1, 524288
537; RV32IF-NEXT:    beqz a3, .LBB13_6
538; RV32IF-NEXT:  .LBB13_12:
539; RV32IF-NEXT:    addi a1, a4, -1
540; RV32IF-NEXT:    beqz a2, .LBB13_7
541; RV32IF-NEXT:    j .LBB13_8
542;
543; RV64IF-LABEL: test_round_si64:
544; RV64IF:       # %bb.0:
545; RV64IF-NEXT:    feq.s a0, fa0, fa0
546; RV64IF-NEXT:    beqz a0, .LBB13_2
547; RV64IF-NEXT:  # %bb.1:
548; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
549; RV64IF-NEXT:  .LBB13_2:
550; RV64IF-NEXT:    ret
551  %a = call float @llvm.round.f32(float %x)
552  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
553  ret i64 %b
554}
555
556define signext i32 @test_round_ui32(float %x) {
557; CHECKIF-LABEL: test_round_ui32:
558; CHECKIF:       # %bb.0:
559; CHECKIF-NEXT:    feq.s a0, fa0, fa0
560; CHECKIF-NEXT:    beqz a0, .LBB14_2
561; CHECKIF-NEXT:  # %bb.1:
562; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rmm
563; CHECKIF-NEXT:  .LBB14_2:
564; CHECKIF-NEXT:    ret
565  %a = call float @llvm.round.f32(float %x)
566  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
567  ret i32 %b
568}
569
570define i64 @test_round_ui64(float %x) nounwind {
571; RV32IF-LABEL: test_round_ui64:
572; RV32IF:       # %bb.0:
573; RV32IF-NEXT:    addi sp, sp, -16
574; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
575; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
576; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
577; RV32IF-NEXT:    call roundf@plt
578; RV32IF-NEXT:    fmv.s fs0, fa0
579; RV32IF-NEXT:    fmv.w.x ft0, zero
580; RV32IF-NEXT:    fle.s s0, ft0, fa0
581; RV32IF-NEXT:    call __fixunssfdi@plt
582; RV32IF-NEXT:    mv a3, a0
583; RV32IF-NEXT:    bnez s0, .LBB15_2
584; RV32IF-NEXT:  # %bb.1:
585; RV32IF-NEXT:    li a3, 0
586; RV32IF-NEXT:  .LBB15_2:
587; RV32IF-NEXT:    lui a0, %hi(.LCPI15_0)
588; RV32IF-NEXT:    flw ft0, %lo(.LCPI15_0)(a0)
589; RV32IF-NEXT:    flt.s a4, ft0, fs0
590; RV32IF-NEXT:    li a2, -1
591; RV32IF-NEXT:    li a0, -1
592; RV32IF-NEXT:    beqz a4, .LBB15_7
593; RV32IF-NEXT:  # %bb.3:
594; RV32IF-NEXT:    beqz s0, .LBB15_8
595; RV32IF-NEXT:  .LBB15_4:
596; RV32IF-NEXT:    bnez a4, .LBB15_6
597; RV32IF-NEXT:  .LBB15_5:
598; RV32IF-NEXT:    mv a2, a1
599; RV32IF-NEXT:  .LBB15_6:
600; RV32IF-NEXT:    mv a1, a2
601; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
602; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
603; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
604; RV32IF-NEXT:    addi sp, sp, 16
605; RV32IF-NEXT:    ret
606; RV32IF-NEXT:  .LBB15_7:
607; RV32IF-NEXT:    mv a0, a3
608; RV32IF-NEXT:    bnez s0, .LBB15_4
609; RV32IF-NEXT:  .LBB15_8:
610; RV32IF-NEXT:    li a1, 0
611; RV32IF-NEXT:    beqz a4, .LBB15_5
612; RV32IF-NEXT:    j .LBB15_6
613;
614; RV64IF-LABEL: test_round_ui64:
615; RV64IF:       # %bb.0:
616; RV64IF-NEXT:    feq.s a0, fa0, fa0
617; RV64IF-NEXT:    beqz a0, .LBB15_2
618; RV64IF-NEXT:  # %bb.1:
619; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
620; RV64IF-NEXT:  .LBB15_2:
621; RV64IF-NEXT:    ret
622  %a = call float @llvm.round.f32(float %x)
623  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
624  ret i64 %b
625}
626
627define signext i32 @test_roundeven_si32(float %x) {
628; CHECKIF-LABEL: test_roundeven_si32:
629; CHECKIF:       # %bb.0:
630; CHECKIF-NEXT:    feq.s a0, fa0, fa0
631; CHECKIF-NEXT:    beqz a0, .LBB16_2
632; CHECKIF-NEXT:  # %bb.1:
633; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rne
634; CHECKIF-NEXT:  .LBB16_2:
635; CHECKIF-NEXT:    ret
636  %a = call float @llvm.roundeven.f32(float %x)
637  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
638  ret i32 %b
639}
640
641define i64 @test_roundeven_si64(float %x) nounwind {
642; RV32IF-LABEL: test_roundeven_si64:
643; RV32IF:       # %bb.0:
644; RV32IF-NEXT:    addi sp, sp, -16
645; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
646; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
647; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
648; RV32IF-NEXT:    call roundevenf@plt
649; RV32IF-NEXT:    lui a0, %hi(.LCPI17_0)
650; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_0)(a0)
651; RV32IF-NEXT:    fmv.s fs0, fa0
652; RV32IF-NEXT:    fle.s s0, ft0, fa0
653; RV32IF-NEXT:    call __fixsfdi@plt
654; RV32IF-NEXT:    mv a2, a0
655; RV32IF-NEXT:    bnez s0, .LBB17_2
656; RV32IF-NEXT:  # %bb.1:
657; RV32IF-NEXT:    li a2, 0
658; RV32IF-NEXT:  .LBB17_2:
659; RV32IF-NEXT:    lui a0, %hi(.LCPI17_1)
660; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_1)(a0)
661; RV32IF-NEXT:    flt.s a3, ft0, fs0
662; RV32IF-NEXT:    li a0, -1
663; RV32IF-NEXT:    beqz a3, .LBB17_9
664; RV32IF-NEXT:  # %bb.3:
665; RV32IF-NEXT:    feq.s a2, fs0, fs0
666; RV32IF-NEXT:    beqz a2, .LBB17_10
667; RV32IF-NEXT:  .LBB17_4:
668; RV32IF-NEXT:    lui a4, 524288
669; RV32IF-NEXT:    beqz s0, .LBB17_11
670; RV32IF-NEXT:  .LBB17_5:
671; RV32IF-NEXT:    bnez a3, .LBB17_12
672; RV32IF-NEXT:  .LBB17_6:
673; RV32IF-NEXT:    bnez a2, .LBB17_8
674; RV32IF-NEXT:  .LBB17_7:
675; RV32IF-NEXT:    li a1, 0
676; RV32IF-NEXT:  .LBB17_8:
677; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
678; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
679; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
680; RV32IF-NEXT:    addi sp, sp, 16
681; RV32IF-NEXT:    ret
682; RV32IF-NEXT:  .LBB17_9:
683; RV32IF-NEXT:    mv a0, a2
684; RV32IF-NEXT:    feq.s a2, fs0, fs0
685; RV32IF-NEXT:    bnez a2, .LBB17_4
686; RV32IF-NEXT:  .LBB17_10:
687; RV32IF-NEXT:    li a0, 0
688; RV32IF-NEXT:    lui a4, 524288
689; RV32IF-NEXT:    bnez s0, .LBB17_5
690; RV32IF-NEXT:  .LBB17_11:
691; RV32IF-NEXT:    lui a1, 524288
692; RV32IF-NEXT:    beqz a3, .LBB17_6
693; RV32IF-NEXT:  .LBB17_12:
694; RV32IF-NEXT:    addi a1, a4, -1
695; RV32IF-NEXT:    beqz a2, .LBB17_7
696; RV32IF-NEXT:    j .LBB17_8
697;
698; RV64IF-LABEL: test_roundeven_si64:
699; RV64IF:       # %bb.0:
700; RV64IF-NEXT:    feq.s a0, fa0, fa0
701; RV64IF-NEXT:    beqz a0, .LBB17_2
702; RV64IF-NEXT:  # %bb.1:
703; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
704; RV64IF-NEXT:  .LBB17_2:
705; RV64IF-NEXT:    ret
706  %a = call float @llvm.roundeven.f32(float %x)
707  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
708  ret i64 %b
709}
710
711define signext i32 @test_roundeven_ui32(float %x) {
712; CHECKIF-LABEL: test_roundeven_ui32:
713; CHECKIF:       # %bb.0:
714; CHECKIF-NEXT:    feq.s a0, fa0, fa0
715; CHECKIF-NEXT:    beqz a0, .LBB18_2
716; CHECKIF-NEXT:  # %bb.1:
717; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rne
718; CHECKIF-NEXT:  .LBB18_2:
719; CHECKIF-NEXT:    ret
720  %a = call float @llvm.roundeven.f32(float %x)
721  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
722  ret i32 %b
723}
724
725define i64 @test_roundeven_ui64(float %x) nounwind {
726; RV32IF-LABEL: test_roundeven_ui64:
727; RV32IF:       # %bb.0:
728; RV32IF-NEXT:    addi sp, sp, -16
729; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
730; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
731; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
732; RV32IF-NEXT:    call roundevenf@plt
733; RV32IF-NEXT:    fmv.s fs0, fa0
734; RV32IF-NEXT:    fmv.w.x ft0, zero
735; RV32IF-NEXT:    fle.s s0, ft0, fa0
736; RV32IF-NEXT:    call __fixunssfdi@plt
737; RV32IF-NEXT:    mv a3, a0
738; RV32IF-NEXT:    bnez s0, .LBB19_2
739; RV32IF-NEXT:  # %bb.1:
740; RV32IF-NEXT:    li a3, 0
741; RV32IF-NEXT:  .LBB19_2:
742; RV32IF-NEXT:    lui a0, %hi(.LCPI19_0)
743; RV32IF-NEXT:    flw ft0, %lo(.LCPI19_0)(a0)
744; RV32IF-NEXT:    flt.s a4, ft0, fs0
745; RV32IF-NEXT:    li a2, -1
746; RV32IF-NEXT:    li a0, -1
747; RV32IF-NEXT:    beqz a4, .LBB19_7
748; RV32IF-NEXT:  # %bb.3:
749; RV32IF-NEXT:    beqz s0, .LBB19_8
750; RV32IF-NEXT:  .LBB19_4:
751; RV32IF-NEXT:    bnez a4, .LBB19_6
752; RV32IF-NEXT:  .LBB19_5:
753; RV32IF-NEXT:    mv a2, a1
754; RV32IF-NEXT:  .LBB19_6:
755; RV32IF-NEXT:    mv a1, a2
756; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
757; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
758; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
759; RV32IF-NEXT:    addi sp, sp, 16
760; RV32IF-NEXT:    ret
761; RV32IF-NEXT:  .LBB19_7:
762; RV32IF-NEXT:    mv a0, a3
763; RV32IF-NEXT:    bnez s0, .LBB19_4
764; RV32IF-NEXT:  .LBB19_8:
765; RV32IF-NEXT:    li a1, 0
766; RV32IF-NEXT:    beqz a4, .LBB19_5
767; RV32IF-NEXT:    j .LBB19_6
768;
769; RV64IF-LABEL: test_roundeven_ui64:
770; RV64IF:       # %bb.0:
771; RV64IF-NEXT:    feq.s a0, fa0, fa0
772; RV64IF-NEXT:    beqz a0, .LBB19_2
773; RV64IF-NEXT:  # %bb.1:
774; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
775; RV64IF-NEXT:  .LBB19_2:
776; RV64IF-NEXT:    ret
777  %a = call float @llvm.roundeven.f32(float %x)
778  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
779  ret i64 %b
780}
781
782declare float @llvm.floor.f32(float)
783declare float @llvm.ceil.f32(float)
784declare float @llvm.trunc.f32(float)
785declare float @llvm.round.f32(float)
786declare float @llvm.roundeven.f32(float)
787declare i32 @llvm.fptosi.sat.i32.f32(float)
788declare i64 @llvm.fptosi.sat.i64.f32(float)
789declare i32 @llvm.fptoui.sat.i32.f32(float)
790declare i64 @llvm.fptoui.sat.i64.f32(float)
791