1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
6
7define signext i32 @test_floor_si32(float %x) {
8; RV32IF-LABEL: test_floor_si32:
9; RV32IF:       # %bb.0:
10; RV32IF-NEXT:    feq.s a0, fa0, fa0
11; RV32IF-NEXT:    bnez a0, .LBB0_2
12; RV32IF-NEXT:  # %bb.1:
13; RV32IF-NEXT:    li a0, 0
14; RV32IF-NEXT:    ret
15; RV32IF-NEXT:  .LBB0_2:
16; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
17; RV32IF-NEXT:    ret
18;
19; RV64IF-LABEL: test_floor_si32:
20; RV64IF:       # %bb.0:
21; RV64IF-NEXT:    feq.s a0, fa0, fa0
22; RV64IF-NEXT:    bnez a0, .LBB0_2
23; RV64IF-NEXT:  # %bb.1:
24; RV64IF-NEXT:    li a0, 0
25; RV64IF-NEXT:    ret
26; RV64IF-NEXT:  .LBB0_2:
27; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
28; RV64IF-NEXT:    ret
29  %a = call float @llvm.floor.f32(float %x)
30  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
31  ret i32 %b
32}
33
34define i64 @test_floor_si64(float %x) nounwind {
35; RV32IF-LABEL: test_floor_si64:
36; RV32IF:       # %bb.0:
37; RV32IF-NEXT:    addi sp, sp, -16
38; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
39; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
40; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
41; RV32IF-NEXT:    call floorf@plt
42; RV32IF-NEXT:    lui a0, %hi(.LCPI1_0)
43; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
44; RV32IF-NEXT:    fmv.s fs0, fa0
45; RV32IF-NEXT:    fle.s s0, ft0, fa0
46; RV32IF-NEXT:    call __fixsfdi@plt
47; RV32IF-NEXT:    mv a2, a0
48; RV32IF-NEXT:    bnez s0, .LBB1_2
49; RV32IF-NEXT:  # %bb.1:
50; RV32IF-NEXT:    li a2, 0
51; RV32IF-NEXT:  .LBB1_2:
52; RV32IF-NEXT:    lui a0, %hi(.LCPI1_1)
53; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_1)(a0)
54; RV32IF-NEXT:    flt.s a3, ft0, fs0
55; RV32IF-NEXT:    li a0, -1
56; RV32IF-NEXT:    beqz a3, .LBB1_9
57; RV32IF-NEXT:  # %bb.3:
58; RV32IF-NEXT:    feq.s a2, fs0, fs0
59; RV32IF-NEXT:    beqz a2, .LBB1_10
60; RV32IF-NEXT:  .LBB1_4:
61; RV32IF-NEXT:    lui a4, 524288
62; RV32IF-NEXT:    beqz s0, .LBB1_11
63; RV32IF-NEXT:  .LBB1_5:
64; RV32IF-NEXT:    bnez a3, .LBB1_12
65; RV32IF-NEXT:  .LBB1_6:
66; RV32IF-NEXT:    bnez a2, .LBB1_8
67; RV32IF-NEXT:  .LBB1_7:
68; RV32IF-NEXT:    li a1, 0
69; RV32IF-NEXT:  .LBB1_8:
70; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
71; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
72; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
73; RV32IF-NEXT:    addi sp, sp, 16
74; RV32IF-NEXT:    ret
75; RV32IF-NEXT:  .LBB1_9:
76; RV32IF-NEXT:    mv a0, a2
77; RV32IF-NEXT:    feq.s a2, fs0, fs0
78; RV32IF-NEXT:    bnez a2, .LBB1_4
79; RV32IF-NEXT:  .LBB1_10:
80; RV32IF-NEXT:    li a0, 0
81; RV32IF-NEXT:    lui a4, 524288
82; RV32IF-NEXT:    bnez s0, .LBB1_5
83; RV32IF-NEXT:  .LBB1_11:
84; RV32IF-NEXT:    lui a1, 524288
85; RV32IF-NEXT:    beqz a3, .LBB1_6
86; RV32IF-NEXT:  .LBB1_12:
87; RV32IF-NEXT:    addi a1, a4, -1
88; RV32IF-NEXT:    beqz a2, .LBB1_7
89; RV32IF-NEXT:    j .LBB1_8
90;
91; RV64IF-LABEL: test_floor_si64:
92; RV64IF:       # %bb.0:
93; RV64IF-NEXT:    feq.s a0, fa0, fa0
94; RV64IF-NEXT:    bnez a0, .LBB1_2
95; RV64IF-NEXT:  # %bb.1:
96; RV64IF-NEXT:    li a0, 0
97; RV64IF-NEXT:    ret
98; RV64IF-NEXT:  .LBB1_2:
99; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
100; RV64IF-NEXT:    ret
101  %a = call float @llvm.floor.f32(float %x)
102  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
103  ret i64 %b
104}
105
106define signext i32 @test_floor_ui32(float %x) {
107; RV32IF-LABEL: test_floor_ui32:
108; RV32IF:       # %bb.0:
109; RV32IF-NEXT:    feq.s a0, fa0, fa0
110; RV32IF-NEXT:    bnez a0, .LBB2_2
111; RV32IF-NEXT:  # %bb.1:
112; RV32IF-NEXT:    li a0, 0
113; RV32IF-NEXT:    ret
114; RV32IF-NEXT:  .LBB2_2:
115; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
116; RV32IF-NEXT:    ret
117;
118; RV64IF-LABEL: test_floor_ui32:
119; RV64IF:       # %bb.0:
120; RV64IF-NEXT:    feq.s a0, fa0, fa0
121; RV64IF-NEXT:    bnez a0, .LBB2_2
122; RV64IF-NEXT:  # %bb.1:
123; RV64IF-NEXT:    li a0, 0
124; RV64IF-NEXT:    ret
125; RV64IF-NEXT:  .LBB2_2:
126; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
127; RV64IF-NEXT:    ret
128  %a = call float @llvm.floor.f32(float %x)
129  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
130  ret i32 %b
131}
132
133define i64 @test_floor_ui64(float %x) nounwind {
134; RV32IF-LABEL: test_floor_ui64:
135; RV32IF:       # %bb.0:
136; RV32IF-NEXT:    addi sp, sp, -16
137; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
138; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
139; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
140; RV32IF-NEXT:    call floorf@plt
141; RV32IF-NEXT:    fmv.s fs0, fa0
142; RV32IF-NEXT:    fmv.w.x ft0, zero
143; RV32IF-NEXT:    fle.s s0, ft0, fa0
144; RV32IF-NEXT:    call __fixunssfdi@plt
145; RV32IF-NEXT:    mv a3, a0
146; RV32IF-NEXT:    bnez s0, .LBB3_2
147; RV32IF-NEXT:  # %bb.1:
148; RV32IF-NEXT:    li a3, 0
149; RV32IF-NEXT:  .LBB3_2:
150; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
151; RV32IF-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
152; RV32IF-NEXT:    flt.s a4, ft0, fs0
153; RV32IF-NEXT:    li a2, -1
154; RV32IF-NEXT:    li a0, -1
155; RV32IF-NEXT:    beqz a4, .LBB3_7
156; RV32IF-NEXT:  # %bb.3:
157; RV32IF-NEXT:    beqz s0, .LBB3_8
158; RV32IF-NEXT:  .LBB3_4:
159; RV32IF-NEXT:    bnez a4, .LBB3_6
160; RV32IF-NEXT:  .LBB3_5:
161; RV32IF-NEXT:    mv a2, a1
162; RV32IF-NEXT:  .LBB3_6:
163; RV32IF-NEXT:    mv a1, a2
164; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
165; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
166; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
167; RV32IF-NEXT:    addi sp, sp, 16
168; RV32IF-NEXT:    ret
169; RV32IF-NEXT:  .LBB3_7:
170; RV32IF-NEXT:    mv a0, a3
171; RV32IF-NEXT:    bnez s0, .LBB3_4
172; RV32IF-NEXT:  .LBB3_8:
173; RV32IF-NEXT:    li a1, 0
174; RV32IF-NEXT:    beqz a4, .LBB3_5
175; RV32IF-NEXT:    j .LBB3_6
176;
177; RV64IF-LABEL: test_floor_ui64:
178; RV64IF:       # %bb.0:
179; RV64IF-NEXT:    feq.s a0, fa0, fa0
180; RV64IF-NEXT:    bnez a0, .LBB3_2
181; RV64IF-NEXT:  # %bb.1:
182; RV64IF-NEXT:    li a0, 0
183; RV64IF-NEXT:    ret
184; RV64IF-NEXT:  .LBB3_2:
185; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
186; RV64IF-NEXT:    ret
187  %a = call float @llvm.floor.f32(float %x)
188  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
189  ret i64 %b
190}
191
192define signext i32 @test_ceil_si32(float %x) {
193; RV32IF-LABEL: test_ceil_si32:
194; RV32IF:       # %bb.0:
195; RV32IF-NEXT:    feq.s a0, fa0, fa0
196; RV32IF-NEXT:    bnez a0, .LBB4_2
197; RV32IF-NEXT:  # %bb.1:
198; RV32IF-NEXT:    li a0, 0
199; RV32IF-NEXT:    ret
200; RV32IF-NEXT:  .LBB4_2:
201; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
202; RV32IF-NEXT:    ret
203;
204; RV64IF-LABEL: test_ceil_si32:
205; RV64IF:       # %bb.0:
206; RV64IF-NEXT:    feq.s a0, fa0, fa0
207; RV64IF-NEXT:    bnez a0, .LBB4_2
208; RV64IF-NEXT:  # %bb.1:
209; RV64IF-NEXT:    li a0, 0
210; RV64IF-NEXT:    ret
211; RV64IF-NEXT:  .LBB4_2:
212; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
213; RV64IF-NEXT:    ret
214  %a = call float @llvm.ceil.f32(float %x)
215  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
216  ret i32 %b
217}
218
219define i64 @test_ceil_si64(float %x) nounwind {
220; RV32IF-LABEL: test_ceil_si64:
221; RV32IF:       # %bb.0:
222; RV32IF-NEXT:    addi sp, sp, -16
223; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
224; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
225; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
226; RV32IF-NEXT:    call ceilf@plt
227; RV32IF-NEXT:    lui a0, %hi(.LCPI5_0)
228; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_0)(a0)
229; RV32IF-NEXT:    fmv.s fs0, fa0
230; RV32IF-NEXT:    fle.s s0, ft0, fa0
231; RV32IF-NEXT:    call __fixsfdi@plt
232; RV32IF-NEXT:    mv a2, a0
233; RV32IF-NEXT:    bnez s0, .LBB5_2
234; RV32IF-NEXT:  # %bb.1:
235; RV32IF-NEXT:    li a2, 0
236; RV32IF-NEXT:  .LBB5_2:
237; RV32IF-NEXT:    lui a0, %hi(.LCPI5_1)
238; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_1)(a0)
239; RV32IF-NEXT:    flt.s a3, ft0, fs0
240; RV32IF-NEXT:    li a0, -1
241; RV32IF-NEXT:    beqz a3, .LBB5_9
242; RV32IF-NEXT:  # %bb.3:
243; RV32IF-NEXT:    feq.s a2, fs0, fs0
244; RV32IF-NEXT:    beqz a2, .LBB5_10
245; RV32IF-NEXT:  .LBB5_4:
246; RV32IF-NEXT:    lui a4, 524288
247; RV32IF-NEXT:    beqz s0, .LBB5_11
248; RV32IF-NEXT:  .LBB5_5:
249; RV32IF-NEXT:    bnez a3, .LBB5_12
250; RV32IF-NEXT:  .LBB5_6:
251; RV32IF-NEXT:    bnez a2, .LBB5_8
252; RV32IF-NEXT:  .LBB5_7:
253; RV32IF-NEXT:    li a1, 0
254; RV32IF-NEXT:  .LBB5_8:
255; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
256; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
257; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
258; RV32IF-NEXT:    addi sp, sp, 16
259; RV32IF-NEXT:    ret
260; RV32IF-NEXT:  .LBB5_9:
261; RV32IF-NEXT:    mv a0, a2
262; RV32IF-NEXT:    feq.s a2, fs0, fs0
263; RV32IF-NEXT:    bnez a2, .LBB5_4
264; RV32IF-NEXT:  .LBB5_10:
265; RV32IF-NEXT:    li a0, 0
266; RV32IF-NEXT:    lui a4, 524288
267; RV32IF-NEXT:    bnez s0, .LBB5_5
268; RV32IF-NEXT:  .LBB5_11:
269; RV32IF-NEXT:    lui a1, 524288
270; RV32IF-NEXT:    beqz a3, .LBB5_6
271; RV32IF-NEXT:  .LBB5_12:
272; RV32IF-NEXT:    addi a1, a4, -1
273; RV32IF-NEXT:    beqz a2, .LBB5_7
274; RV32IF-NEXT:    j .LBB5_8
275;
276; RV64IF-LABEL: test_ceil_si64:
277; RV64IF:       # %bb.0:
278; RV64IF-NEXT:    feq.s a0, fa0, fa0
279; RV64IF-NEXT:    bnez a0, .LBB5_2
280; RV64IF-NEXT:  # %bb.1:
281; RV64IF-NEXT:    li a0, 0
282; RV64IF-NEXT:    ret
283; RV64IF-NEXT:  .LBB5_2:
284; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
285; RV64IF-NEXT:    ret
286  %a = call float @llvm.ceil.f32(float %x)
287  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
288  ret i64 %b
289}
290
291define signext i32 @test_ceil_ui32(float %x) {
292; RV32IF-LABEL: test_ceil_ui32:
293; RV32IF:       # %bb.0:
294; RV32IF-NEXT:    feq.s a0, fa0, fa0
295; RV32IF-NEXT:    bnez a0, .LBB6_2
296; RV32IF-NEXT:  # %bb.1:
297; RV32IF-NEXT:    li a0, 0
298; RV32IF-NEXT:    ret
299; RV32IF-NEXT:  .LBB6_2:
300; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
301; RV32IF-NEXT:    ret
302;
303; RV64IF-LABEL: test_ceil_ui32:
304; RV64IF:       # %bb.0:
305; RV64IF-NEXT:    feq.s a0, fa0, fa0
306; RV64IF-NEXT:    bnez a0, .LBB6_2
307; RV64IF-NEXT:  # %bb.1:
308; RV64IF-NEXT:    li a0, 0
309; RV64IF-NEXT:    ret
310; RV64IF-NEXT:  .LBB6_2:
311; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
312; RV64IF-NEXT:    ret
313  %a = call float @llvm.ceil.f32(float %x)
314  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
315  ret i32 %b
316}
317
318define i64 @test_ceil_ui64(float %x) nounwind {
319; RV32IF-LABEL: test_ceil_ui64:
320; RV32IF:       # %bb.0:
321; RV32IF-NEXT:    addi sp, sp, -16
322; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
323; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
324; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
325; RV32IF-NEXT:    call ceilf@plt
326; RV32IF-NEXT:    fmv.s fs0, fa0
327; RV32IF-NEXT:    fmv.w.x ft0, zero
328; RV32IF-NEXT:    fle.s s0, ft0, fa0
329; RV32IF-NEXT:    call __fixunssfdi@plt
330; RV32IF-NEXT:    mv a3, a0
331; RV32IF-NEXT:    bnez s0, .LBB7_2
332; RV32IF-NEXT:  # %bb.1:
333; RV32IF-NEXT:    li a3, 0
334; RV32IF-NEXT:  .LBB7_2:
335; RV32IF-NEXT:    lui a0, %hi(.LCPI7_0)
336; RV32IF-NEXT:    flw ft0, %lo(.LCPI7_0)(a0)
337; RV32IF-NEXT:    flt.s a4, ft0, fs0
338; RV32IF-NEXT:    li a2, -1
339; RV32IF-NEXT:    li a0, -1
340; RV32IF-NEXT:    beqz a4, .LBB7_7
341; RV32IF-NEXT:  # %bb.3:
342; RV32IF-NEXT:    beqz s0, .LBB7_8
343; RV32IF-NEXT:  .LBB7_4:
344; RV32IF-NEXT:    bnez a4, .LBB7_6
345; RV32IF-NEXT:  .LBB7_5:
346; RV32IF-NEXT:    mv a2, a1
347; RV32IF-NEXT:  .LBB7_6:
348; RV32IF-NEXT:    mv a1, a2
349; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
350; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
351; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
352; RV32IF-NEXT:    addi sp, sp, 16
353; RV32IF-NEXT:    ret
354; RV32IF-NEXT:  .LBB7_7:
355; RV32IF-NEXT:    mv a0, a3
356; RV32IF-NEXT:    bnez s0, .LBB7_4
357; RV32IF-NEXT:  .LBB7_8:
358; RV32IF-NEXT:    li a1, 0
359; RV32IF-NEXT:    beqz a4, .LBB7_5
360; RV32IF-NEXT:    j .LBB7_6
361;
362; RV64IF-LABEL: test_ceil_ui64:
363; RV64IF:       # %bb.0:
364; RV64IF-NEXT:    feq.s a0, fa0, fa0
365; RV64IF-NEXT:    bnez a0, .LBB7_2
366; RV64IF-NEXT:  # %bb.1:
367; RV64IF-NEXT:    li a0, 0
368; RV64IF-NEXT:    ret
369; RV64IF-NEXT:  .LBB7_2:
370; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
371; RV64IF-NEXT:    ret
372  %a = call float @llvm.ceil.f32(float %x)
373  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
374  ret i64 %b
375}
376
377define signext i32 @test_trunc_si32(float %x) {
378; RV32IF-LABEL: test_trunc_si32:
379; RV32IF:       # %bb.0:
380; RV32IF-NEXT:    feq.s a0, fa0, fa0
381; RV32IF-NEXT:    bnez a0, .LBB8_2
382; RV32IF-NEXT:  # %bb.1:
383; RV32IF-NEXT:    li a0, 0
384; RV32IF-NEXT:    ret
385; RV32IF-NEXT:  .LBB8_2:
386; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
387; RV32IF-NEXT:    ret
388;
389; RV64IF-LABEL: test_trunc_si32:
390; RV64IF:       # %bb.0:
391; RV64IF-NEXT:    feq.s a0, fa0, fa0
392; RV64IF-NEXT:    bnez a0, .LBB8_2
393; RV64IF-NEXT:  # %bb.1:
394; RV64IF-NEXT:    li a0, 0
395; RV64IF-NEXT:    ret
396; RV64IF-NEXT:  .LBB8_2:
397; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
398; RV64IF-NEXT:    ret
399  %a = call float @llvm.trunc.f32(float %x)
400  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
401  ret i32 %b
402}
403
404define i64 @test_trunc_si64(float %x) nounwind {
405; RV32IF-LABEL: test_trunc_si64:
406; RV32IF:       # %bb.0:
407; RV32IF-NEXT:    addi sp, sp, -16
408; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
409; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
410; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
411; RV32IF-NEXT:    call truncf@plt
412; RV32IF-NEXT:    lui a0, %hi(.LCPI9_0)
413; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
414; RV32IF-NEXT:    fmv.s fs0, fa0
415; RV32IF-NEXT:    fle.s s0, ft0, fa0
416; RV32IF-NEXT:    call __fixsfdi@plt
417; RV32IF-NEXT:    mv a2, a0
418; RV32IF-NEXT:    bnez s0, .LBB9_2
419; RV32IF-NEXT:  # %bb.1:
420; RV32IF-NEXT:    li a2, 0
421; RV32IF-NEXT:  .LBB9_2:
422; RV32IF-NEXT:    lui a0, %hi(.LCPI9_1)
423; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
424; RV32IF-NEXT:    flt.s a3, ft0, fs0
425; RV32IF-NEXT:    li a0, -1
426; RV32IF-NEXT:    beqz a3, .LBB9_9
427; RV32IF-NEXT:  # %bb.3:
428; RV32IF-NEXT:    feq.s a2, fs0, fs0
429; RV32IF-NEXT:    beqz a2, .LBB9_10
430; RV32IF-NEXT:  .LBB9_4:
431; RV32IF-NEXT:    lui a4, 524288
432; RV32IF-NEXT:    beqz s0, .LBB9_11
433; RV32IF-NEXT:  .LBB9_5:
434; RV32IF-NEXT:    bnez a3, .LBB9_12
435; RV32IF-NEXT:  .LBB9_6:
436; RV32IF-NEXT:    bnez a2, .LBB9_8
437; RV32IF-NEXT:  .LBB9_7:
438; RV32IF-NEXT:    li a1, 0
439; RV32IF-NEXT:  .LBB9_8:
440; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
441; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
442; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
443; RV32IF-NEXT:    addi sp, sp, 16
444; RV32IF-NEXT:    ret
445; RV32IF-NEXT:  .LBB9_9:
446; RV32IF-NEXT:    mv a0, a2
447; RV32IF-NEXT:    feq.s a2, fs0, fs0
448; RV32IF-NEXT:    bnez a2, .LBB9_4
449; RV32IF-NEXT:  .LBB9_10:
450; RV32IF-NEXT:    li a0, 0
451; RV32IF-NEXT:    lui a4, 524288
452; RV32IF-NEXT:    bnez s0, .LBB9_5
453; RV32IF-NEXT:  .LBB9_11:
454; RV32IF-NEXT:    lui a1, 524288
455; RV32IF-NEXT:    beqz a3, .LBB9_6
456; RV32IF-NEXT:  .LBB9_12:
457; RV32IF-NEXT:    addi a1, a4, -1
458; RV32IF-NEXT:    beqz a2, .LBB9_7
459; RV32IF-NEXT:    j .LBB9_8
460;
461; RV64IF-LABEL: test_trunc_si64:
462; RV64IF:       # %bb.0:
463; RV64IF-NEXT:    feq.s a0, fa0, fa0
464; RV64IF-NEXT:    bnez a0, .LBB9_2
465; RV64IF-NEXT:  # %bb.1:
466; RV64IF-NEXT:    li a0, 0
467; RV64IF-NEXT:    ret
468; RV64IF-NEXT:  .LBB9_2:
469; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
470; RV64IF-NEXT:    ret
471  %a = call float @llvm.trunc.f32(float %x)
472  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
473  ret i64 %b
474}
475
476define signext i32 @test_trunc_ui32(float %x) {
477; RV32IF-LABEL: test_trunc_ui32:
478; RV32IF:       # %bb.0:
479; RV32IF-NEXT:    feq.s a0, fa0, fa0
480; RV32IF-NEXT:    bnez a0, .LBB10_2
481; RV32IF-NEXT:  # %bb.1:
482; RV32IF-NEXT:    li a0, 0
483; RV32IF-NEXT:    ret
484; RV32IF-NEXT:  .LBB10_2:
485; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
486; RV32IF-NEXT:    ret
487;
488; RV64IF-LABEL: test_trunc_ui32:
489; RV64IF:       # %bb.0:
490; RV64IF-NEXT:    feq.s a0, fa0, fa0
491; RV64IF-NEXT:    bnez a0, .LBB10_2
492; RV64IF-NEXT:  # %bb.1:
493; RV64IF-NEXT:    li a0, 0
494; RV64IF-NEXT:    ret
495; RV64IF-NEXT:  .LBB10_2:
496; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
497; RV64IF-NEXT:    ret
498  %a = call float @llvm.trunc.f32(float %x)
499  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
500  ret i32 %b
501}
502
503define i64 @test_trunc_ui64(float %x) nounwind {
504; RV32IF-LABEL: test_trunc_ui64:
505; RV32IF:       # %bb.0:
506; RV32IF-NEXT:    addi sp, sp, -16
507; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
508; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
509; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
510; RV32IF-NEXT:    call truncf@plt
511; RV32IF-NEXT:    fmv.s fs0, fa0
512; RV32IF-NEXT:    fmv.w.x ft0, zero
513; RV32IF-NEXT:    fle.s s0, ft0, fa0
514; RV32IF-NEXT:    call __fixunssfdi@plt
515; RV32IF-NEXT:    mv a3, a0
516; RV32IF-NEXT:    bnez s0, .LBB11_2
517; RV32IF-NEXT:  # %bb.1:
518; RV32IF-NEXT:    li a3, 0
519; RV32IF-NEXT:  .LBB11_2:
520; RV32IF-NEXT:    lui a0, %hi(.LCPI11_0)
521; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
522; RV32IF-NEXT:    flt.s a4, ft0, fs0
523; RV32IF-NEXT:    li a2, -1
524; RV32IF-NEXT:    li a0, -1
525; RV32IF-NEXT:    beqz a4, .LBB11_7
526; RV32IF-NEXT:  # %bb.3:
527; RV32IF-NEXT:    beqz s0, .LBB11_8
528; RV32IF-NEXT:  .LBB11_4:
529; RV32IF-NEXT:    bnez a4, .LBB11_6
530; RV32IF-NEXT:  .LBB11_5:
531; RV32IF-NEXT:    mv a2, a1
532; RV32IF-NEXT:  .LBB11_6:
533; RV32IF-NEXT:    mv a1, a2
534; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
535; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
536; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
537; RV32IF-NEXT:    addi sp, sp, 16
538; RV32IF-NEXT:    ret
539; RV32IF-NEXT:  .LBB11_7:
540; RV32IF-NEXT:    mv a0, a3
541; RV32IF-NEXT:    bnez s0, .LBB11_4
542; RV32IF-NEXT:  .LBB11_8:
543; RV32IF-NEXT:    li a1, 0
544; RV32IF-NEXT:    beqz a4, .LBB11_5
545; RV32IF-NEXT:    j .LBB11_6
546;
547; RV64IF-LABEL: test_trunc_ui64:
548; RV64IF:       # %bb.0:
549; RV64IF-NEXT:    feq.s a0, fa0, fa0
550; RV64IF-NEXT:    bnez a0, .LBB11_2
551; RV64IF-NEXT:  # %bb.1:
552; RV64IF-NEXT:    li a0, 0
553; RV64IF-NEXT:    ret
554; RV64IF-NEXT:  .LBB11_2:
555; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
556; RV64IF-NEXT:    ret
557  %a = call float @llvm.trunc.f32(float %x)
558  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
559  ret i64 %b
560}
561
562define signext i32 @test_round_si32(float %x) {
563; RV32IF-LABEL: test_round_si32:
564; RV32IF:       # %bb.0:
565; RV32IF-NEXT:    feq.s a0, fa0, fa0
566; RV32IF-NEXT:    bnez a0, .LBB12_2
567; RV32IF-NEXT:  # %bb.1:
568; RV32IF-NEXT:    li a0, 0
569; RV32IF-NEXT:    ret
570; RV32IF-NEXT:  .LBB12_2:
571; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
572; RV32IF-NEXT:    ret
573;
574; RV64IF-LABEL: test_round_si32:
575; RV64IF:       # %bb.0:
576; RV64IF-NEXT:    feq.s a0, fa0, fa0
577; RV64IF-NEXT:    bnez a0, .LBB12_2
578; RV64IF-NEXT:  # %bb.1:
579; RV64IF-NEXT:    li a0, 0
580; RV64IF-NEXT:    ret
581; RV64IF-NEXT:  .LBB12_2:
582; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
583; RV64IF-NEXT:    ret
584  %a = call float @llvm.round.f32(float %x)
585  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
586  ret i32 %b
587}
588
589define i64 @test_round_si64(float %x) nounwind {
590; RV32IF-LABEL: test_round_si64:
591; RV32IF:       # %bb.0:
592; RV32IF-NEXT:    addi sp, sp, -16
593; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
594; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
595; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
596; RV32IF-NEXT:    call roundf@plt
597; RV32IF-NEXT:    lui a0, %hi(.LCPI13_0)
598; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_0)(a0)
599; RV32IF-NEXT:    fmv.s fs0, fa0
600; RV32IF-NEXT:    fle.s s0, ft0, fa0
601; RV32IF-NEXT:    call __fixsfdi@plt
602; RV32IF-NEXT:    mv a2, a0
603; RV32IF-NEXT:    bnez s0, .LBB13_2
604; RV32IF-NEXT:  # %bb.1:
605; RV32IF-NEXT:    li a2, 0
606; RV32IF-NEXT:  .LBB13_2:
607; RV32IF-NEXT:    lui a0, %hi(.LCPI13_1)
608; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_1)(a0)
609; RV32IF-NEXT:    flt.s a3, ft0, fs0
610; RV32IF-NEXT:    li a0, -1
611; RV32IF-NEXT:    beqz a3, .LBB13_9
612; RV32IF-NEXT:  # %bb.3:
613; RV32IF-NEXT:    feq.s a2, fs0, fs0
614; RV32IF-NEXT:    beqz a2, .LBB13_10
615; RV32IF-NEXT:  .LBB13_4:
616; RV32IF-NEXT:    lui a4, 524288
617; RV32IF-NEXT:    beqz s0, .LBB13_11
618; RV32IF-NEXT:  .LBB13_5:
619; RV32IF-NEXT:    bnez a3, .LBB13_12
620; RV32IF-NEXT:  .LBB13_6:
621; RV32IF-NEXT:    bnez a2, .LBB13_8
622; RV32IF-NEXT:  .LBB13_7:
623; RV32IF-NEXT:    li a1, 0
624; RV32IF-NEXT:  .LBB13_8:
625; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
626; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
627; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
628; RV32IF-NEXT:    addi sp, sp, 16
629; RV32IF-NEXT:    ret
630; RV32IF-NEXT:  .LBB13_9:
631; RV32IF-NEXT:    mv a0, a2
632; RV32IF-NEXT:    feq.s a2, fs0, fs0
633; RV32IF-NEXT:    bnez a2, .LBB13_4
634; RV32IF-NEXT:  .LBB13_10:
635; RV32IF-NEXT:    li a0, 0
636; RV32IF-NEXT:    lui a4, 524288
637; RV32IF-NEXT:    bnez s0, .LBB13_5
638; RV32IF-NEXT:  .LBB13_11:
639; RV32IF-NEXT:    lui a1, 524288
640; RV32IF-NEXT:    beqz a3, .LBB13_6
641; RV32IF-NEXT:  .LBB13_12:
642; RV32IF-NEXT:    addi a1, a4, -1
643; RV32IF-NEXT:    beqz a2, .LBB13_7
644; RV32IF-NEXT:    j .LBB13_8
645;
646; RV64IF-LABEL: test_round_si64:
647; RV64IF:       # %bb.0:
648; RV64IF-NEXT:    feq.s a0, fa0, fa0
649; RV64IF-NEXT:    bnez a0, .LBB13_2
650; RV64IF-NEXT:  # %bb.1:
651; RV64IF-NEXT:    li a0, 0
652; RV64IF-NEXT:    ret
653; RV64IF-NEXT:  .LBB13_2:
654; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
655; RV64IF-NEXT:    ret
656  %a = call float @llvm.round.f32(float %x)
657  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
658  ret i64 %b
659}
660
661define signext i32 @test_round_ui32(float %x) {
662; RV32IF-LABEL: test_round_ui32:
663; RV32IF:       # %bb.0:
664; RV32IF-NEXT:    feq.s a0, fa0, fa0
665; RV32IF-NEXT:    bnez a0, .LBB14_2
666; RV32IF-NEXT:  # %bb.1:
667; RV32IF-NEXT:    li a0, 0
668; RV32IF-NEXT:    ret
669; RV32IF-NEXT:  .LBB14_2:
670; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
671; RV32IF-NEXT:    ret
672;
673; RV64IF-LABEL: test_round_ui32:
674; RV64IF:       # %bb.0:
675; RV64IF-NEXT:    feq.s a0, fa0, fa0
676; RV64IF-NEXT:    bnez a0, .LBB14_2
677; RV64IF-NEXT:  # %bb.1:
678; RV64IF-NEXT:    li a0, 0
679; RV64IF-NEXT:    ret
680; RV64IF-NEXT:  .LBB14_2:
681; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
682; RV64IF-NEXT:    ret
683  %a = call float @llvm.round.f32(float %x)
684  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
685  ret i32 %b
686}
687
688define i64 @test_round_ui64(float %x) nounwind {
689; RV32IF-LABEL: test_round_ui64:
690; RV32IF:       # %bb.0:
691; RV32IF-NEXT:    addi sp, sp, -16
692; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
693; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
694; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
695; RV32IF-NEXT:    call roundf@plt
696; RV32IF-NEXT:    fmv.s fs0, fa0
697; RV32IF-NEXT:    fmv.w.x ft0, zero
698; RV32IF-NEXT:    fle.s s0, ft0, fa0
699; RV32IF-NEXT:    call __fixunssfdi@plt
700; RV32IF-NEXT:    mv a3, a0
701; RV32IF-NEXT:    bnez s0, .LBB15_2
702; RV32IF-NEXT:  # %bb.1:
703; RV32IF-NEXT:    li a3, 0
704; RV32IF-NEXT:  .LBB15_2:
705; RV32IF-NEXT:    lui a0, %hi(.LCPI15_0)
706; RV32IF-NEXT:    flw ft0, %lo(.LCPI15_0)(a0)
707; RV32IF-NEXT:    flt.s a4, ft0, fs0
708; RV32IF-NEXT:    li a2, -1
709; RV32IF-NEXT:    li a0, -1
710; RV32IF-NEXT:    beqz a4, .LBB15_7
711; RV32IF-NEXT:  # %bb.3:
712; RV32IF-NEXT:    beqz s0, .LBB15_8
713; RV32IF-NEXT:  .LBB15_4:
714; RV32IF-NEXT:    bnez a4, .LBB15_6
715; RV32IF-NEXT:  .LBB15_5:
716; RV32IF-NEXT:    mv a2, a1
717; RV32IF-NEXT:  .LBB15_6:
718; RV32IF-NEXT:    mv a1, a2
719; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
720; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
721; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
722; RV32IF-NEXT:    addi sp, sp, 16
723; RV32IF-NEXT:    ret
724; RV32IF-NEXT:  .LBB15_7:
725; RV32IF-NEXT:    mv a0, a3
726; RV32IF-NEXT:    bnez s0, .LBB15_4
727; RV32IF-NEXT:  .LBB15_8:
728; RV32IF-NEXT:    li a1, 0
729; RV32IF-NEXT:    beqz a4, .LBB15_5
730; RV32IF-NEXT:    j .LBB15_6
731;
732; RV64IF-LABEL: test_round_ui64:
733; RV64IF:       # %bb.0:
734; RV64IF-NEXT:    feq.s a0, fa0, fa0
735; RV64IF-NEXT:    bnez a0, .LBB15_2
736; RV64IF-NEXT:  # %bb.1:
737; RV64IF-NEXT:    li a0, 0
738; RV64IF-NEXT:    ret
739; RV64IF-NEXT:  .LBB15_2:
740; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
741; RV64IF-NEXT:    ret
742  %a = call float @llvm.round.f32(float %x)
743  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
744  ret i64 %b
745}
746
747define signext i32 @test_roundeven_si32(float %x) {
748; RV32IF-LABEL: test_roundeven_si32:
749; RV32IF:       # %bb.0:
750; RV32IF-NEXT:    feq.s a0, fa0, fa0
751; RV32IF-NEXT:    bnez a0, .LBB16_2
752; RV32IF-NEXT:  # %bb.1:
753; RV32IF-NEXT:    li a0, 0
754; RV32IF-NEXT:    ret
755; RV32IF-NEXT:  .LBB16_2:
756; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
757; RV32IF-NEXT:    ret
758;
759; RV64IF-LABEL: test_roundeven_si32:
760; RV64IF:       # %bb.0:
761; RV64IF-NEXT:    feq.s a0, fa0, fa0
762; RV64IF-NEXT:    bnez a0, .LBB16_2
763; RV64IF-NEXT:  # %bb.1:
764; RV64IF-NEXT:    li a0, 0
765; RV64IF-NEXT:    ret
766; RV64IF-NEXT:  .LBB16_2:
767; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
768; RV64IF-NEXT:    ret
769  %a = call float @llvm.roundeven.f32(float %x)
770  %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
771  ret i32 %b
772}
773
774define i64 @test_roundeven_si64(float %x) nounwind {
775; RV32IF-LABEL: test_roundeven_si64:
776; RV32IF:       # %bb.0:
777; RV32IF-NEXT:    addi sp, sp, -16
778; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
779; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
780; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
781; RV32IF-NEXT:    call roundevenf@plt
782; RV32IF-NEXT:    lui a0, %hi(.LCPI17_0)
783; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_0)(a0)
784; RV32IF-NEXT:    fmv.s fs0, fa0
785; RV32IF-NEXT:    fle.s s0, ft0, fa0
786; RV32IF-NEXT:    call __fixsfdi@plt
787; RV32IF-NEXT:    mv a2, a0
788; RV32IF-NEXT:    bnez s0, .LBB17_2
789; RV32IF-NEXT:  # %bb.1:
790; RV32IF-NEXT:    li a2, 0
791; RV32IF-NEXT:  .LBB17_2:
792; RV32IF-NEXT:    lui a0, %hi(.LCPI17_1)
793; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_1)(a0)
794; RV32IF-NEXT:    flt.s a3, ft0, fs0
795; RV32IF-NEXT:    li a0, -1
796; RV32IF-NEXT:    beqz a3, .LBB17_9
797; RV32IF-NEXT:  # %bb.3:
798; RV32IF-NEXT:    feq.s a2, fs0, fs0
799; RV32IF-NEXT:    beqz a2, .LBB17_10
800; RV32IF-NEXT:  .LBB17_4:
801; RV32IF-NEXT:    lui a4, 524288
802; RV32IF-NEXT:    beqz s0, .LBB17_11
803; RV32IF-NEXT:  .LBB17_5:
804; RV32IF-NEXT:    bnez a3, .LBB17_12
805; RV32IF-NEXT:  .LBB17_6:
806; RV32IF-NEXT:    bnez a2, .LBB17_8
807; RV32IF-NEXT:  .LBB17_7:
808; RV32IF-NEXT:    li a1, 0
809; RV32IF-NEXT:  .LBB17_8:
810; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
811; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
812; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
813; RV32IF-NEXT:    addi sp, sp, 16
814; RV32IF-NEXT:    ret
815; RV32IF-NEXT:  .LBB17_9:
816; RV32IF-NEXT:    mv a0, a2
817; RV32IF-NEXT:    feq.s a2, fs0, fs0
818; RV32IF-NEXT:    bnez a2, .LBB17_4
819; RV32IF-NEXT:  .LBB17_10:
820; RV32IF-NEXT:    li a0, 0
821; RV32IF-NEXT:    lui a4, 524288
822; RV32IF-NEXT:    bnez s0, .LBB17_5
823; RV32IF-NEXT:  .LBB17_11:
824; RV32IF-NEXT:    lui a1, 524288
825; RV32IF-NEXT:    beqz a3, .LBB17_6
826; RV32IF-NEXT:  .LBB17_12:
827; RV32IF-NEXT:    addi a1, a4, -1
828; RV32IF-NEXT:    beqz a2, .LBB17_7
829; RV32IF-NEXT:    j .LBB17_8
830;
831; RV64IF-LABEL: test_roundeven_si64:
832; RV64IF:       # %bb.0:
833; RV64IF-NEXT:    feq.s a0, fa0, fa0
834; RV64IF-NEXT:    bnez a0, .LBB17_2
835; RV64IF-NEXT:  # %bb.1:
836; RV64IF-NEXT:    li a0, 0
837; RV64IF-NEXT:    ret
838; RV64IF-NEXT:  .LBB17_2:
839; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
840; RV64IF-NEXT:    ret
841  %a = call float @llvm.roundeven.f32(float %x)
842  %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
843  ret i64 %b
844}
845
846define signext i32 @test_roundeven_ui32(float %x) {
847; RV32IF-LABEL: test_roundeven_ui32:
848; RV32IF:       # %bb.0:
849; RV32IF-NEXT:    feq.s a0, fa0, fa0
850; RV32IF-NEXT:    bnez a0, .LBB18_2
851; RV32IF-NEXT:  # %bb.1:
852; RV32IF-NEXT:    li a0, 0
853; RV32IF-NEXT:    ret
854; RV32IF-NEXT:  .LBB18_2:
855; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
856; RV32IF-NEXT:    ret
857;
858; RV64IF-LABEL: test_roundeven_ui32:
859; RV64IF:       # %bb.0:
860; RV64IF-NEXT:    feq.s a0, fa0, fa0
861; RV64IF-NEXT:    bnez a0, .LBB18_2
862; RV64IF-NEXT:  # %bb.1:
863; RV64IF-NEXT:    li a0, 0
864; RV64IF-NEXT:    ret
865; RV64IF-NEXT:  .LBB18_2:
866; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
867; RV64IF-NEXT:    ret
868  %a = call float @llvm.roundeven.f32(float %x)
869  %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
870  ret i32 %b
871}
872
873define i64 @test_roundeven_ui64(float %x) nounwind {
874; RV32IF-LABEL: test_roundeven_ui64:
875; RV32IF:       # %bb.0:
876; RV32IF-NEXT:    addi sp, sp, -16
877; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
878; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
879; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
880; RV32IF-NEXT:    call roundevenf@plt
881; RV32IF-NEXT:    fmv.s fs0, fa0
882; RV32IF-NEXT:    fmv.w.x ft0, zero
883; RV32IF-NEXT:    fle.s s0, ft0, fa0
884; RV32IF-NEXT:    call __fixunssfdi@plt
885; RV32IF-NEXT:    mv a3, a0
886; RV32IF-NEXT:    bnez s0, .LBB19_2
887; RV32IF-NEXT:  # %bb.1:
888; RV32IF-NEXT:    li a3, 0
889; RV32IF-NEXT:  .LBB19_2:
890; RV32IF-NEXT:    lui a0, %hi(.LCPI19_0)
891; RV32IF-NEXT:    flw ft0, %lo(.LCPI19_0)(a0)
892; RV32IF-NEXT:    flt.s a4, ft0, fs0
893; RV32IF-NEXT:    li a2, -1
894; RV32IF-NEXT:    li a0, -1
895; RV32IF-NEXT:    beqz a4, .LBB19_7
896; RV32IF-NEXT:  # %bb.3:
897; RV32IF-NEXT:    beqz s0, .LBB19_8
898; RV32IF-NEXT:  .LBB19_4:
899; RV32IF-NEXT:    bnez a4, .LBB19_6
900; RV32IF-NEXT:  .LBB19_5:
901; RV32IF-NEXT:    mv a2, a1
902; RV32IF-NEXT:  .LBB19_6:
903; RV32IF-NEXT:    mv a1, a2
904; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
905; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
906; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
907; RV32IF-NEXT:    addi sp, sp, 16
908; RV32IF-NEXT:    ret
909; RV32IF-NEXT:  .LBB19_7:
910; RV32IF-NEXT:    mv a0, a3
911; RV32IF-NEXT:    bnez s0, .LBB19_4
912; RV32IF-NEXT:  .LBB19_8:
913; RV32IF-NEXT:    li a1, 0
914; RV32IF-NEXT:    beqz a4, .LBB19_5
915; RV32IF-NEXT:    j .LBB19_6
916;
917; RV64IF-LABEL: test_roundeven_ui64:
918; RV64IF:       # %bb.0:
919; RV64IF-NEXT:    feq.s a0, fa0, fa0
920; RV64IF-NEXT:    bnez a0, .LBB19_2
921; RV64IF-NEXT:  # %bb.1:
922; RV64IF-NEXT:    li a0, 0
923; RV64IF-NEXT:    ret
924; RV64IF-NEXT:  .LBB19_2:
925; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
926; RV64IF-NEXT:    ret
927  %a = call float @llvm.roundeven.f32(float %x)
928  %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
929  ret i64 %b
930}
931
932declare float @llvm.floor.f32(float)
933declare float @llvm.ceil.f32(float)
934declare float @llvm.trunc.f32(float)
935declare float @llvm.round.f32(float)
936declare float @llvm.roundeven.f32(float)
937declare i32 @llvm.fptosi.sat.i32.f32(float)
938declare i64 @llvm.fptosi.sat.i64.f32(float)
939declare i32 @llvm.fptoui.sat.i32.f32(float)
940declare i64 @llvm.fptoui.sat.i64.f32(float)
941