1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV32I %s
8; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64I %s
10
11define float @frem_f32(float %a, float %b) nounwind {
12; RV32IF-LABEL: frem_f32:
13; RV32IF:       # %bb.0:
14; RV32IF-NEXT:    addi sp, sp, -16
15; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
16; RV32IF-NEXT:    call fmodf@plt
17; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
18; RV32IF-NEXT:    addi sp, sp, 16
19; RV32IF-NEXT:    ret
20;
21; RV64IF-LABEL: frem_f32:
22; RV64IF:       # %bb.0:
23; RV64IF-NEXT:    addi sp, sp, -16
24; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
25; RV64IF-NEXT:    call fmodf@plt
26; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
27; RV64IF-NEXT:    addi sp, sp, 16
28; RV64IF-NEXT:    ret
29;
30; RV32I-LABEL: frem_f32:
31; RV32I:       # %bb.0:
32; RV32I-NEXT:    addi sp, sp, -16
33; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
34; RV32I-NEXT:    call fmodf@plt
35; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
36; RV32I-NEXT:    addi sp, sp, 16
37; RV32I-NEXT:    ret
38;
39; RV64I-LABEL: frem_f32:
40; RV64I:       # %bb.0:
41; RV64I-NEXT:    addi sp, sp, -16
42; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
43; RV64I-NEXT:    call fmodf@plt
44; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
45; RV64I-NEXT:    addi sp, sp, 16
46; RV64I-NEXT:    ret
47  %1 = frem float %a, %b
48  ret float %1
49}
50