1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV32I %s
8; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64I %s
10
11define i32 @fcvt_w_s(float %a) nounwind {
12; RV32IF-LABEL: fcvt_w_s:
13; RV32IF:       # %bb.0:
14; RV32IF-NEXT:    fmv.w.x ft0, a0
15; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
16; RV32IF-NEXT:    ret
17;
18; RV64IF-LABEL: fcvt_w_s:
19; RV64IF:       # %bb.0:
20; RV64IF-NEXT:    fmv.w.x ft0, a0
21; RV64IF-NEXT:    fcvt.w.s a0, ft0, rtz
22; RV64IF-NEXT:    ret
23;
24; RV32I-LABEL: fcvt_w_s:
25; RV32I:       # %bb.0:
26; RV32I-NEXT:    addi sp, sp, -16
27; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
28; RV32I-NEXT:    call __fixsfsi@plt
29; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
30; RV32I-NEXT:    addi sp, sp, 16
31; RV32I-NEXT:    ret
32;
33; RV64I-LABEL: fcvt_w_s:
34; RV64I:       # %bb.0:
35; RV64I-NEXT:    addi sp, sp, -16
36; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
37; RV64I-NEXT:    call __fixsfsi@plt
38; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
39; RV64I-NEXT:    addi sp, sp, 16
40; RV64I-NEXT:    ret
41  %1 = fptosi float %a to i32
42  ret i32 %1
43}
44
45define i32 @fcvt_w_s_sat(float %a) nounwind {
46; RV32IF-LABEL: fcvt_w_s_sat:
47; RV32IF:       # %bb.0: # %start
48; RV32IF-NEXT:    fmv.w.x ft0, a0
49; RV32IF-NEXT:    feq.s a0, ft0, ft0
50; RV32IF-NEXT:    bnez a0, .LBB1_2
51; RV32IF-NEXT:  # %bb.1: # %start
52; RV32IF-NEXT:    li a0, 0
53; RV32IF-NEXT:    ret
54; RV32IF-NEXT:  .LBB1_2:
55; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
56; RV32IF-NEXT:    ret
57;
58; RV64IF-LABEL: fcvt_w_s_sat:
59; RV64IF:       # %bb.0: # %start
60; RV64IF-NEXT:    fmv.w.x ft0, a0
61; RV64IF-NEXT:    feq.s a0, ft0, ft0
62; RV64IF-NEXT:    bnez a0, .LBB1_2
63; RV64IF-NEXT:  # %bb.1: # %start
64; RV64IF-NEXT:    li a0, 0
65; RV64IF-NEXT:    ret
66; RV64IF-NEXT:  .LBB1_2:
67; RV64IF-NEXT:    fcvt.w.s a0, ft0, rtz
68; RV64IF-NEXT:    ret
69;
70; RV32I-LABEL: fcvt_w_s_sat:
71; RV32I:       # %bb.0: # %start
72; RV32I-NEXT:    addi sp, sp, -32
73; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
74; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
75; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
76; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
77; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
78; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
79; RV32I-NEXT:    mv s0, a0
80; RV32I-NEXT:    lui a1, 847872
81; RV32I-NEXT:    call __gesf2@plt
82; RV32I-NEXT:    mv s2, a0
83; RV32I-NEXT:    mv a0, s0
84; RV32I-NEXT:    call __fixsfsi@plt
85; RV32I-NEXT:    li s1, 0
86; RV32I-NEXT:    lui s4, 524288
87; RV32I-NEXT:    lui s3, 524288
88; RV32I-NEXT:    bltz s2, .LBB1_2
89; RV32I-NEXT:  # %bb.1: # %start
90; RV32I-NEXT:    mv s3, a0
91; RV32I-NEXT:  .LBB1_2: # %start
92; RV32I-NEXT:    lui a0, 323584
93; RV32I-NEXT:    addi a1, a0, -1
94; RV32I-NEXT:    mv a0, s0
95; RV32I-NEXT:    call __gtsf2@plt
96; RV32I-NEXT:    bge s1, a0, .LBB1_4
97; RV32I-NEXT:  # %bb.3:
98; RV32I-NEXT:    addi s3, s4, -1
99; RV32I-NEXT:  .LBB1_4: # %start
100; RV32I-NEXT:    mv a0, s0
101; RV32I-NEXT:    mv a1, s0
102; RV32I-NEXT:    call __unordsf2@plt
103; RV32I-NEXT:    bne a0, s1, .LBB1_6
104; RV32I-NEXT:  # %bb.5: # %start
105; RV32I-NEXT:    mv s1, s3
106; RV32I-NEXT:  .LBB1_6: # %start
107; RV32I-NEXT:    mv a0, s1
108; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
109; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
110; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
111; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
112; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
113; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
114; RV32I-NEXT:    addi sp, sp, 32
115; RV32I-NEXT:    ret
116;
117; RV64I-LABEL: fcvt_w_s_sat:
118; RV64I:       # %bb.0: # %start
119; RV64I-NEXT:    addi sp, sp, -48
120; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
121; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
122; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
123; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
124; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
125; RV64I-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
126; RV64I-NEXT:    mv s0, a0
127; RV64I-NEXT:    lui a1, 847872
128; RV64I-NEXT:    call __gesf2@plt
129; RV64I-NEXT:    mv s2, a0
130; RV64I-NEXT:    mv a0, s0
131; RV64I-NEXT:    call __fixsfdi@plt
132; RV64I-NEXT:    li s1, 0
133; RV64I-NEXT:    lui s4, 524288
134; RV64I-NEXT:    lui s3, 524288
135; RV64I-NEXT:    bltz s2, .LBB1_2
136; RV64I-NEXT:  # %bb.1: # %start
137; RV64I-NEXT:    mv s3, a0
138; RV64I-NEXT:  .LBB1_2: # %start
139; RV64I-NEXT:    lui a0, 323584
140; RV64I-NEXT:    addiw a1, a0, -1
141; RV64I-NEXT:    mv a0, s0
142; RV64I-NEXT:    call __gtsf2@plt
143; RV64I-NEXT:    bge s1, a0, .LBB1_4
144; RV64I-NEXT:  # %bb.3:
145; RV64I-NEXT:    addiw s3, s4, -1
146; RV64I-NEXT:  .LBB1_4: # %start
147; RV64I-NEXT:    mv a0, s0
148; RV64I-NEXT:    mv a1, s0
149; RV64I-NEXT:    call __unordsf2@plt
150; RV64I-NEXT:    bne a0, s1, .LBB1_6
151; RV64I-NEXT:  # %bb.5: # %start
152; RV64I-NEXT:    mv s1, s3
153; RV64I-NEXT:  .LBB1_6: # %start
154; RV64I-NEXT:    mv a0, s1
155; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
156; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
157; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
158; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
159; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
160; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
161; RV64I-NEXT:    addi sp, sp, 48
162; RV64I-NEXT:    ret
163start:
164  %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
165  ret i32 %0
166}
167declare i32 @llvm.fptosi.sat.i32.f32(float)
168
169define i32 @fcvt_wu_s(float %a) nounwind {
170; RV32IF-LABEL: fcvt_wu_s:
171; RV32IF:       # %bb.0:
172; RV32IF-NEXT:    fmv.w.x ft0, a0
173; RV32IF-NEXT:    fcvt.wu.s a0, ft0, rtz
174; RV32IF-NEXT:    ret
175;
176; RV64IF-LABEL: fcvt_wu_s:
177; RV64IF:       # %bb.0:
178; RV64IF-NEXT:    fmv.w.x ft0, a0
179; RV64IF-NEXT:    fcvt.wu.s a0, ft0, rtz
180; RV64IF-NEXT:    ret
181;
182; RV32I-LABEL: fcvt_wu_s:
183; RV32I:       # %bb.0:
184; RV32I-NEXT:    addi sp, sp, -16
185; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
186; RV32I-NEXT:    call __fixunssfsi@plt
187; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
188; RV32I-NEXT:    addi sp, sp, 16
189; RV32I-NEXT:    ret
190;
191; RV64I-LABEL: fcvt_wu_s:
192; RV64I:       # %bb.0:
193; RV64I-NEXT:    addi sp, sp, -16
194; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
195; RV64I-NEXT:    call __fixunssfsi@plt
196; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
197; RV64I-NEXT:    addi sp, sp, 16
198; RV64I-NEXT:    ret
199  %1 = fptoui float %a to i32
200  ret i32 %1
201}
202
203; Test where the fptoui has multiple uses, one of which causes a sext to be
204; inserted on RV64.
205define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
206; RV32IF-LABEL: fcvt_wu_s_multiple_use:
207; RV32IF:       # %bb.0:
208; RV32IF-NEXT:    fmv.w.x ft0, a0
209; RV32IF-NEXT:    fcvt.wu.s a1, ft0, rtz
210; RV32IF-NEXT:    li a0, 1
211; RV32IF-NEXT:    beqz a1, .LBB3_2
212; RV32IF-NEXT:  # %bb.1:
213; RV32IF-NEXT:    mv a0, a1
214; RV32IF-NEXT:  .LBB3_2:
215; RV32IF-NEXT:    ret
216;
217; RV64IF-LABEL: fcvt_wu_s_multiple_use:
218; RV64IF:       # %bb.0:
219; RV64IF-NEXT:    fmv.w.x ft0, a0
220; RV64IF-NEXT:    fcvt.wu.s a1, ft0, rtz
221; RV64IF-NEXT:    li a0, 1
222; RV64IF-NEXT:    beqz a1, .LBB3_2
223; RV64IF-NEXT:  # %bb.1:
224; RV64IF-NEXT:    mv a0, a1
225; RV64IF-NEXT:  .LBB3_2:
226; RV64IF-NEXT:    ret
227;
228; RV32I-LABEL: fcvt_wu_s_multiple_use:
229; RV32I:       # %bb.0:
230; RV32I-NEXT:    addi sp, sp, -16
231; RV32I-NEXT:    .cfi_def_cfa_offset 16
232; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
233; RV32I-NEXT:    .cfi_offset ra, -4
234; RV32I-NEXT:    call __fixunssfsi@plt
235; RV32I-NEXT:    mv a1, a0
236; RV32I-NEXT:    li a0, 1
237; RV32I-NEXT:    beqz a1, .LBB3_2
238; RV32I-NEXT:  # %bb.1:
239; RV32I-NEXT:    mv a0, a1
240; RV32I-NEXT:  .LBB3_2:
241; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
242; RV32I-NEXT:    addi sp, sp, 16
243; RV32I-NEXT:    ret
244;
245; RV64I-LABEL: fcvt_wu_s_multiple_use:
246; RV64I:       # %bb.0:
247; RV64I-NEXT:    addi sp, sp, -16
248; RV64I-NEXT:    .cfi_def_cfa_offset 16
249; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
250; RV64I-NEXT:    .cfi_offset ra, -8
251; RV64I-NEXT:    call __fixunssfsi@plt
252; RV64I-NEXT:    mv a1, a0
253; RV64I-NEXT:    li a0, 1
254; RV64I-NEXT:    beqz a1, .LBB3_2
255; RV64I-NEXT:  # %bb.1:
256; RV64I-NEXT:    mv a0, a1
257; RV64I-NEXT:  .LBB3_2:
258; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
259; RV64I-NEXT:    addi sp, sp, 16
260; RV64I-NEXT:    ret
261  %a = fptoui float %x to i32
262  %b = icmp eq i32 %a, 0
263  %c = select i1 %b, i32 1, i32 %a
264  ret i32 %c
265}
266
267define i32 @fcvt_wu_s_sat(float %a) nounwind {
268; RV32IF-LABEL: fcvt_wu_s_sat:
269; RV32IF:       # %bb.0: # %start
270; RV32IF-NEXT:    fmv.w.x ft0, a0
271; RV32IF-NEXT:    feq.s a0, ft0, ft0
272; RV32IF-NEXT:    bnez a0, .LBB4_2
273; RV32IF-NEXT:  # %bb.1: # %start
274; RV32IF-NEXT:    li a0, 0
275; RV32IF-NEXT:    ret
276; RV32IF-NEXT:  .LBB4_2:
277; RV32IF-NEXT:    fcvt.wu.s a0, ft0, rtz
278; RV32IF-NEXT:    ret
279;
280; RV64IF-LABEL: fcvt_wu_s_sat:
281; RV64IF:       # %bb.0: # %start
282; RV64IF-NEXT:    fmv.w.x ft0, a0
283; RV64IF-NEXT:    feq.s a0, ft0, ft0
284; RV64IF-NEXT:    bnez a0, .LBB4_2
285; RV64IF-NEXT:  # %bb.1: # %start
286; RV64IF-NEXT:    li a0, 0
287; RV64IF-NEXT:    ret
288; RV64IF-NEXT:  .LBB4_2:
289; RV64IF-NEXT:    fcvt.wu.s a0, ft0, rtz
290; RV64IF-NEXT:    ret
291;
292; RV32I-LABEL: fcvt_wu_s_sat:
293; RV32I:       # %bb.0: # %start
294; RV32I-NEXT:    addi sp, sp, -16
295; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
296; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
297; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
298; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
299; RV32I-NEXT:    mv s0, a0
300; RV32I-NEXT:    li a1, 0
301; RV32I-NEXT:    call __gesf2@plt
302; RV32I-NEXT:    mv s1, a0
303; RV32I-NEXT:    mv a0, s0
304; RV32I-NEXT:    call __fixunssfsi@plt
305; RV32I-NEXT:    li s2, 0
306; RV32I-NEXT:    bltz s1, .LBB4_2
307; RV32I-NEXT:  # %bb.1: # %start
308; RV32I-NEXT:    mv s2, a0
309; RV32I-NEXT:  .LBB4_2: # %start
310; RV32I-NEXT:    lui a0, 325632
311; RV32I-NEXT:    addi a1, a0, -1
312; RV32I-NEXT:    mv a0, s0
313; RV32I-NEXT:    call __gtsf2@plt
314; RV32I-NEXT:    mv a1, a0
315; RV32I-NEXT:    li a0, -1
316; RV32I-NEXT:    bgtz a1, .LBB4_4
317; RV32I-NEXT:  # %bb.3: # %start
318; RV32I-NEXT:    mv a0, s2
319; RV32I-NEXT:  .LBB4_4: # %start
320; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
321; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
322; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
323; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
324; RV32I-NEXT:    addi sp, sp, 16
325; RV32I-NEXT:    ret
326;
327; RV64I-LABEL: fcvt_wu_s_sat:
328; RV64I:       # %bb.0: # %start
329; RV64I-NEXT:    addi sp, sp, -32
330; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
331; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
332; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
333; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
334; RV64I-NEXT:    mv s0, a0
335; RV64I-NEXT:    li a1, 0
336; RV64I-NEXT:    call __gesf2@plt
337; RV64I-NEXT:    mv s2, a0
338; RV64I-NEXT:    mv a0, s0
339; RV64I-NEXT:    call __fixunssfdi@plt
340; RV64I-NEXT:    li s1, 0
341; RV64I-NEXT:    bltz s2, .LBB4_2
342; RV64I-NEXT:  # %bb.1: # %start
343; RV64I-NEXT:    mv s1, a0
344; RV64I-NEXT:  .LBB4_2: # %start
345; RV64I-NEXT:    lui a0, 325632
346; RV64I-NEXT:    addiw a1, a0, -1
347; RV64I-NEXT:    mv a0, s0
348; RV64I-NEXT:    call __gtsf2@plt
349; RV64I-NEXT:    blez a0, .LBB4_4
350; RV64I-NEXT:  # %bb.3:
351; RV64I-NEXT:    li a0, -1
352; RV64I-NEXT:    srli s1, a0, 32
353; RV64I-NEXT:  .LBB4_4: # %start
354; RV64I-NEXT:    mv a0, s1
355; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
356; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
357; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
358; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
359; RV64I-NEXT:    addi sp, sp, 32
360; RV64I-NEXT:    ret
361start:
362  %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
363  ret i32 %0
364}
365declare i32 @llvm.fptoui.sat.i32.f32(float)
366
367define i32 @fmv_x_w(float %a, float %b) nounwind {
368; RV32IF-LABEL: fmv_x_w:
369; RV32IF:       # %bb.0:
370; RV32IF-NEXT:    fmv.w.x ft0, a1
371; RV32IF-NEXT:    fmv.w.x ft1, a0
372; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
373; RV32IF-NEXT:    fmv.x.w a0, ft0
374; RV32IF-NEXT:    ret
375;
376; RV64IF-LABEL: fmv_x_w:
377; RV64IF:       # %bb.0:
378; RV64IF-NEXT:    fmv.w.x ft0, a1
379; RV64IF-NEXT:    fmv.w.x ft1, a0
380; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
381; RV64IF-NEXT:    fmv.x.w a0, ft0
382; RV64IF-NEXT:    ret
383;
384; RV32I-LABEL: fmv_x_w:
385; RV32I:       # %bb.0:
386; RV32I-NEXT:    addi sp, sp, -16
387; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
388; RV32I-NEXT:    call __addsf3@plt
389; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
390; RV32I-NEXT:    addi sp, sp, 16
391; RV32I-NEXT:    ret
392;
393; RV64I-LABEL: fmv_x_w:
394; RV64I:       # %bb.0:
395; RV64I-NEXT:    addi sp, sp, -16
396; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
397; RV64I-NEXT:    call __addsf3@plt
398; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
399; RV64I-NEXT:    addi sp, sp, 16
400; RV64I-NEXT:    ret
401; Ensure fmv.x.w is generated even for a soft float calling convention
402  %1 = fadd float %a, %b
403  %2 = bitcast float %1 to i32
404  ret i32 %2
405}
406
407define float @fcvt_s_w(i32 %a) nounwind {
408; RV32IF-LABEL: fcvt_s_w:
409; RV32IF:       # %bb.0:
410; RV32IF-NEXT:    fcvt.s.w ft0, a0
411; RV32IF-NEXT:    fmv.x.w a0, ft0
412; RV32IF-NEXT:    ret
413;
414; RV64IF-LABEL: fcvt_s_w:
415; RV64IF:       # %bb.0:
416; RV64IF-NEXT:    fcvt.s.w ft0, a0
417; RV64IF-NEXT:    fmv.x.w a0, ft0
418; RV64IF-NEXT:    ret
419;
420; RV32I-LABEL: fcvt_s_w:
421; RV32I:       # %bb.0:
422; RV32I-NEXT:    addi sp, sp, -16
423; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
424; RV32I-NEXT:    call __floatsisf@plt
425; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
426; RV32I-NEXT:    addi sp, sp, 16
427; RV32I-NEXT:    ret
428;
429; RV64I-LABEL: fcvt_s_w:
430; RV64I:       # %bb.0:
431; RV64I-NEXT:    addi sp, sp, -16
432; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
433; RV64I-NEXT:    sext.w a0, a0
434; RV64I-NEXT:    call __floatsisf@plt
435; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
436; RV64I-NEXT:    addi sp, sp, 16
437; RV64I-NEXT:    ret
438  %1 = sitofp i32 %a to float
439  ret float %1
440}
441
442define float @fcvt_s_w_load(i32* %p) nounwind {
443; RV32IF-LABEL: fcvt_s_w_load:
444; RV32IF:       # %bb.0:
445; RV32IF-NEXT:    lw a0, 0(a0)
446; RV32IF-NEXT:    fcvt.s.w ft0, a0
447; RV32IF-NEXT:    fmv.x.w a0, ft0
448; RV32IF-NEXT:    ret
449;
450; RV64IF-LABEL: fcvt_s_w_load:
451; RV64IF:       # %bb.0:
452; RV64IF-NEXT:    lw a0, 0(a0)
453; RV64IF-NEXT:    fcvt.s.w ft0, a0
454; RV64IF-NEXT:    fmv.x.w a0, ft0
455; RV64IF-NEXT:    ret
456;
457; RV32I-LABEL: fcvt_s_w_load:
458; RV32I:       # %bb.0:
459; RV32I-NEXT:    addi sp, sp, -16
460; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
461; RV32I-NEXT:    lw a0, 0(a0)
462; RV32I-NEXT:    call __floatsisf@plt
463; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
464; RV32I-NEXT:    addi sp, sp, 16
465; RV32I-NEXT:    ret
466;
467; RV64I-LABEL: fcvt_s_w_load:
468; RV64I:       # %bb.0:
469; RV64I-NEXT:    addi sp, sp, -16
470; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
471; RV64I-NEXT:    lw a0, 0(a0)
472; RV64I-NEXT:    call __floatsisf@plt
473; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
474; RV64I-NEXT:    addi sp, sp, 16
475; RV64I-NEXT:    ret
476  %a = load i32, i32* %p
477  %1 = sitofp i32 %a to float
478  ret float %1
479}
480
481define float @fcvt_s_wu(i32 %a) nounwind {
482; RV32IF-LABEL: fcvt_s_wu:
483; RV32IF:       # %bb.0:
484; RV32IF-NEXT:    fcvt.s.wu ft0, a0
485; RV32IF-NEXT:    fmv.x.w a0, ft0
486; RV32IF-NEXT:    ret
487;
488; RV64IF-LABEL: fcvt_s_wu:
489; RV64IF:       # %bb.0:
490; RV64IF-NEXT:    fcvt.s.wu ft0, a0
491; RV64IF-NEXT:    fmv.x.w a0, ft0
492; RV64IF-NEXT:    ret
493;
494; RV32I-LABEL: fcvt_s_wu:
495; RV32I:       # %bb.0:
496; RV32I-NEXT:    addi sp, sp, -16
497; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
498; RV32I-NEXT:    call __floatunsisf@plt
499; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
500; RV32I-NEXT:    addi sp, sp, 16
501; RV32I-NEXT:    ret
502;
503; RV64I-LABEL: fcvt_s_wu:
504; RV64I:       # %bb.0:
505; RV64I-NEXT:    addi sp, sp, -16
506; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
507; RV64I-NEXT:    sext.w a0, a0
508; RV64I-NEXT:    call __floatunsisf@plt
509; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
510; RV64I-NEXT:    addi sp, sp, 16
511; RV64I-NEXT:    ret
512  %1 = uitofp i32 %a to float
513  ret float %1
514}
515
516define float @fcvt_s_wu_load(i32* %p) nounwind {
517; RV32IF-LABEL: fcvt_s_wu_load:
518; RV32IF:       # %bb.0:
519; RV32IF-NEXT:    lw a0, 0(a0)
520; RV32IF-NEXT:    fcvt.s.wu ft0, a0
521; RV32IF-NEXT:    fmv.x.w a0, ft0
522; RV32IF-NEXT:    ret
523;
524; RV64IF-LABEL: fcvt_s_wu_load:
525; RV64IF:       # %bb.0:
526; RV64IF-NEXT:    lwu a0, 0(a0)
527; RV64IF-NEXT:    fcvt.s.wu ft0, a0
528; RV64IF-NEXT:    fmv.x.w a0, ft0
529; RV64IF-NEXT:    ret
530;
531; RV32I-LABEL: fcvt_s_wu_load:
532; RV32I:       # %bb.0:
533; RV32I-NEXT:    addi sp, sp, -16
534; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
535; RV32I-NEXT:    lw a0, 0(a0)
536; RV32I-NEXT:    call __floatunsisf@plt
537; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
538; RV32I-NEXT:    addi sp, sp, 16
539; RV32I-NEXT:    ret
540;
541; RV64I-LABEL: fcvt_s_wu_load:
542; RV64I:       # %bb.0:
543; RV64I-NEXT:    addi sp, sp, -16
544; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
545; RV64I-NEXT:    lw a0, 0(a0)
546; RV64I-NEXT:    call __floatunsisf@plt
547; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
548; RV64I-NEXT:    addi sp, sp, 16
549; RV64I-NEXT:    ret
550  %a = load i32, i32* %p
551  %1 = uitofp i32 %a to float
552  ret float %1
553}
554
555define float @fmv_w_x(i32 %a, i32 %b) nounwind {
556; RV32IF-LABEL: fmv_w_x:
557; RV32IF:       # %bb.0:
558; RV32IF-NEXT:    fmv.w.x ft0, a0
559; RV32IF-NEXT:    fmv.w.x ft1, a1
560; RV32IF-NEXT:    fadd.s ft0, ft0, ft1
561; RV32IF-NEXT:    fmv.x.w a0, ft0
562; RV32IF-NEXT:    ret
563;
564; RV64IF-LABEL: fmv_w_x:
565; RV64IF:       # %bb.0:
566; RV64IF-NEXT:    fmv.w.x ft0, a0
567; RV64IF-NEXT:    fmv.w.x ft1, a1
568; RV64IF-NEXT:    fadd.s ft0, ft0, ft1
569; RV64IF-NEXT:    fmv.x.w a0, ft0
570; RV64IF-NEXT:    ret
571;
572; RV32I-LABEL: fmv_w_x:
573; RV32I:       # %bb.0:
574; RV32I-NEXT:    addi sp, sp, -16
575; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
576; RV32I-NEXT:    call __addsf3@plt
577; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
578; RV32I-NEXT:    addi sp, sp, 16
579; RV32I-NEXT:    ret
580;
581; RV64I-LABEL: fmv_w_x:
582; RV64I:       # %bb.0:
583; RV64I-NEXT:    addi sp, sp, -16
584; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
585; RV64I-NEXT:    call __addsf3@plt
586; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
587; RV64I-NEXT:    addi sp, sp, 16
588; RV64I-NEXT:    ret
589; Ensure fmv.w.x is generated even for a soft float calling convention
590  %1 = bitcast i32 %a to float
591  %2 = bitcast i32 %b to float
592  %3 = fadd float %1, %2
593  ret float %3
594}
595
596define i64 @fcvt_l_s(float %a) nounwind {
597; RV32IF-LABEL: fcvt_l_s:
598; RV32IF:       # %bb.0:
599; RV32IF-NEXT:    addi sp, sp, -16
600; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
601; RV32IF-NEXT:    call __fixsfdi@plt
602; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
603; RV32IF-NEXT:    addi sp, sp, 16
604; RV32IF-NEXT:    ret
605;
606; RV64IF-LABEL: fcvt_l_s:
607; RV64IF:       # %bb.0:
608; RV64IF-NEXT:    fmv.w.x ft0, a0
609; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
610; RV64IF-NEXT:    ret
611;
612; RV32I-LABEL: fcvt_l_s:
613; RV32I:       # %bb.0:
614; RV32I-NEXT:    addi sp, sp, -16
615; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
616; RV32I-NEXT:    call __fixsfdi@plt
617; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
618; RV32I-NEXT:    addi sp, sp, 16
619; RV32I-NEXT:    ret
620;
621; RV64I-LABEL: fcvt_l_s:
622; RV64I:       # %bb.0:
623; RV64I-NEXT:    addi sp, sp, -16
624; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
625; RV64I-NEXT:    call __fixsfdi@plt
626; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
627; RV64I-NEXT:    addi sp, sp, 16
628; RV64I-NEXT:    ret
629  %1 = fptosi float %a to i64
630  ret i64 %1
631}
632
633define i64 @fcvt_l_s_sat(float %a) nounwind {
634; RV32IF-LABEL: fcvt_l_s_sat:
635; RV32IF:       # %bb.0: # %start
636; RV32IF-NEXT:    addi sp, sp, -16
637; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
638; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
639; RV32IF-NEXT:    lui a1, %hi(.LCPI12_0)
640; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_0)(a1)
641; RV32IF-NEXT:    fmv.w.x ft1, a0
642; RV32IF-NEXT:    fsw ft1, 4(sp) # 4-byte Folded Spill
643; RV32IF-NEXT:    fle.s s0, ft0, ft1
644; RV32IF-NEXT:    call __fixsfdi@plt
645; RV32IF-NEXT:    mv a2, a0
646; RV32IF-NEXT:    bnez s0, .LBB12_2
647; RV32IF-NEXT:  # %bb.1: # %start
648; RV32IF-NEXT:    li a2, 0
649; RV32IF-NEXT:  .LBB12_2: # %start
650; RV32IF-NEXT:    lui a0, %hi(.LCPI12_1)
651; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_1)(a0)
652; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
653; RV32IF-NEXT:    flt.s a3, ft0, ft1
654; RV32IF-NEXT:    fmv.s ft0, ft1
655; RV32IF-NEXT:    li a0, -1
656; RV32IF-NEXT:    beqz a3, .LBB12_9
657; RV32IF-NEXT:  # %bb.3: # %start
658; RV32IF-NEXT:    feq.s a2, ft0, ft0
659; RV32IF-NEXT:    beqz a2, .LBB12_10
660; RV32IF-NEXT:  .LBB12_4: # %start
661; RV32IF-NEXT:    lui a4, 524288
662; RV32IF-NEXT:    beqz s0, .LBB12_11
663; RV32IF-NEXT:  .LBB12_5: # %start
664; RV32IF-NEXT:    bnez a3, .LBB12_12
665; RV32IF-NEXT:  .LBB12_6: # %start
666; RV32IF-NEXT:    bnez a2, .LBB12_8
667; RV32IF-NEXT:  .LBB12_7: # %start
668; RV32IF-NEXT:    li a1, 0
669; RV32IF-NEXT:  .LBB12_8: # %start
670; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
671; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
672; RV32IF-NEXT:    addi sp, sp, 16
673; RV32IF-NEXT:    ret
674; RV32IF-NEXT:  .LBB12_9: # %start
675; RV32IF-NEXT:    mv a0, a2
676; RV32IF-NEXT:    feq.s a2, ft0, ft0
677; RV32IF-NEXT:    bnez a2, .LBB12_4
678; RV32IF-NEXT:  .LBB12_10: # %start
679; RV32IF-NEXT:    li a0, 0
680; RV32IF-NEXT:    lui a4, 524288
681; RV32IF-NEXT:    bnez s0, .LBB12_5
682; RV32IF-NEXT:  .LBB12_11: # %start
683; RV32IF-NEXT:    lui a1, 524288
684; RV32IF-NEXT:    beqz a3, .LBB12_6
685; RV32IF-NEXT:  .LBB12_12:
686; RV32IF-NEXT:    addi a1, a4, -1
687; RV32IF-NEXT:    beqz a2, .LBB12_7
688; RV32IF-NEXT:    j .LBB12_8
689;
690; RV64IF-LABEL: fcvt_l_s_sat:
691; RV64IF:       # %bb.0: # %start
692; RV64IF-NEXT:    fmv.w.x ft0, a0
693; RV64IF-NEXT:    feq.s a0, ft0, ft0
694; RV64IF-NEXT:    bnez a0, .LBB12_2
695; RV64IF-NEXT:  # %bb.1: # %start
696; RV64IF-NEXT:    li a0, 0
697; RV64IF-NEXT:    ret
698; RV64IF-NEXT:  .LBB12_2:
699; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
700; RV64IF-NEXT:    ret
701;
702; RV32I-LABEL: fcvt_l_s_sat:
703; RV32I:       # %bb.0: # %start
704; RV32I-NEXT:    addi sp, sp, -32
705; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
706; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
707; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
708; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
709; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
710; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
711; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
712; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
713; RV32I-NEXT:    mv s0, a0
714; RV32I-NEXT:    lui a1, 913408
715; RV32I-NEXT:    call __gesf2@plt
716; RV32I-NEXT:    mv s3, a0
717; RV32I-NEXT:    mv a0, s0
718; RV32I-NEXT:    call __fixsfdi@plt
719; RV32I-NEXT:    mv s2, a1
720; RV32I-NEXT:    li s1, 0
721; RV32I-NEXT:    li s5, 0
722; RV32I-NEXT:    bltz s3, .LBB12_2
723; RV32I-NEXT:  # %bb.1: # %start
724; RV32I-NEXT:    mv s5, a0
725; RV32I-NEXT:  .LBB12_2: # %start
726; RV32I-NEXT:    lui a0, 389120
727; RV32I-NEXT:    addi s4, a0, -1
728; RV32I-NEXT:    mv a0, s0
729; RV32I-NEXT:    mv a1, s4
730; RV32I-NEXT:    call __gtsf2@plt
731; RV32I-NEXT:    li s6, -1
732; RV32I-NEXT:    blt s1, a0, .LBB12_4
733; RV32I-NEXT:  # %bb.3: # %start
734; RV32I-NEXT:    mv s6, s5
735; RV32I-NEXT:  .LBB12_4: # %start
736; RV32I-NEXT:    mv a0, s0
737; RV32I-NEXT:    mv a1, s0
738; RV32I-NEXT:    call __unordsf2@plt
739; RV32I-NEXT:    mv s3, s1
740; RV32I-NEXT:    bne a0, s1, .LBB12_6
741; RV32I-NEXT:  # %bb.5: # %start
742; RV32I-NEXT:    mv s3, s6
743; RV32I-NEXT:  .LBB12_6: # %start
744; RV32I-NEXT:    lui a1, 913408
745; RV32I-NEXT:    mv a0, s0
746; RV32I-NEXT:    call __gesf2@plt
747; RV32I-NEXT:    lui s6, 524288
748; RV32I-NEXT:    lui s5, 524288
749; RV32I-NEXT:    blt a0, s1, .LBB12_8
750; RV32I-NEXT:  # %bb.7: # %start
751; RV32I-NEXT:    mv s5, s2
752; RV32I-NEXT:  .LBB12_8: # %start
753; RV32I-NEXT:    mv a0, s0
754; RV32I-NEXT:    mv a1, s4
755; RV32I-NEXT:    call __gtsf2@plt
756; RV32I-NEXT:    bge s1, a0, .LBB12_10
757; RV32I-NEXT:  # %bb.9:
758; RV32I-NEXT:    addi s5, s6, -1
759; RV32I-NEXT:  .LBB12_10: # %start
760; RV32I-NEXT:    mv a0, s0
761; RV32I-NEXT:    mv a1, s0
762; RV32I-NEXT:    call __unordsf2@plt
763; RV32I-NEXT:    bne a0, s1, .LBB12_12
764; RV32I-NEXT:  # %bb.11: # %start
765; RV32I-NEXT:    mv s1, s5
766; RV32I-NEXT:  .LBB12_12: # %start
767; RV32I-NEXT:    mv a0, s3
768; RV32I-NEXT:    mv a1, s1
769; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
770; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
771; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
772; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
773; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
774; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
775; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
776; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload
777; RV32I-NEXT:    addi sp, sp, 32
778; RV32I-NEXT:    ret
779;
780; RV64I-LABEL: fcvt_l_s_sat:
781; RV64I:       # %bb.0: # %start
782; RV64I-NEXT:    addi sp, sp, -48
783; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
784; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
785; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
786; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
787; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
788; RV64I-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
789; RV64I-NEXT:    mv s0, a0
790; RV64I-NEXT:    lui a1, 913408
791; RV64I-NEXT:    call __gesf2@plt
792; RV64I-NEXT:    mv s3, a0
793; RV64I-NEXT:    mv a0, s0
794; RV64I-NEXT:    call __fixsfdi@plt
795; RV64I-NEXT:    li s1, 0
796; RV64I-NEXT:    li s4, -1
797; RV64I-NEXT:    bltz s3, .LBB12_2
798; RV64I-NEXT:  # %bb.1: # %start
799; RV64I-NEXT:    mv s2, a0
800; RV64I-NEXT:    j .LBB12_3
801; RV64I-NEXT:  .LBB12_2:
802; RV64I-NEXT:    slli s2, s4, 63
803; RV64I-NEXT:  .LBB12_3: # %start
804; RV64I-NEXT:    lui a0, 389120
805; RV64I-NEXT:    addiw a1, a0, -1
806; RV64I-NEXT:    mv a0, s0
807; RV64I-NEXT:    call __gtsf2@plt
808; RV64I-NEXT:    bge s1, a0, .LBB12_5
809; RV64I-NEXT:  # %bb.4:
810; RV64I-NEXT:    srli s2, s4, 1
811; RV64I-NEXT:  .LBB12_5: # %start
812; RV64I-NEXT:    mv a0, s0
813; RV64I-NEXT:    mv a1, s0
814; RV64I-NEXT:    call __unordsf2@plt
815; RV64I-NEXT:    bne a0, s1, .LBB12_7
816; RV64I-NEXT:  # %bb.6: # %start
817; RV64I-NEXT:    mv s1, s2
818; RV64I-NEXT:  .LBB12_7: # %start
819; RV64I-NEXT:    mv a0, s1
820; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
821; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
822; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
823; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
824; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
825; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
826; RV64I-NEXT:    addi sp, sp, 48
827; RV64I-NEXT:    ret
828start:
829  %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
830  ret i64 %0
831}
832declare i64 @llvm.fptosi.sat.i64.f32(float)
833
834define i64 @fcvt_lu_s(float %a) nounwind {
835; RV32IF-LABEL: fcvt_lu_s:
836; RV32IF:       # %bb.0:
837; RV32IF-NEXT:    addi sp, sp, -16
838; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
839; RV32IF-NEXT:    call __fixunssfdi@plt
840; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
841; RV32IF-NEXT:    addi sp, sp, 16
842; RV32IF-NEXT:    ret
843;
844; RV64IF-LABEL: fcvt_lu_s:
845; RV64IF:       # %bb.0:
846; RV64IF-NEXT:    fmv.w.x ft0, a0
847; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
848; RV64IF-NEXT:    ret
849;
850; RV32I-LABEL: fcvt_lu_s:
851; RV32I:       # %bb.0:
852; RV32I-NEXT:    addi sp, sp, -16
853; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
854; RV32I-NEXT:    call __fixunssfdi@plt
855; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
856; RV32I-NEXT:    addi sp, sp, 16
857; RV32I-NEXT:    ret
858;
859; RV64I-LABEL: fcvt_lu_s:
860; RV64I:       # %bb.0:
861; RV64I-NEXT:    addi sp, sp, -16
862; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
863; RV64I-NEXT:    call __fixunssfdi@plt
864; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
865; RV64I-NEXT:    addi sp, sp, 16
866; RV64I-NEXT:    ret
867  %1 = fptoui float %a to i64
868  ret i64 %1
869}
870
871define i64 @fcvt_lu_s_sat(float %a) nounwind {
872; RV32IF-LABEL: fcvt_lu_s_sat:
873; RV32IF:       # %bb.0: # %start
874; RV32IF-NEXT:    addi sp, sp, -16
875; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
876; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
877; RV32IF-NEXT:    fmv.w.x ft1, a0
878; RV32IF-NEXT:    fmv.w.x ft0, zero
879; RV32IF-NEXT:    fsw ft1, 4(sp) # 4-byte Folded Spill
880; RV32IF-NEXT:    fle.s s0, ft0, ft1
881; RV32IF-NEXT:    call __fixunssfdi@plt
882; RV32IF-NEXT:    mv a3, a0
883; RV32IF-NEXT:    bnez s0, .LBB14_2
884; RV32IF-NEXT:  # %bb.1: # %start
885; RV32IF-NEXT:    li a3, 0
886; RV32IF-NEXT:  .LBB14_2: # %start
887; RV32IF-NEXT:    lui a0, %hi(.LCPI14_0)
888; RV32IF-NEXT:    flw ft0, %lo(.LCPI14_0)(a0)
889; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
890; RV32IF-NEXT:    flt.s a4, ft0, ft1
891; RV32IF-NEXT:    li a2, -1
892; RV32IF-NEXT:    li a0, -1
893; RV32IF-NEXT:    beqz a4, .LBB14_7
894; RV32IF-NEXT:  # %bb.3: # %start
895; RV32IF-NEXT:    beqz s0, .LBB14_8
896; RV32IF-NEXT:  .LBB14_4: # %start
897; RV32IF-NEXT:    bnez a4, .LBB14_6
898; RV32IF-NEXT:  .LBB14_5: # %start
899; RV32IF-NEXT:    mv a2, a1
900; RV32IF-NEXT:  .LBB14_6: # %start
901; RV32IF-NEXT:    mv a1, a2
902; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
903; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
904; RV32IF-NEXT:    addi sp, sp, 16
905; RV32IF-NEXT:    ret
906; RV32IF-NEXT:  .LBB14_7: # %start
907; RV32IF-NEXT:    mv a0, a3
908; RV32IF-NEXT:    bnez s0, .LBB14_4
909; RV32IF-NEXT:  .LBB14_8: # %start
910; RV32IF-NEXT:    li a1, 0
911; RV32IF-NEXT:    beqz a4, .LBB14_5
912; RV32IF-NEXT:    j .LBB14_6
913;
914; RV64IF-LABEL: fcvt_lu_s_sat:
915; RV64IF:       # %bb.0: # %start
916; RV64IF-NEXT:    fmv.w.x ft0, a0
917; RV64IF-NEXT:    feq.s a0, ft0, ft0
918; RV64IF-NEXT:    bnez a0, .LBB14_2
919; RV64IF-NEXT:  # %bb.1: # %start
920; RV64IF-NEXT:    li a0, 0
921; RV64IF-NEXT:    ret
922; RV64IF-NEXT:  .LBB14_2:
923; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
924; RV64IF-NEXT:    ret
925;
926; RV32I-LABEL: fcvt_lu_s_sat:
927; RV32I:       # %bb.0: # %start
928; RV32I-NEXT:    addi sp, sp, -32
929; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
930; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
931; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
932; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
933; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
934; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
935; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
936; RV32I-NEXT:    mv s0, a0
937; RV32I-NEXT:    li a1, 0
938; RV32I-NEXT:    call __gesf2@plt
939; RV32I-NEXT:    mv s1, a0
940; RV32I-NEXT:    mv a0, s0
941; RV32I-NEXT:    call __fixunssfdi@plt
942; RV32I-NEXT:    mv s2, a1
943; RV32I-NEXT:    li s5, 0
944; RV32I-NEXT:    bltz s1, .LBB14_2
945; RV32I-NEXT:  # %bb.1: # %start
946; RV32I-NEXT:    mv s5, a0
947; RV32I-NEXT:  .LBB14_2: # %start
948; RV32I-NEXT:    lui a0, 391168
949; RV32I-NEXT:    addi s1, a0, -1
950; RV32I-NEXT:    mv a0, s0
951; RV32I-NEXT:    mv a1, s1
952; RV32I-NEXT:    call __gtsf2@plt
953; RV32I-NEXT:    li s3, -1
954; RV32I-NEXT:    li s4, -1
955; RV32I-NEXT:    bgtz a0, .LBB14_4
956; RV32I-NEXT:  # %bb.3: # %start
957; RV32I-NEXT:    mv s4, s5
958; RV32I-NEXT:  .LBB14_4: # %start
959; RV32I-NEXT:    mv a0, s0
960; RV32I-NEXT:    li a1, 0
961; RV32I-NEXT:    call __gesf2@plt
962; RV32I-NEXT:    li s5, 0
963; RV32I-NEXT:    bltz a0, .LBB14_6
964; RV32I-NEXT:  # %bb.5: # %start
965; RV32I-NEXT:    mv s5, s2
966; RV32I-NEXT:  .LBB14_6: # %start
967; RV32I-NEXT:    mv a0, s0
968; RV32I-NEXT:    mv a1, s1
969; RV32I-NEXT:    call __gtsf2@plt
970; RV32I-NEXT:    bgtz a0, .LBB14_8
971; RV32I-NEXT:  # %bb.7: # %start
972; RV32I-NEXT:    mv s3, s5
973; RV32I-NEXT:  .LBB14_8: # %start
974; RV32I-NEXT:    mv a0, s4
975; RV32I-NEXT:    mv a1, s3
976; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
977; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
978; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
979; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
980; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
981; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
982; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
983; RV32I-NEXT:    addi sp, sp, 32
984; RV32I-NEXT:    ret
985;
986; RV64I-LABEL: fcvt_lu_s_sat:
987; RV64I:       # %bb.0: # %start
988; RV64I-NEXT:    addi sp, sp, -32
989; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
990; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
991; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
992; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
993; RV64I-NEXT:    mv s0, a0
994; RV64I-NEXT:    li a1, 0
995; RV64I-NEXT:    call __gesf2@plt
996; RV64I-NEXT:    mv s1, a0
997; RV64I-NEXT:    mv a0, s0
998; RV64I-NEXT:    call __fixunssfdi@plt
999; RV64I-NEXT:    li s2, 0
1000; RV64I-NEXT:    bltz s1, .LBB14_2
1001; RV64I-NEXT:  # %bb.1: # %start
1002; RV64I-NEXT:    mv s2, a0
1003; RV64I-NEXT:  .LBB14_2: # %start
1004; RV64I-NEXT:    lui a0, 391168
1005; RV64I-NEXT:    addiw a1, a0, -1
1006; RV64I-NEXT:    mv a0, s0
1007; RV64I-NEXT:    call __gtsf2@plt
1008; RV64I-NEXT:    mv a1, a0
1009; RV64I-NEXT:    li a0, -1
1010; RV64I-NEXT:    bgtz a1, .LBB14_4
1011; RV64I-NEXT:  # %bb.3: # %start
1012; RV64I-NEXT:    mv a0, s2
1013; RV64I-NEXT:  .LBB14_4: # %start
1014; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1015; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1016; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1017; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
1018; RV64I-NEXT:    addi sp, sp, 32
1019; RV64I-NEXT:    ret
1020start:
1021  %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
1022  ret i64 %0
1023}
1024declare i64 @llvm.fptoui.sat.i64.f32(float)
1025
1026define float @fcvt_s_l(i64 %a) nounwind {
1027; RV32IF-LABEL: fcvt_s_l:
1028; RV32IF:       # %bb.0:
1029; RV32IF-NEXT:    addi sp, sp, -16
1030; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1031; RV32IF-NEXT:    call __floatdisf@plt
1032; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1033; RV32IF-NEXT:    addi sp, sp, 16
1034; RV32IF-NEXT:    ret
1035;
1036; RV64IF-LABEL: fcvt_s_l:
1037; RV64IF:       # %bb.0:
1038; RV64IF-NEXT:    fcvt.s.l ft0, a0
1039; RV64IF-NEXT:    fmv.x.w a0, ft0
1040; RV64IF-NEXT:    ret
1041;
1042; RV32I-LABEL: fcvt_s_l:
1043; RV32I:       # %bb.0:
1044; RV32I-NEXT:    addi sp, sp, -16
1045; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1046; RV32I-NEXT:    call __floatdisf@plt
1047; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1048; RV32I-NEXT:    addi sp, sp, 16
1049; RV32I-NEXT:    ret
1050;
1051; RV64I-LABEL: fcvt_s_l:
1052; RV64I:       # %bb.0:
1053; RV64I-NEXT:    addi sp, sp, -16
1054; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1055; RV64I-NEXT:    call __floatdisf@plt
1056; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1057; RV64I-NEXT:    addi sp, sp, 16
1058; RV64I-NEXT:    ret
1059  %1 = sitofp i64 %a to float
1060  ret float %1
1061}
1062
1063define float @fcvt_s_lu(i64 %a) nounwind {
1064; RV32IF-LABEL: fcvt_s_lu:
1065; RV32IF:       # %bb.0:
1066; RV32IF-NEXT:    addi sp, sp, -16
1067; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1068; RV32IF-NEXT:    call __floatundisf@plt
1069; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1070; RV32IF-NEXT:    addi sp, sp, 16
1071; RV32IF-NEXT:    ret
1072;
1073; RV64IF-LABEL: fcvt_s_lu:
1074; RV64IF:       # %bb.0:
1075; RV64IF-NEXT:    fcvt.s.lu ft0, a0
1076; RV64IF-NEXT:    fmv.x.w a0, ft0
1077; RV64IF-NEXT:    ret
1078;
1079; RV32I-LABEL: fcvt_s_lu:
1080; RV32I:       # %bb.0:
1081; RV32I-NEXT:    addi sp, sp, -16
1082; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1083; RV32I-NEXT:    call __floatundisf@plt
1084; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1085; RV32I-NEXT:    addi sp, sp, 16
1086; RV32I-NEXT:    ret
1087;
1088; RV64I-LABEL: fcvt_s_lu:
1089; RV64I:       # %bb.0:
1090; RV64I-NEXT:    addi sp, sp, -16
1091; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1092; RV64I-NEXT:    call __floatundisf@plt
1093; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1094; RV64I-NEXT:    addi sp, sp, 16
1095; RV64I-NEXT:    ret
1096  %1 = uitofp i64 %a to float
1097  ret float %1
1098}
1099
1100define float @fcvt_s_w_i8(i8 signext %a) nounwind {
1101; RV32IF-LABEL: fcvt_s_w_i8:
1102; RV32IF:       # %bb.0:
1103; RV32IF-NEXT:    fcvt.s.w ft0, a0
1104; RV32IF-NEXT:    fmv.x.w a0, ft0
1105; RV32IF-NEXT:    ret
1106;
1107; RV64IF-LABEL: fcvt_s_w_i8:
1108; RV64IF:       # %bb.0:
1109; RV64IF-NEXT:    fcvt.s.w ft0, a0
1110; RV64IF-NEXT:    fmv.x.w a0, ft0
1111; RV64IF-NEXT:    ret
1112;
1113; RV32I-LABEL: fcvt_s_w_i8:
1114; RV32I:       # %bb.0:
1115; RV32I-NEXT:    addi sp, sp, -16
1116; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1117; RV32I-NEXT:    call __floatsisf@plt
1118; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1119; RV32I-NEXT:    addi sp, sp, 16
1120; RV32I-NEXT:    ret
1121;
1122; RV64I-LABEL: fcvt_s_w_i8:
1123; RV64I:       # %bb.0:
1124; RV64I-NEXT:    addi sp, sp, -16
1125; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1126; RV64I-NEXT:    call __floatsisf@plt
1127; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1128; RV64I-NEXT:    addi sp, sp, 16
1129; RV64I-NEXT:    ret
1130  %1 = sitofp i8 %a to float
1131  ret float %1
1132}
1133
1134define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
1135; RV32IF-LABEL: fcvt_s_wu_i8:
1136; RV32IF:       # %bb.0:
1137; RV32IF-NEXT:    fcvt.s.wu ft0, a0
1138; RV32IF-NEXT:    fmv.x.w a0, ft0
1139; RV32IF-NEXT:    ret
1140;
1141; RV64IF-LABEL: fcvt_s_wu_i8:
1142; RV64IF:       # %bb.0:
1143; RV64IF-NEXT:    fcvt.s.wu ft0, a0
1144; RV64IF-NEXT:    fmv.x.w a0, ft0
1145; RV64IF-NEXT:    ret
1146;
1147; RV32I-LABEL: fcvt_s_wu_i8:
1148; RV32I:       # %bb.0:
1149; RV32I-NEXT:    addi sp, sp, -16
1150; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1151; RV32I-NEXT:    call __floatunsisf@plt
1152; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1153; RV32I-NEXT:    addi sp, sp, 16
1154; RV32I-NEXT:    ret
1155;
1156; RV64I-LABEL: fcvt_s_wu_i8:
1157; RV64I:       # %bb.0:
1158; RV64I-NEXT:    addi sp, sp, -16
1159; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1160; RV64I-NEXT:    call __floatunsisf@plt
1161; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1162; RV64I-NEXT:    addi sp, sp, 16
1163; RV64I-NEXT:    ret
1164  %1 = uitofp i8 %a to float
1165  ret float %1
1166}
1167
1168define float @fcvt_s_w_i16(i16 signext %a) nounwind {
1169; RV32IF-LABEL: fcvt_s_w_i16:
1170; RV32IF:       # %bb.0:
1171; RV32IF-NEXT:    fcvt.s.w ft0, a0
1172; RV32IF-NEXT:    fmv.x.w a0, ft0
1173; RV32IF-NEXT:    ret
1174;
1175; RV64IF-LABEL: fcvt_s_w_i16:
1176; RV64IF:       # %bb.0:
1177; RV64IF-NEXT:    fcvt.s.w ft0, a0
1178; RV64IF-NEXT:    fmv.x.w a0, ft0
1179; RV64IF-NEXT:    ret
1180;
1181; RV32I-LABEL: fcvt_s_w_i16:
1182; RV32I:       # %bb.0:
1183; RV32I-NEXT:    addi sp, sp, -16
1184; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1185; RV32I-NEXT:    call __floatsisf@plt
1186; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1187; RV32I-NEXT:    addi sp, sp, 16
1188; RV32I-NEXT:    ret
1189;
1190; RV64I-LABEL: fcvt_s_w_i16:
1191; RV64I:       # %bb.0:
1192; RV64I-NEXT:    addi sp, sp, -16
1193; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1194; RV64I-NEXT:    call __floatsisf@plt
1195; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1196; RV64I-NEXT:    addi sp, sp, 16
1197; RV64I-NEXT:    ret
1198  %1 = sitofp i16 %a to float
1199  ret float %1
1200}
1201
1202define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
1203; RV32IF-LABEL: fcvt_s_wu_i16:
1204; RV32IF:       # %bb.0:
1205; RV32IF-NEXT:    fcvt.s.wu ft0, a0
1206; RV32IF-NEXT:    fmv.x.w a0, ft0
1207; RV32IF-NEXT:    ret
1208;
1209; RV64IF-LABEL: fcvt_s_wu_i16:
1210; RV64IF:       # %bb.0:
1211; RV64IF-NEXT:    fcvt.s.wu ft0, a0
1212; RV64IF-NEXT:    fmv.x.w a0, ft0
1213; RV64IF-NEXT:    ret
1214;
1215; RV32I-LABEL: fcvt_s_wu_i16:
1216; RV32I:       # %bb.0:
1217; RV32I-NEXT:    addi sp, sp, -16
1218; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1219; RV32I-NEXT:    call __floatunsisf@plt
1220; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1221; RV32I-NEXT:    addi sp, sp, 16
1222; RV32I-NEXT:    ret
1223;
1224; RV64I-LABEL: fcvt_s_wu_i16:
1225; RV64I:       # %bb.0:
1226; RV64I-NEXT:    addi sp, sp, -16
1227; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1228; RV64I-NEXT:    call __floatunsisf@plt
1229; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1230; RV64I-NEXT:    addi sp, sp, 16
1231; RV64I-NEXT:    ret
1232  %1 = uitofp i16 %a to float
1233  ret float %1
1234}
1235
1236; Make sure we select W version of addi on RV64.
1237define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
1238; RV32IF-LABEL: fcvt_s_w_demanded_bits:
1239; RV32IF:       # %bb.0:
1240; RV32IF-NEXT:    addi a0, a0, 1
1241; RV32IF-NEXT:    fcvt.s.w ft0, a0
1242; RV32IF-NEXT:    fsw ft0, 0(a1)
1243; RV32IF-NEXT:    ret
1244;
1245; RV64IF-LABEL: fcvt_s_w_demanded_bits:
1246; RV64IF:       # %bb.0:
1247; RV64IF-NEXT:    addiw a0, a0, 1
1248; RV64IF-NEXT:    fcvt.s.w ft0, a0
1249; RV64IF-NEXT:    fsw ft0, 0(a1)
1250; RV64IF-NEXT:    ret
1251;
1252; RV32I-LABEL: fcvt_s_w_demanded_bits:
1253; RV32I:       # %bb.0:
1254; RV32I-NEXT:    addi sp, sp, -16
1255; RV32I-NEXT:    .cfi_def_cfa_offset 16
1256; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1257; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1258; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1259; RV32I-NEXT:    .cfi_offset ra, -4
1260; RV32I-NEXT:    .cfi_offset s0, -8
1261; RV32I-NEXT:    .cfi_offset s1, -12
1262; RV32I-NEXT:    mv s0, a1
1263; RV32I-NEXT:    addi s1, a0, 1
1264; RV32I-NEXT:    mv a0, s1
1265; RV32I-NEXT:    call __floatsisf@plt
1266; RV32I-NEXT:    sw a0, 0(s0)
1267; RV32I-NEXT:    mv a0, s1
1268; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1269; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1270; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1271; RV32I-NEXT:    addi sp, sp, 16
1272; RV32I-NEXT:    ret
1273;
1274; RV64I-LABEL: fcvt_s_w_demanded_bits:
1275; RV64I:       # %bb.0:
1276; RV64I-NEXT:    addi sp, sp, -32
1277; RV64I-NEXT:    .cfi_def_cfa_offset 32
1278; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1279; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1280; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1281; RV64I-NEXT:    .cfi_offset ra, -8
1282; RV64I-NEXT:    .cfi_offset s0, -16
1283; RV64I-NEXT:    .cfi_offset s1, -24
1284; RV64I-NEXT:    mv s0, a1
1285; RV64I-NEXT:    addiw s1, a0, 1
1286; RV64I-NEXT:    mv a0, s1
1287; RV64I-NEXT:    call __floatsisf@plt
1288; RV64I-NEXT:    sw a0, 0(s0)
1289; RV64I-NEXT:    mv a0, s1
1290; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1291; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1292; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1293; RV64I-NEXT:    addi sp, sp, 32
1294; RV64I-NEXT:    ret
1295  %3 = add i32 %0, 1
1296  %4 = sitofp i32 %3 to float
1297  store float %4, float* %1, align 4
1298  ret i32 %3
1299}
1300
1301; Make sure we select W version of addi on RV64.
1302define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
1303; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
1304; RV32IF:       # %bb.0:
1305; RV32IF-NEXT:    addi a0, a0, 1
1306; RV32IF-NEXT:    fcvt.s.wu ft0, a0
1307; RV32IF-NEXT:    fsw ft0, 0(a1)
1308; RV32IF-NEXT:    ret
1309;
1310; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
1311; RV64IF:       # %bb.0:
1312; RV64IF-NEXT:    addiw a0, a0, 1
1313; RV64IF-NEXT:    fcvt.s.wu ft0, a0
1314; RV64IF-NEXT:    fsw ft0, 0(a1)
1315; RV64IF-NEXT:    ret
1316;
1317; RV32I-LABEL: fcvt_s_wu_demanded_bits:
1318; RV32I:       # %bb.0:
1319; RV32I-NEXT:    addi sp, sp, -16
1320; RV32I-NEXT:    .cfi_def_cfa_offset 16
1321; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1322; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1323; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1324; RV32I-NEXT:    .cfi_offset ra, -4
1325; RV32I-NEXT:    .cfi_offset s0, -8
1326; RV32I-NEXT:    .cfi_offset s1, -12
1327; RV32I-NEXT:    mv s0, a1
1328; RV32I-NEXT:    addi s1, a0, 1
1329; RV32I-NEXT:    mv a0, s1
1330; RV32I-NEXT:    call __floatunsisf@plt
1331; RV32I-NEXT:    sw a0, 0(s0)
1332; RV32I-NEXT:    mv a0, s1
1333; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1334; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1335; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1336; RV32I-NEXT:    addi sp, sp, 16
1337; RV32I-NEXT:    ret
1338;
1339; RV64I-LABEL: fcvt_s_wu_demanded_bits:
1340; RV64I:       # %bb.0:
1341; RV64I-NEXT:    addi sp, sp, -32
1342; RV64I-NEXT:    .cfi_def_cfa_offset 32
1343; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1344; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1345; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1346; RV64I-NEXT:    .cfi_offset ra, -8
1347; RV64I-NEXT:    .cfi_offset s0, -16
1348; RV64I-NEXT:    .cfi_offset s1, -24
1349; RV64I-NEXT:    mv s0, a1
1350; RV64I-NEXT:    addiw s1, a0, 1
1351; RV64I-NEXT:    mv a0, s1
1352; RV64I-NEXT:    call __floatunsisf@plt
1353; RV64I-NEXT:    sw a0, 0(s0)
1354; RV64I-NEXT:    mv a0, s1
1355; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1356; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1357; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1358; RV64I-NEXT:    addi sp, sp, 32
1359; RV64I-NEXT:    ret
1360  %3 = add i32 %0, 1
1361  %4 = uitofp i32 %3 to float
1362  store float %4, float* %1, align 4
1363  ret i32 %3
1364}
1365