[RISCV] Use check-prefixes to reduce check lines

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D125083

[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.

Using AArch64's original implementation for reference, this patch
implements a pass to remove unneeded copies of X0. This p

[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.

Using AArch64's original implementation for reference, this patch
implements a pass to remove unneeded copies of X0. This pass runs
after register allocation and looks to see if a register is implied
to be 0 by a branch in the predecessor basic block.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118160

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[RISCV] Set CostPerUse to 1 iff RVC is enabled

After D86836, we can define multiple cost values for
different cost models. So here we set CostPerUse to
1 iff RVC is enabled to avoid potential impact

[RISCV] Set CostPerUse to 1 iff RVC is enabled

After D86836, we can define multiple cost values for
different cost models. So here we set CostPerUse to
1 iff RVC is enabled to avoid potential impact on RA.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117741

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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC

These tests are interested in the FP instructions being used, not
the conversions needed to pass the arguments/ret

[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC

These tests are interested in the FP instructions being used, not
the conversions needed to pass the arguments/returns in GPRs.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D116869

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[SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits.

These nodes should saturate to their saturating VT. We can use this
information to know the bits past the VT

[SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits.

These nodes should saturate to their saturating VT. We can use this
information to know the bits past the VT are all zeros or all sign bits.

I think we might only have test coverage for the unsigned case. I'll
verify and add tests.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D116870

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[RISCV] Add i8/i16 fptosi/fptoui and fptosi_sat/fptoui_sat tests. NFC

Use signext/zeroext return attributes to show unnecessary ands or
shifts in the saturating tests.

[RISCV] Add nounwind to remove some cfi directives from test CHECKs. NFC

[RISCV] Remove stale comments from tests. NFC

The tests no longer generate the instructions that are mentioned
in the comments.

[RISCV] Reverse the order of loading/storing callee-saved registers.

Currently, we restore the return address register as the last restoring
instruction in the epilog. The next instruction is `ret`

[RISCV] Reverse the order of loading/storing callee-saved registers.

Currently, we restore the return address register as the last restoring
instruction in the epilog. The next instruction is `ret` usually. It is
a use of return address register. In some microarchitectures, there is
load-to-use data hazard. To avoid the load-to-use data hazard, we could
separate the load instruction from its use as far as possible. In this
patch, we reverse the order of restoring callee-saved registers to
increase the distance of `load ra` and `ret` in the epilog.

Differential Revision: https://reviews.llvm.org/D113967

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[RISCV] Generate pseudo instruction li

Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by r

[RISCV] Generate pseudo instruction li

Add an alias of `addi [x], zero, imm` to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by running script
`llvm/utils/update_llc_test_checks.py`.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D112692

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[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC

This improves our coverage of soft float libcalls lowering.

Remove most of the test cases from rv64i-single-softfloat.ll. The

[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC

This improves our coverage of soft float libcalls lowering.

Remove most of the test cases from rv64i-single-softfloat.ll. They
were duplicated in the test files that now test softflow. Only
a couple test cases for constrained FP remain. Those should be
removed when we start supporting constrained FP.

This is follow up from D113528.

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[RISCV] Remove stale FIXMEs from float-convert.ll and double-convert.ll. NFC

[RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsers

These instructions only read the lower 32 bits of their input.

[RISCV] Add test cases showing failure to use ADDIW before fcvt.s.w/fcvt.d.w/fcvt.h.w. NFC

By not using ADDIW we can cause both an ADDIW and ADDI to be emitted
when the add has multiple users.

Thes

[RISCV] Add test cases showing failure to use ADDIW before fcvt.s.w/fcvt.d.w/fcvt.h.w. NFC

By not using ADDIW we can cause both an ADDIW and ADDI to be emitted
when the add has multiple users.

These instructions needed be added to the list of instructions that
only use the lower 32 bits of input.

I've also added tests for the wu versions, but I'm having trouble
showing bad codegen from it.

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[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.

The fcvt fp to integer instructions saturate if their input is
infinity or out of range, but the instructions produce a maximum
integer for nan inst

[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.

The fcvt fp to integer instructions saturate if their input is
infinity or out of range, but the instructions produce a maximum
integer for nan instead of 0 required for the ISD opcodes.

This means we can use the instructions to do the saturating
conversion, but we'll need to fix up the nan case at the end.

We can probably improve the i8 and i16 default codegen as well,
but I'll leave that for a follow up.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D107230

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[RISCV] Custom lower (i32 (fptoui/fptosi X)).

I stumbled onto a case where our (sext_inreg (assertzexti32 (fptoui X)), i32)
isel pattern can cause an fcvt.wu and fcvt.lu to be emitted if
the assertz

[RISCV] Custom lower (i32 (fptoui/fptosi X)).

I stumbled onto a case where our (sext_inreg (assertzexti32 (fptoui X)), i32)
isel pattern can cause an fcvt.wu and fcvt.lu to be emitted if
the assertzexti32 has an additional user. If we add a one use check
it would just cause a fcvt.lu followed by a sext.w when only need
a fcvt.wu to satisfy both users.

To mitigate this I've added custom isel and new ISD opcodes for
fcvt.wu. This allows us to keep know it started life as a conversion
to i32 without needing to match multiple nodes. ComputeNumSignBits
has been taught that this new nodes produces 33 sign bits. To
prevent regressions when we need to zero extend the result of an
(i32 (fptoui X)), I've added a DAG combine to convert it to an
(i64 (fptoui X)) before type legalization. In most cases this would
happen in InstCombine, but a zero_extend can be created for function
returns or arguments.

To keep everything consistent I've added new nodes for fptosi as well.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D106346

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[RISCV] Add test cases to show an issue with our fcvt.wu isel patterns on RV64.

The pattern we match is (sext_inreg (assertzexti32 (fp_to_uint)), i32). If
the assertzexti32 has an additional user we

[RISCV] Add test cases to show an issue with our fcvt.wu isel patterns on RV64.

The pattern we match is (sext_inreg (assertzexti32 (fp_to_uint)), i32). If
the assertzexti32 has an additional user we'll end up emitting
an fcvt.wu and an fcvt.lu.

This can happen if the original fp_to_uint before type legalization
has one user that causes a sext_inreg to be emitted and one that
doesn't.

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[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_ex

[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_extend_inreg or AND folded into
sextload/zextload.

Differential Revision: https://reviews.llvm.org/D104079

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[RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC

The loads end up becoming sextload/zextload which prevent our
isel patterns from finding the

[RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC

The loads end up becoming sextload/zextload which prevent our
isel patterns from finding the sign_extend_inreg or AND instruction
we need.

The easiest way to fix this is to use computeKnownBits or
ComputeNumSignBits in our isel matching to catch this.

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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.

Add PromoteIntOp_FP_TO_XINT_SAT to type legalize the bit width
operand from i32 to i64 for RV64.

Add test cases for

[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.

Add PromoteIntOp_FP_TO_XINT_SAT to type legalize the bit width
operand from i32 to i64 for RV64.

Add test cases for the saturating intrinsics for half/float/double
and i32/i64. CodeGen is definitely not optimal. We can probably
make use of the native behavior of fcvt instructions in many cases.

Fixes PR50083

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[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.

The patterns that use this really want to know if the operand has at
least 32 sign/zero bits.

This increases opp

[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.

The patterns that use this really want to know if the operand has at
least 32 sign/zero bits.

This increases opportunities to use W instructions when the original
source used i8/i16. Not sure how much this matters for performance,
but it makes i8/i16 code more consistent with i32.

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[RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16.

[RISCV][NFC] Regenerate RISCV CodeGen tests

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and adde

[RISCV][NFC] Regenerate RISCV CodeGen tests

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Differential Revision: https://reviews.llvm.org/D92841

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[RISCV] Switch to the Machine Scheduler

Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revisio

[RISCV] Switch to the Machine Scheduler

Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106

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Revert Patch from Phabricator

This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04)

llvm-svn: 372104