1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6
7; For RV64F, fcvt.l.s is semantically equivalent to fcvt.w.s in this case
8; because fptosi will produce poison if the result doesn't fit into an i32.
9define i32 @fcvt_w_s(float %a) nounwind {
10; RV32IF-LABEL: fcvt_w_s:
11; RV32IF:       # %bb.0:
12; RV32IF-NEXT:    fmv.w.x ft0, a0
13; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
14; RV32IF-NEXT:    ret
15;
16; RV64IF-LABEL: fcvt_w_s:
17; RV64IF:       # %bb.0:
18; RV64IF-NEXT:    fmv.w.x ft0, a0
19; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
20; RV64IF-NEXT:    ret
21  %1 = fptosi float %a to i32
22  ret i32 %1
23}
24
25define i32 @fcvt_w_s_sat(float %a) nounwind {
26; RV32IF-LABEL: fcvt_w_s_sat:
27; RV32IF:       # %bb.0: # %start
28; RV32IF-NEXT:    lui a1, %hi(.LCPI1_0)
29; RV32IF-NEXT:    flw ft1, %lo(.LCPI1_0)(a1)
30; RV32IF-NEXT:    fmv.w.x ft0, a0
31; RV32IF-NEXT:    fle.s a0, ft1, ft0
32; RV32IF-NEXT:    lui a1, 524288
33; RV32IF-NEXT:    bnez a0, .LBB1_2
34; RV32IF-NEXT:  # %bb.1: # %start
35; RV32IF-NEXT:    lui a0, 524288
36; RV32IF-NEXT:    j .LBB1_3
37; RV32IF-NEXT:  .LBB1_2:
38; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
39; RV32IF-NEXT:  .LBB1_3: # %start
40; RV32IF-NEXT:    lui a2, %hi(.LCPI1_1)
41; RV32IF-NEXT:    flw ft1, %lo(.LCPI1_1)(a2)
42; RV32IF-NEXT:    flt.s a2, ft1, ft0
43; RV32IF-NEXT:    bnez a2, .LBB1_6
44; RV32IF-NEXT:  # %bb.4: # %start
45; RV32IF-NEXT:    feq.s a1, ft0, ft0
46; RV32IF-NEXT:    beqz a1, .LBB1_7
47; RV32IF-NEXT:  .LBB1_5: # %start
48; RV32IF-NEXT:    ret
49; RV32IF-NEXT:  .LBB1_6:
50; RV32IF-NEXT:    addi a0, a1, -1
51; RV32IF-NEXT:    feq.s a1, ft0, ft0
52; RV32IF-NEXT:    bnez a1, .LBB1_5
53; RV32IF-NEXT:  .LBB1_7: # %start
54; RV32IF-NEXT:    mv a0, zero
55; RV32IF-NEXT:    ret
56;
57; RV64IF-LABEL: fcvt_w_s_sat:
58; RV64IF:       # %bb.0: # %start
59; RV64IF-NEXT:    lui a1, %hi(.LCPI1_0)
60; RV64IF-NEXT:    flw ft1, %lo(.LCPI1_0)(a1)
61; RV64IF-NEXT:    fmv.w.x ft0, a0
62; RV64IF-NEXT:    fle.s a0, ft1, ft0
63; RV64IF-NEXT:    lui a1, 524288
64; RV64IF-NEXT:    bnez a0, .LBB1_2
65; RV64IF-NEXT:  # %bb.1: # %start
66; RV64IF-NEXT:    lui a0, 524288
67; RV64IF-NEXT:    j .LBB1_3
68; RV64IF-NEXT:  .LBB1_2:
69; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
70; RV64IF-NEXT:  .LBB1_3: # %start
71; RV64IF-NEXT:    lui a2, %hi(.LCPI1_1)
72; RV64IF-NEXT:    flw ft1, %lo(.LCPI1_1)(a2)
73; RV64IF-NEXT:    flt.s a2, ft1, ft0
74; RV64IF-NEXT:    bnez a2, .LBB1_6
75; RV64IF-NEXT:  # %bb.4: # %start
76; RV64IF-NEXT:    feq.s a1, ft0, ft0
77; RV64IF-NEXT:    beqz a1, .LBB1_7
78; RV64IF-NEXT:  .LBB1_5: # %start
79; RV64IF-NEXT:    ret
80; RV64IF-NEXT:  .LBB1_6:
81; RV64IF-NEXT:    addiw a0, a1, -1
82; RV64IF-NEXT:    feq.s a1, ft0, ft0
83; RV64IF-NEXT:    bnez a1, .LBB1_5
84; RV64IF-NEXT:  .LBB1_7: # %start
85; RV64IF-NEXT:    mv a0, zero
86; RV64IF-NEXT:    ret
87start:
88  %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
89  ret i32 %0
90}
91declare i32 @llvm.fptosi.sat.i32.f32(float)
92
93; For RV64F, fcvt.lu.s is semantically equivalent to fcvt.wu.s in this case
94; because fptoui will produce poison if the result doesn't fit into an i32.
95define i32 @fcvt_wu_s(float %a) nounwind {
96; RV32IF-LABEL: fcvt_wu_s:
97; RV32IF:       # %bb.0:
98; RV32IF-NEXT:    fmv.w.x ft0, a0
99; RV32IF-NEXT:    fcvt.wu.s a0, ft0, rtz
100; RV32IF-NEXT:    ret
101;
102; RV64IF-LABEL: fcvt_wu_s:
103; RV64IF:       # %bb.0:
104; RV64IF-NEXT:    fmv.w.x ft0, a0
105; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
106; RV64IF-NEXT:    ret
107  %1 = fptoui float %a to i32
108  ret i32 %1
109}
110
111define i32 @fcvt_wu_s_sat(float %a) nounwind {
112; RV32IF-LABEL: fcvt_wu_s_sat:
113; RV32IF:       # %bb.0: # %start
114; RV32IF-NEXT:    fmv.w.x ft0, a0
115; RV32IF-NEXT:    fmv.w.x ft1, zero
116; RV32IF-NEXT:    fle.s a0, ft1, ft0
117; RV32IF-NEXT:    bnez a0, .LBB3_2
118; RV32IF-NEXT:  # %bb.1: # %start
119; RV32IF-NEXT:    mv a1, zero
120; RV32IF-NEXT:    j .LBB3_3
121; RV32IF-NEXT:  .LBB3_2:
122; RV32IF-NEXT:    fcvt.wu.s a1, ft0, rtz
123; RV32IF-NEXT:  .LBB3_3: # %start
124; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
125; RV32IF-NEXT:    flw ft1, %lo(.LCPI3_0)(a0)
126; RV32IF-NEXT:    flt.s a2, ft1, ft0
127; RV32IF-NEXT:    addi a0, zero, -1
128; RV32IF-NEXT:    bnez a2, .LBB3_5
129; RV32IF-NEXT:  # %bb.4: # %start
130; RV32IF-NEXT:    mv a0, a1
131; RV32IF-NEXT:  .LBB3_5: # %start
132; RV32IF-NEXT:    ret
133;
134; RV64IF-LABEL: fcvt_wu_s_sat:
135; RV64IF:       # %bb.0: # %start
136; RV64IF-NEXT:    fmv.w.x ft0, a0
137; RV64IF-NEXT:    fmv.w.x ft1, zero
138; RV64IF-NEXT:    fle.s a0, ft1, ft0
139; RV64IF-NEXT:    bnez a0, .LBB3_2
140; RV64IF-NEXT:  # %bb.1: # %start
141; RV64IF-NEXT:    mv a0, zero
142; RV64IF-NEXT:    j .LBB3_3
143; RV64IF-NEXT:  .LBB3_2:
144; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
145; RV64IF-NEXT:  .LBB3_3: # %start
146; RV64IF-NEXT:    lui a1, %hi(.LCPI3_0)
147; RV64IF-NEXT:    flw ft1, %lo(.LCPI3_0)(a1)
148; RV64IF-NEXT:    flt.s a1, ft1, ft0
149; RV64IF-NEXT:    beqz a1, .LBB3_5
150; RV64IF-NEXT:  # %bb.4:
151; RV64IF-NEXT:    addi a0, zero, -1
152; RV64IF-NEXT:    srli a0, a0, 32
153; RV64IF-NEXT:  .LBB3_5: # %start
154; RV64IF-NEXT:    ret
155start:
156  %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
157  ret i32 %0
158}
159declare i32 @llvm.fptoui.sat.i32.f32(float)
160
161define i32 @fmv_x_w(float %a, float %b) nounwind {
162; RV32IF-LABEL: fmv_x_w:
163; RV32IF:       # %bb.0:
164; RV32IF-NEXT:    fmv.w.x ft0, a1
165; RV32IF-NEXT:    fmv.w.x ft1, a0
166; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
167; RV32IF-NEXT:    fmv.x.w a0, ft0
168; RV32IF-NEXT:    ret
169;
170; RV64IF-LABEL: fmv_x_w:
171; RV64IF:       # %bb.0:
172; RV64IF-NEXT:    fmv.w.x ft0, a1
173; RV64IF-NEXT:    fmv.w.x ft1, a0
174; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
175; RV64IF-NEXT:    fmv.x.w a0, ft0
176; RV64IF-NEXT:    ret
177; Ensure fmv.x.w is generated even for a soft float calling convention
178  %1 = fadd float %a, %b
179  %2 = bitcast float %1 to i32
180  ret i32 %2
181}
182
183define float @fcvt_s_w(i32 %a) nounwind {
184; RV32IF-LABEL: fcvt_s_w:
185; RV32IF:       # %bb.0:
186; RV32IF-NEXT:    fcvt.s.w ft0, a0
187; RV32IF-NEXT:    fmv.x.w a0, ft0
188; RV32IF-NEXT:    ret
189;
190; RV64IF-LABEL: fcvt_s_w:
191; RV64IF:       # %bb.0:
192; RV64IF-NEXT:    fcvt.s.w ft0, a0
193; RV64IF-NEXT:    fmv.x.w a0, ft0
194; RV64IF-NEXT:    ret
195  %1 = sitofp i32 %a to float
196  ret float %1
197}
198
199define float @fcvt_s_w_load(i32* %p) nounwind {
200; RV32IF-LABEL: fcvt_s_w_load:
201; RV32IF:       # %bb.0:
202; RV32IF-NEXT:    lw a0, 0(a0)
203; RV32IF-NEXT:    fcvt.s.w ft0, a0
204; RV32IF-NEXT:    fmv.x.w a0, ft0
205; RV32IF-NEXT:    ret
206;
207; RV64IF-LABEL: fcvt_s_w_load:
208; RV64IF:       # %bb.0:
209; RV64IF-NEXT:    lw a0, 0(a0)
210; RV64IF-NEXT:    fcvt.s.w ft0, a0
211; RV64IF-NEXT:    fmv.x.w a0, ft0
212; RV64IF-NEXT:    ret
213  %a = load i32, i32* %p
214  %1 = sitofp i32 %a to float
215  ret float %1
216}
217
218define float @fcvt_s_wu(i32 %a) nounwind {
219; RV32IF-LABEL: fcvt_s_wu:
220; RV32IF:       # %bb.0:
221; RV32IF-NEXT:    fcvt.s.wu ft0, a0
222; RV32IF-NEXT:    fmv.x.w a0, ft0
223; RV32IF-NEXT:    ret
224;
225; RV64IF-LABEL: fcvt_s_wu:
226; RV64IF:       # %bb.0:
227; RV64IF-NEXT:    fcvt.s.wu ft0, a0
228; RV64IF-NEXT:    fmv.x.w a0, ft0
229; RV64IF-NEXT:    ret
230  %1 = uitofp i32 %a to float
231  ret float %1
232}
233
234define float @fcvt_s_wu_load(i32* %p) nounwind {
235; RV32IF-LABEL: fcvt_s_wu_load:
236; RV32IF:       # %bb.0:
237; RV32IF-NEXT:    lw a0, 0(a0)
238; RV32IF-NEXT:    fcvt.s.wu ft0, a0
239; RV32IF-NEXT:    fmv.x.w a0, ft0
240; RV32IF-NEXT:    ret
241;
242; RV64IF-LABEL: fcvt_s_wu_load:
243; RV64IF:       # %bb.0:
244; RV64IF-NEXT:    lwu a0, 0(a0)
245; RV64IF-NEXT:    fcvt.s.wu ft0, a0
246; RV64IF-NEXT:    fmv.x.w a0, ft0
247; RV64IF-NEXT:    ret
248  %a = load i32, i32* %p
249  %1 = uitofp i32 %a to float
250  ret float %1
251}
252
253define float @fmv_w_x(i32 %a, i32 %b) nounwind {
254; RV32IF-LABEL: fmv_w_x:
255; RV32IF:       # %bb.0:
256; RV32IF-NEXT:    fmv.w.x ft0, a0
257; RV32IF-NEXT:    fmv.w.x ft1, a1
258; RV32IF-NEXT:    fadd.s ft0, ft0, ft1
259; RV32IF-NEXT:    fmv.x.w a0, ft0
260; RV32IF-NEXT:    ret
261;
262; RV64IF-LABEL: fmv_w_x:
263; RV64IF:       # %bb.0:
264; RV64IF-NEXT:    fmv.w.x ft0, a0
265; RV64IF-NEXT:    fmv.w.x ft1, a1
266; RV64IF-NEXT:    fadd.s ft0, ft0, ft1
267; RV64IF-NEXT:    fmv.x.w a0, ft0
268; RV64IF-NEXT:    ret
269; Ensure fmv.w.x is generated even for a soft float calling convention
270  %1 = bitcast i32 %a to float
271  %2 = bitcast i32 %b to float
272  %3 = fadd float %1, %2
273  ret float %3
274}
275
276define i64 @fcvt_l_s(float %a) nounwind {
277; RV32IF-LABEL: fcvt_l_s:
278; RV32IF:       # %bb.0:
279; RV32IF-NEXT:    addi sp, sp, -16
280; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
281; RV32IF-NEXT:    call __fixsfdi@plt
282; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
283; RV32IF-NEXT:    addi sp, sp, 16
284; RV32IF-NEXT:    ret
285;
286; RV64IF-LABEL: fcvt_l_s:
287; RV64IF:       # %bb.0:
288; RV64IF-NEXT:    fmv.w.x ft0, a0
289; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
290; RV64IF-NEXT:    ret
291  %1 = fptosi float %a to i64
292  ret i64 %1
293}
294
295define i64 @fcvt_l_s_sat(float %a) nounwind {
296; RV32IF-LABEL: fcvt_l_s_sat:
297; RV32IF:       # %bb.0: # %start
298; RV32IF-NEXT:    addi sp, sp, -16
299; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
300; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
301; RV32IF-NEXT:    lui a1, %hi(.LCPI11_0)
302; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a1)
303; RV32IF-NEXT:    fmv.w.x ft1, a0
304; RV32IF-NEXT:    fsw ft1, 4(sp) # 4-byte Folded Spill
305; RV32IF-NEXT:    fle.s s0, ft0, ft1
306; RV32IF-NEXT:    call __fixsfdi@plt
307; RV32IF-NEXT:    mv a2, a0
308; RV32IF-NEXT:    bnez s0, .LBB11_2
309; RV32IF-NEXT:  # %bb.1: # %start
310; RV32IF-NEXT:    mv a2, zero
311; RV32IF-NEXT:  .LBB11_2: # %start
312; RV32IF-NEXT:    lui a0, %hi(.LCPI11_1)
313; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_1)(a0)
314; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
315; RV32IF-NEXT:    flt.s a3, ft0, ft1
316; RV32IF-NEXT:    fmv.s ft0, ft1
317; RV32IF-NEXT:    addi a0, zero, -1
318; RV32IF-NEXT:    beqz a3, .LBB11_9
319; RV32IF-NEXT:  # %bb.3: # %start
320; RV32IF-NEXT:    feq.s a2, ft0, ft0
321; RV32IF-NEXT:    beqz a2, .LBB11_10
322; RV32IF-NEXT:  .LBB11_4: # %start
323; RV32IF-NEXT:    lui a4, 524288
324; RV32IF-NEXT:    beqz s0, .LBB11_11
325; RV32IF-NEXT:  .LBB11_5: # %start
326; RV32IF-NEXT:    bnez a3, .LBB11_12
327; RV32IF-NEXT:  .LBB11_6: # %start
328; RV32IF-NEXT:    bnez a2, .LBB11_8
329; RV32IF-NEXT:  .LBB11_7: # %start
330; RV32IF-NEXT:    mv a1, zero
331; RV32IF-NEXT:  .LBB11_8: # %start
332; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
333; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
334; RV32IF-NEXT:    addi sp, sp, 16
335; RV32IF-NEXT:    ret
336; RV32IF-NEXT:  .LBB11_9: # %start
337; RV32IF-NEXT:    mv a0, a2
338; RV32IF-NEXT:    feq.s a2, ft0, ft0
339; RV32IF-NEXT:    bnez a2, .LBB11_4
340; RV32IF-NEXT:  .LBB11_10: # %start
341; RV32IF-NEXT:    mv a0, zero
342; RV32IF-NEXT:    lui a4, 524288
343; RV32IF-NEXT:    bnez s0, .LBB11_5
344; RV32IF-NEXT:  .LBB11_11: # %start
345; RV32IF-NEXT:    lui a1, 524288
346; RV32IF-NEXT:    beqz a3, .LBB11_6
347; RV32IF-NEXT:  .LBB11_12:
348; RV32IF-NEXT:    addi a1, a4, -1
349; RV32IF-NEXT:    beqz a2, .LBB11_7
350; RV32IF-NEXT:    j .LBB11_8
351;
352; RV64IF-LABEL: fcvt_l_s_sat:
353; RV64IF:       # %bb.0: # %start
354; RV64IF-NEXT:    lui a1, %hi(.LCPI11_0)
355; RV64IF-NEXT:    flw ft1, %lo(.LCPI11_0)(a1)
356; RV64IF-NEXT:    fmv.w.x ft0, a0
357; RV64IF-NEXT:    fle.s a0, ft1, ft0
358; RV64IF-NEXT:    addi a1, zero, -1
359; RV64IF-NEXT:    bnez a0, .LBB11_2
360; RV64IF-NEXT:  # %bb.1: # %start
361; RV64IF-NEXT:    slli a0, a1, 63
362; RV64IF-NEXT:    j .LBB11_3
363; RV64IF-NEXT:  .LBB11_2:
364; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
365; RV64IF-NEXT:  .LBB11_3: # %start
366; RV64IF-NEXT:    lui a2, %hi(.LCPI11_1)
367; RV64IF-NEXT:    flw ft1, %lo(.LCPI11_1)(a2)
368; RV64IF-NEXT:    flt.s a2, ft1, ft0
369; RV64IF-NEXT:    bnez a2, .LBB11_6
370; RV64IF-NEXT:  # %bb.4: # %start
371; RV64IF-NEXT:    feq.s a1, ft0, ft0
372; RV64IF-NEXT:    beqz a1, .LBB11_7
373; RV64IF-NEXT:  .LBB11_5: # %start
374; RV64IF-NEXT:    ret
375; RV64IF-NEXT:  .LBB11_6:
376; RV64IF-NEXT:    srli a0, a1, 1
377; RV64IF-NEXT:    feq.s a1, ft0, ft0
378; RV64IF-NEXT:    bnez a1, .LBB11_5
379; RV64IF-NEXT:  .LBB11_7: # %start
380; RV64IF-NEXT:    mv a0, zero
381; RV64IF-NEXT:    ret
382start:
383  %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
384  ret i64 %0
385}
386declare i64 @llvm.fptosi.sat.i64.f32(float)
387
388define i64 @fcvt_lu_s(float %a) nounwind {
389; RV32IF-LABEL: fcvt_lu_s:
390; RV32IF:       # %bb.0:
391; RV32IF-NEXT:    addi sp, sp, -16
392; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
393; RV32IF-NEXT:    call __fixunssfdi@plt
394; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
395; RV32IF-NEXT:    addi sp, sp, 16
396; RV32IF-NEXT:    ret
397;
398; RV64IF-LABEL: fcvt_lu_s:
399; RV64IF:       # %bb.0:
400; RV64IF-NEXT:    fmv.w.x ft0, a0
401; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
402; RV64IF-NEXT:    ret
403  %1 = fptoui float %a to i64
404  ret i64 %1
405}
406
407define i64 @fcvt_lu_s_sat(float %a) nounwind {
408; RV32IF-LABEL: fcvt_lu_s_sat:
409; RV32IF:       # %bb.0: # %start
410; RV32IF-NEXT:    addi sp, sp, -16
411; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
412; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
413; RV32IF-NEXT:    fmv.w.x ft1, a0
414; RV32IF-NEXT:    fmv.w.x ft0, zero
415; RV32IF-NEXT:    fsw ft1, 4(sp) # 4-byte Folded Spill
416; RV32IF-NEXT:    fle.s s0, ft0, ft1
417; RV32IF-NEXT:    call __fixunssfdi@plt
418; RV32IF-NEXT:    mv a3, a0
419; RV32IF-NEXT:    bnez s0, .LBB13_2
420; RV32IF-NEXT:  # %bb.1: # %start
421; RV32IF-NEXT:    mv a3, zero
422; RV32IF-NEXT:  .LBB13_2: # %start
423; RV32IF-NEXT:    lui a0, %hi(.LCPI13_0)
424; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_0)(a0)
425; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
426; RV32IF-NEXT:    flt.s a4, ft0, ft1
427; RV32IF-NEXT:    addi a2, zero, -1
428; RV32IF-NEXT:    addi a0, zero, -1
429; RV32IF-NEXT:    beqz a4, .LBB13_7
430; RV32IF-NEXT:  # %bb.3: # %start
431; RV32IF-NEXT:    beqz s0, .LBB13_8
432; RV32IF-NEXT:  .LBB13_4: # %start
433; RV32IF-NEXT:    bnez a4, .LBB13_6
434; RV32IF-NEXT:  .LBB13_5: # %start
435; RV32IF-NEXT:    mv a2, a1
436; RV32IF-NEXT:  .LBB13_6: # %start
437; RV32IF-NEXT:    mv a1, a2
438; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
439; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
440; RV32IF-NEXT:    addi sp, sp, 16
441; RV32IF-NEXT:    ret
442; RV32IF-NEXT:  .LBB13_7: # %start
443; RV32IF-NEXT:    mv a0, a3
444; RV32IF-NEXT:    bnez s0, .LBB13_4
445; RV32IF-NEXT:  .LBB13_8: # %start
446; RV32IF-NEXT:    mv a1, zero
447; RV32IF-NEXT:    beqz a4, .LBB13_5
448; RV32IF-NEXT:    j .LBB13_6
449;
450; RV64IF-LABEL: fcvt_lu_s_sat:
451; RV64IF:       # %bb.0: # %start
452; RV64IF-NEXT:    fmv.w.x ft0, a0
453; RV64IF-NEXT:    fmv.w.x ft1, zero
454; RV64IF-NEXT:    fle.s a0, ft1, ft0
455; RV64IF-NEXT:    bnez a0, .LBB13_2
456; RV64IF-NEXT:  # %bb.1: # %start
457; RV64IF-NEXT:    mv a1, zero
458; RV64IF-NEXT:    j .LBB13_3
459; RV64IF-NEXT:  .LBB13_2:
460; RV64IF-NEXT:    fcvt.lu.s a1, ft0, rtz
461; RV64IF-NEXT:  .LBB13_3: # %start
462; RV64IF-NEXT:    lui a0, %hi(.LCPI13_0)
463; RV64IF-NEXT:    flw ft1, %lo(.LCPI13_0)(a0)
464; RV64IF-NEXT:    flt.s a2, ft1, ft0
465; RV64IF-NEXT:    addi a0, zero, -1
466; RV64IF-NEXT:    bnez a2, .LBB13_5
467; RV64IF-NEXT:  # %bb.4: # %start
468; RV64IF-NEXT:    mv a0, a1
469; RV64IF-NEXT:  .LBB13_5: # %start
470; RV64IF-NEXT:    ret
471start:
472  %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
473  ret i64 %0
474}
475declare i64 @llvm.fptoui.sat.i64.f32(float)
476
477define float @fcvt_s_l(i64 %a) nounwind {
478; RV32IF-LABEL: fcvt_s_l:
479; RV32IF:       # %bb.0:
480; RV32IF-NEXT:    addi sp, sp, -16
481; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
482; RV32IF-NEXT:    call __floatdisf@plt
483; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
484; RV32IF-NEXT:    addi sp, sp, 16
485; RV32IF-NEXT:    ret
486;
487; RV64IF-LABEL: fcvt_s_l:
488; RV64IF:       # %bb.0:
489; RV64IF-NEXT:    fcvt.s.l ft0, a0
490; RV64IF-NEXT:    fmv.x.w a0, ft0
491; RV64IF-NEXT:    ret
492  %1 = sitofp i64 %a to float
493  ret float %1
494}
495
496define float @fcvt_s_lu(i64 %a) nounwind {
497; RV32IF-LABEL: fcvt_s_lu:
498; RV32IF:       # %bb.0:
499; RV32IF-NEXT:    addi sp, sp, -16
500; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
501; RV32IF-NEXT:    call __floatundisf@plt
502; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
503; RV32IF-NEXT:    addi sp, sp, 16
504; RV32IF-NEXT:    ret
505;
506; RV64IF-LABEL: fcvt_s_lu:
507; RV64IF:       # %bb.0:
508; RV64IF-NEXT:    fcvt.s.lu ft0, a0
509; RV64IF-NEXT:    fmv.x.w a0, ft0
510; RV64IF-NEXT:    ret
511  %1 = uitofp i64 %a to float
512  ret float %1
513}
514
515define float @fcvt_s_w_i8(i8 signext %a) nounwind {
516; RV32IF-LABEL: fcvt_s_w_i8:
517; RV32IF:       # %bb.0:
518; RV32IF-NEXT:    fcvt.s.w ft0, a0
519; RV32IF-NEXT:    fmv.x.w a0, ft0
520; RV32IF-NEXT:    ret
521;
522; RV64IF-LABEL: fcvt_s_w_i8:
523; RV64IF:       # %bb.0:
524; RV64IF-NEXT:    fcvt.s.w ft0, a0
525; RV64IF-NEXT:    fmv.x.w a0, ft0
526; RV64IF-NEXT:    ret
527  %1 = sitofp i8 %a to float
528  ret float %1
529}
530
531define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
532; RV32IF-LABEL: fcvt_s_wu_i8:
533; RV32IF:       # %bb.0:
534; RV32IF-NEXT:    fcvt.s.wu ft0, a0
535; RV32IF-NEXT:    fmv.x.w a0, ft0
536; RV32IF-NEXT:    ret
537;
538; RV64IF-LABEL: fcvt_s_wu_i8:
539; RV64IF:       # %bb.0:
540; RV64IF-NEXT:    fcvt.s.wu ft0, a0
541; RV64IF-NEXT:    fmv.x.w a0, ft0
542; RV64IF-NEXT:    ret
543  %1 = uitofp i8 %a to float
544  ret float %1
545}
546
547define float @fcvt_s_w_i16(i16 signext %a) nounwind {
548; RV32IF-LABEL: fcvt_s_w_i16:
549; RV32IF:       # %bb.0:
550; RV32IF-NEXT:    fcvt.s.w ft0, a0
551; RV32IF-NEXT:    fmv.x.w a0, ft0
552; RV32IF-NEXT:    ret
553;
554; RV64IF-LABEL: fcvt_s_w_i16:
555; RV64IF:       # %bb.0:
556; RV64IF-NEXT:    fcvt.s.w ft0, a0
557; RV64IF-NEXT:    fmv.x.w a0, ft0
558; RV64IF-NEXT:    ret
559  %1 = sitofp i16 %a to float
560  ret float %1
561}
562
563define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
564; RV32IF-LABEL: fcvt_s_wu_i16:
565; RV32IF:       # %bb.0:
566; RV32IF-NEXT:    fcvt.s.wu ft0, a0
567; RV32IF-NEXT:    fmv.x.w a0, ft0
568; RV32IF-NEXT:    ret
569;
570; RV64IF-LABEL: fcvt_s_wu_i16:
571; RV64IF:       # %bb.0:
572; RV64IF-NEXT:    fcvt.s.wu ft0, a0
573; RV64IF-NEXT:    fmv.x.w a0, ft0
574; RV64IF-NEXT:    ret
575  %1 = uitofp i16 %a to float
576  ret float %1
577}
578