1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6
7; For RV64F, fcvt.l.s is semantically equivalent to fcvt.w.s in this case
8; because fptosi will produce poison if the result doesn't fit into an i32.
9define i32 @fcvt_w_s(float %a) nounwind {
10; RV32IF-LABEL: fcvt_w_s:
11; RV32IF:       # %bb.0:
12; RV32IF-NEXT:    fmv.w.x ft0, a0
13; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
14; RV32IF-NEXT:    ret
15;
16; RV64IF-LABEL: fcvt_w_s:
17; RV64IF:       # %bb.0:
18; RV64IF-NEXT:    fmv.w.x ft0, a0
19; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
20; RV64IF-NEXT:    ret
21  %1 = fptosi float %a to i32
22  ret i32 %1
23}
24
25define i32 @fcvt_w_s_sat(float %a) nounwind {
26; RV32IF-LABEL: fcvt_w_s_sat:
27; RV32IF:       # %bb.0: # %start
28; RV32IF-NEXT:    lui a1, %hi(.LCPI1_0)
29; RV32IF-NEXT:    flw ft1, %lo(.LCPI1_0)(a1)
30; RV32IF-NEXT:    fmv.w.x ft0, a0
31; RV32IF-NEXT:    fle.s a0, ft1, ft0
32; RV32IF-NEXT:    lui a1, 524288
33; RV32IF-NEXT:    bnez a0, .LBB1_2
34; RV32IF-NEXT:  # %bb.1: # %start
35; RV32IF-NEXT:    lui a0, 524288
36; RV32IF-NEXT:    j .LBB1_3
37; RV32IF-NEXT:  .LBB1_2:
38; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
39; RV32IF-NEXT:  .LBB1_3: # %start
40; RV32IF-NEXT:    lui a2, %hi(.LCPI1_1)
41; RV32IF-NEXT:    flw ft1, %lo(.LCPI1_1)(a2)
42; RV32IF-NEXT:    flt.s a2, ft1, ft0
43; RV32IF-NEXT:    bnez a2, .LBB1_6
44; RV32IF-NEXT:  # %bb.4: # %start
45; RV32IF-NEXT:    feq.s a1, ft0, ft0
46; RV32IF-NEXT:    beqz a1, .LBB1_7
47; RV32IF-NEXT:  .LBB1_5: # %start
48; RV32IF-NEXT:    ret
49; RV32IF-NEXT:  .LBB1_6:
50; RV32IF-NEXT:    addi a0, a1, -1
51; RV32IF-NEXT:    feq.s a1, ft0, ft0
52; RV32IF-NEXT:    bnez a1, .LBB1_5
53; RV32IF-NEXT:  .LBB1_7: # %start
54; RV32IF-NEXT:    mv a0, zero
55; RV32IF-NEXT:    ret
56;
57; RV64IF-LABEL: fcvt_w_s_sat:
58; RV64IF:       # %bb.0: # %start
59; RV64IF-NEXT:    lui a1, %hi(.LCPI1_0)
60; RV64IF-NEXT:    flw ft1, %lo(.LCPI1_0)(a1)
61; RV64IF-NEXT:    fmv.w.x ft0, a0
62; RV64IF-NEXT:    fle.s a0, ft1, ft0
63; RV64IF-NEXT:    lui a1, 524288
64; RV64IF-NEXT:    bnez a0, .LBB1_2
65; RV64IF-NEXT:  # %bb.1: # %start
66; RV64IF-NEXT:    lui a0, 524288
67; RV64IF-NEXT:    j .LBB1_3
68; RV64IF-NEXT:  .LBB1_2:
69; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
70; RV64IF-NEXT:  .LBB1_3: # %start
71; RV64IF-NEXT:    lui a2, %hi(.LCPI1_1)
72; RV64IF-NEXT:    flw ft1, %lo(.LCPI1_1)(a2)
73; RV64IF-NEXT:    flt.s a2, ft1, ft0
74; RV64IF-NEXT:    bnez a2, .LBB1_6
75; RV64IF-NEXT:  # %bb.4: # %start
76; RV64IF-NEXT:    feq.s a1, ft0, ft0
77; RV64IF-NEXT:    beqz a1, .LBB1_7
78; RV64IF-NEXT:  .LBB1_5: # %start
79; RV64IF-NEXT:    ret
80; RV64IF-NEXT:  .LBB1_6:
81; RV64IF-NEXT:    addiw a0, a1, -1
82; RV64IF-NEXT:    feq.s a1, ft0, ft0
83; RV64IF-NEXT:    bnez a1, .LBB1_5
84; RV64IF-NEXT:  .LBB1_7: # %start
85; RV64IF-NEXT:    mv a0, zero
86; RV64IF-NEXT:    ret
87start:
88  %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
89  ret i32 %0
90}
91declare i32 @llvm.fptosi.sat.i32.f32(float)
92
93; For RV64F, fcvt.lu.s is semantically equivalent to fcvt.wu.s in this case
94; because fptoui will produce poison if the result doesn't fit into an i32.
95define i32 @fcvt_wu_s(float %a) nounwind {
96; RV32IF-LABEL: fcvt_wu_s:
97; RV32IF:       # %bb.0:
98; RV32IF-NEXT:    fmv.w.x ft0, a0
99; RV32IF-NEXT:    fcvt.wu.s a0, ft0, rtz
100; RV32IF-NEXT:    ret
101;
102; RV64IF-LABEL: fcvt_wu_s:
103; RV64IF:       # %bb.0:
104; RV64IF-NEXT:    fmv.w.x ft0, a0
105; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
106; RV64IF-NEXT:    ret
107  %1 = fptoui float %a to i32
108  ret i32 %1
109}
110
111define i32 @fcvt_wu_s_sat(float %a) nounwind {
112; RV32IF-LABEL: fcvt_wu_s_sat:
113; RV32IF:       # %bb.0: # %start
114; RV32IF-NEXT:    fmv.w.x ft0, a0
115; RV32IF-NEXT:    fmv.w.x ft1, zero
116; RV32IF-NEXT:    fle.s a0, ft1, ft0
117; RV32IF-NEXT:    bnez a0, .LBB3_2
118; RV32IF-NEXT:  # %bb.1: # %start
119; RV32IF-NEXT:    mv a1, zero
120; RV32IF-NEXT:    j .LBB3_3
121; RV32IF-NEXT:  .LBB3_2:
122; RV32IF-NEXT:    fcvt.wu.s a1, ft0, rtz
123; RV32IF-NEXT:  .LBB3_3: # %start
124; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
125; RV32IF-NEXT:    flw ft1, %lo(.LCPI3_0)(a0)
126; RV32IF-NEXT:    flt.s a2, ft1, ft0
127; RV32IF-NEXT:    addi a0, zero, -1
128; RV32IF-NEXT:    bnez a2, .LBB3_5
129; RV32IF-NEXT:  # %bb.4: # %start
130; RV32IF-NEXT:    mv a0, a1
131; RV32IF-NEXT:  .LBB3_5: # %start
132; RV32IF-NEXT:    ret
133;
134; RV64IF-LABEL: fcvt_wu_s_sat:
135; RV64IF:       # %bb.0: # %start
136; RV64IF-NEXT:    fmv.w.x ft0, a0
137; RV64IF-NEXT:    fmv.w.x ft1, zero
138; RV64IF-NEXT:    fle.s a0, ft1, ft0
139; RV64IF-NEXT:    bnez a0, .LBB3_2
140; RV64IF-NEXT:  # %bb.1: # %start
141; RV64IF-NEXT:    mv a0, zero
142; RV64IF-NEXT:    j .LBB3_3
143; RV64IF-NEXT:  .LBB3_2:
144; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
145; RV64IF-NEXT:  .LBB3_3: # %start
146; RV64IF-NEXT:    lui a1, %hi(.LCPI3_0)
147; RV64IF-NEXT:    flw ft1, %lo(.LCPI3_0)(a1)
148; RV64IF-NEXT:    flt.s a1, ft1, ft0
149; RV64IF-NEXT:    beqz a1, .LBB3_5
150; RV64IF-NEXT:  # %bb.4:
151; RV64IF-NEXT:    addi a0, zero, -1
152; RV64IF-NEXT:    srli a0, a0, 32
153; RV64IF-NEXT:  .LBB3_5: # %start
154; RV64IF-NEXT:    ret
155start:
156  %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
157  ret i32 %0
158}
159declare i32 @llvm.fptoui.sat.i32.f32(float)
160
161define i32 @fmv_x_w(float %a, float %b) nounwind {
162; RV32IF-LABEL: fmv_x_w:
163; RV32IF:       # %bb.0:
164; RV32IF-NEXT:    fmv.w.x ft0, a1
165; RV32IF-NEXT:    fmv.w.x ft1, a0
166; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
167; RV32IF-NEXT:    fmv.x.w a0, ft0
168; RV32IF-NEXT:    ret
169;
170; RV64IF-LABEL: fmv_x_w:
171; RV64IF:       # %bb.0:
172; RV64IF-NEXT:    fmv.w.x ft0, a1
173; RV64IF-NEXT:    fmv.w.x ft1, a0
174; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
175; RV64IF-NEXT:    fmv.x.w a0, ft0
176; RV64IF-NEXT:    ret
177; Ensure fmv.x.w is generated even for a soft float calling convention
178  %1 = fadd float %a, %b
179  %2 = bitcast float %1 to i32
180  ret i32 %2
181}
182
183define float @fcvt_s_w(i32 %a) nounwind {
184; RV32IF-LABEL: fcvt_s_w:
185; RV32IF:       # %bb.0:
186; RV32IF-NEXT:    fcvt.s.w ft0, a0
187; RV32IF-NEXT:    fmv.x.w a0, ft0
188; RV32IF-NEXT:    ret
189;
190; RV64IF-LABEL: fcvt_s_w:
191; RV64IF:       # %bb.0:
192; RV64IF-NEXT:    fcvt.s.w ft0, a0
193; RV64IF-NEXT:    fmv.x.w a0, ft0
194; RV64IF-NEXT:    ret
195  %1 = sitofp i32 %a to float
196  ret float %1
197}
198
199define float @fcvt_s_wu(i32 %a) nounwind {
200; RV32IF-LABEL: fcvt_s_wu:
201; RV32IF:       # %bb.0:
202; RV32IF-NEXT:    fcvt.s.wu ft0, a0
203; RV32IF-NEXT:    fmv.x.w a0, ft0
204; RV32IF-NEXT:    ret
205;
206; RV64IF-LABEL: fcvt_s_wu:
207; RV64IF:       # %bb.0:
208; RV64IF-NEXT:    fcvt.s.wu ft0, a0
209; RV64IF-NEXT:    fmv.x.w a0, ft0
210; RV64IF-NEXT:    ret
211  %1 = uitofp i32 %a to float
212  ret float %1
213}
214
215define float @fmv_w_x(i32 %a, i32 %b) nounwind {
216; RV32IF-LABEL: fmv_w_x:
217; RV32IF:       # %bb.0:
218; RV32IF-NEXT:    fmv.w.x ft0, a0
219; RV32IF-NEXT:    fmv.w.x ft1, a1
220; RV32IF-NEXT:    fadd.s ft0, ft0, ft1
221; RV32IF-NEXT:    fmv.x.w a0, ft0
222; RV32IF-NEXT:    ret
223;
224; RV64IF-LABEL: fmv_w_x:
225; RV64IF:       # %bb.0:
226; RV64IF-NEXT:    fmv.w.x ft0, a0
227; RV64IF-NEXT:    fmv.w.x ft1, a1
228; RV64IF-NEXT:    fadd.s ft0, ft0, ft1
229; RV64IF-NEXT:    fmv.x.w a0, ft0
230; RV64IF-NEXT:    ret
231; Ensure fmv.w.x is generated even for a soft float calling convention
232  %1 = bitcast i32 %a to float
233  %2 = bitcast i32 %b to float
234  %3 = fadd float %1, %2
235  ret float %3
236}
237
238define i64 @fcvt_l_s(float %a) nounwind {
239; RV32IF-LABEL: fcvt_l_s:
240; RV32IF:       # %bb.0:
241; RV32IF-NEXT:    addi sp, sp, -16
242; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
243; RV32IF-NEXT:    call __fixsfdi@plt
244; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
245; RV32IF-NEXT:    addi sp, sp, 16
246; RV32IF-NEXT:    ret
247;
248; RV64IF-LABEL: fcvt_l_s:
249; RV64IF:       # %bb.0:
250; RV64IF-NEXT:    fmv.w.x ft0, a0
251; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
252; RV64IF-NEXT:    ret
253  %1 = fptosi float %a to i64
254  ret i64 %1
255}
256
257define i64 @fcvt_l_s_sat(float %a) nounwind {
258; RV32IF-LABEL: fcvt_l_s_sat:
259; RV32IF:       # %bb.0: # %start
260; RV32IF-NEXT:    addi sp, sp, -16
261; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
262; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
263; RV32IF-NEXT:    lui a1, %hi(.LCPI9_0)
264; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_0)(a1)
265; RV32IF-NEXT:    fmv.w.x ft1, a0
266; RV32IF-NEXT:    fsw ft1, 4(sp) # 4-byte Folded Spill
267; RV32IF-NEXT:    fle.s s0, ft0, ft1
268; RV32IF-NEXT:    call __fixsfdi@plt
269; RV32IF-NEXT:    mv a2, a0
270; RV32IF-NEXT:    bnez s0, .LBB9_2
271; RV32IF-NEXT:  # %bb.1: # %start
272; RV32IF-NEXT:    mv a2, zero
273; RV32IF-NEXT:  .LBB9_2: # %start
274; RV32IF-NEXT:    lui a0, %hi(.LCPI9_1)
275; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
276; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
277; RV32IF-NEXT:    flt.s a3, ft0, ft1
278; RV32IF-NEXT:    fmv.s ft0, ft1
279; RV32IF-NEXT:    addi a0, zero, -1
280; RV32IF-NEXT:    beqz a3, .LBB9_9
281; RV32IF-NEXT:  # %bb.3: # %start
282; RV32IF-NEXT:    feq.s a2, ft0, ft0
283; RV32IF-NEXT:    beqz a2, .LBB9_10
284; RV32IF-NEXT:  .LBB9_4: # %start
285; RV32IF-NEXT:    lui a4, 524288
286; RV32IF-NEXT:    beqz s0, .LBB9_11
287; RV32IF-NEXT:  .LBB9_5: # %start
288; RV32IF-NEXT:    bnez a3, .LBB9_12
289; RV32IF-NEXT:  .LBB9_6: # %start
290; RV32IF-NEXT:    bnez a2, .LBB9_8
291; RV32IF-NEXT:  .LBB9_7: # %start
292; RV32IF-NEXT:    mv a1, zero
293; RV32IF-NEXT:  .LBB9_8: # %start
294; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
295; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
296; RV32IF-NEXT:    addi sp, sp, 16
297; RV32IF-NEXT:    ret
298; RV32IF-NEXT:  .LBB9_9: # %start
299; RV32IF-NEXT:    mv a0, a2
300; RV32IF-NEXT:    feq.s a2, ft0, ft0
301; RV32IF-NEXT:    bnez a2, .LBB9_4
302; RV32IF-NEXT:  .LBB9_10: # %start
303; RV32IF-NEXT:    mv a0, zero
304; RV32IF-NEXT:    lui a4, 524288
305; RV32IF-NEXT:    bnez s0, .LBB9_5
306; RV32IF-NEXT:  .LBB9_11: # %start
307; RV32IF-NEXT:    lui a1, 524288
308; RV32IF-NEXT:    beqz a3, .LBB9_6
309; RV32IF-NEXT:  .LBB9_12:
310; RV32IF-NEXT:    addi a1, a4, -1
311; RV32IF-NEXT:    beqz a2, .LBB9_7
312; RV32IF-NEXT:    j .LBB9_8
313;
314; RV64IF-LABEL: fcvt_l_s_sat:
315; RV64IF:       # %bb.0: # %start
316; RV64IF-NEXT:    lui a1, %hi(.LCPI9_0)
317; RV64IF-NEXT:    flw ft1, %lo(.LCPI9_0)(a1)
318; RV64IF-NEXT:    fmv.w.x ft0, a0
319; RV64IF-NEXT:    fle.s a0, ft1, ft0
320; RV64IF-NEXT:    addi a1, zero, -1
321; RV64IF-NEXT:    bnez a0, .LBB9_2
322; RV64IF-NEXT:  # %bb.1: # %start
323; RV64IF-NEXT:    slli a0, a1, 63
324; RV64IF-NEXT:    j .LBB9_3
325; RV64IF-NEXT:  .LBB9_2:
326; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
327; RV64IF-NEXT:  .LBB9_3: # %start
328; RV64IF-NEXT:    lui a2, %hi(.LCPI9_1)
329; RV64IF-NEXT:    flw ft1, %lo(.LCPI9_1)(a2)
330; RV64IF-NEXT:    flt.s a2, ft1, ft0
331; RV64IF-NEXT:    bnez a2, .LBB9_6
332; RV64IF-NEXT:  # %bb.4: # %start
333; RV64IF-NEXT:    feq.s a1, ft0, ft0
334; RV64IF-NEXT:    beqz a1, .LBB9_7
335; RV64IF-NEXT:  .LBB9_5: # %start
336; RV64IF-NEXT:    ret
337; RV64IF-NEXT:  .LBB9_6:
338; RV64IF-NEXT:    srli a0, a1, 1
339; RV64IF-NEXT:    feq.s a1, ft0, ft0
340; RV64IF-NEXT:    bnez a1, .LBB9_5
341; RV64IF-NEXT:  .LBB9_7: # %start
342; RV64IF-NEXT:    mv a0, zero
343; RV64IF-NEXT:    ret
344start:
345  %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
346  ret i64 %0
347}
348declare i64 @llvm.fptosi.sat.i64.f32(float)
349
350define i64 @fcvt_lu_s(float %a) nounwind {
351; RV32IF-LABEL: fcvt_lu_s:
352; RV32IF:       # %bb.0:
353; RV32IF-NEXT:    addi sp, sp, -16
354; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
355; RV32IF-NEXT:    call __fixunssfdi@plt
356; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
357; RV32IF-NEXT:    addi sp, sp, 16
358; RV32IF-NEXT:    ret
359;
360; RV64IF-LABEL: fcvt_lu_s:
361; RV64IF:       # %bb.0:
362; RV64IF-NEXT:    fmv.w.x ft0, a0
363; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
364; RV64IF-NEXT:    ret
365  %1 = fptoui float %a to i64
366  ret i64 %1
367}
368
369define i64 @fcvt_lu_s_sat(float %a) nounwind {
370; RV32IF-LABEL: fcvt_lu_s_sat:
371; RV32IF:       # %bb.0: # %start
372; RV32IF-NEXT:    addi sp, sp, -16
373; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
374; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
375; RV32IF-NEXT:    fmv.w.x ft1, a0
376; RV32IF-NEXT:    fmv.w.x ft0, zero
377; RV32IF-NEXT:    fsw ft1, 4(sp) # 4-byte Folded Spill
378; RV32IF-NEXT:    fle.s s0, ft0, ft1
379; RV32IF-NEXT:    call __fixunssfdi@plt
380; RV32IF-NEXT:    mv a3, a0
381; RV32IF-NEXT:    bnez s0, .LBB11_2
382; RV32IF-NEXT:  # %bb.1: # %start
383; RV32IF-NEXT:    mv a3, zero
384; RV32IF-NEXT:  .LBB11_2: # %start
385; RV32IF-NEXT:    lui a0, %hi(.LCPI11_0)
386; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
387; RV32IF-NEXT:    flw ft1, 4(sp) # 4-byte Folded Reload
388; RV32IF-NEXT:    flt.s a4, ft0, ft1
389; RV32IF-NEXT:    addi a2, zero, -1
390; RV32IF-NEXT:    addi a0, zero, -1
391; RV32IF-NEXT:    beqz a4, .LBB11_7
392; RV32IF-NEXT:  # %bb.3: # %start
393; RV32IF-NEXT:    beqz s0, .LBB11_8
394; RV32IF-NEXT:  .LBB11_4: # %start
395; RV32IF-NEXT:    bnez a4, .LBB11_6
396; RV32IF-NEXT:  .LBB11_5: # %start
397; RV32IF-NEXT:    mv a2, a1
398; RV32IF-NEXT:  .LBB11_6: # %start
399; RV32IF-NEXT:    mv a1, a2
400; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
401; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
402; RV32IF-NEXT:    addi sp, sp, 16
403; RV32IF-NEXT:    ret
404; RV32IF-NEXT:  .LBB11_7: # %start
405; RV32IF-NEXT:    mv a0, a3
406; RV32IF-NEXT:    bnez s0, .LBB11_4
407; RV32IF-NEXT:  .LBB11_8: # %start
408; RV32IF-NEXT:    mv a1, zero
409; RV32IF-NEXT:    beqz a4, .LBB11_5
410; RV32IF-NEXT:    j .LBB11_6
411;
412; RV64IF-LABEL: fcvt_lu_s_sat:
413; RV64IF:       # %bb.0: # %start
414; RV64IF-NEXT:    fmv.w.x ft0, a0
415; RV64IF-NEXT:    fmv.w.x ft1, zero
416; RV64IF-NEXT:    fle.s a0, ft1, ft0
417; RV64IF-NEXT:    bnez a0, .LBB11_2
418; RV64IF-NEXT:  # %bb.1: # %start
419; RV64IF-NEXT:    mv a1, zero
420; RV64IF-NEXT:    j .LBB11_3
421; RV64IF-NEXT:  .LBB11_2:
422; RV64IF-NEXT:    fcvt.lu.s a1, ft0, rtz
423; RV64IF-NEXT:  .LBB11_3: # %start
424; RV64IF-NEXT:    lui a0, %hi(.LCPI11_0)
425; RV64IF-NEXT:    flw ft1, %lo(.LCPI11_0)(a0)
426; RV64IF-NEXT:    flt.s a2, ft1, ft0
427; RV64IF-NEXT:    addi a0, zero, -1
428; RV64IF-NEXT:    bnez a2, .LBB11_5
429; RV64IF-NEXT:  # %bb.4: # %start
430; RV64IF-NEXT:    mv a0, a1
431; RV64IF-NEXT:  .LBB11_5: # %start
432; RV64IF-NEXT:    ret
433start:
434  %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
435  ret i64 %0
436}
437declare i64 @llvm.fptoui.sat.i64.f32(float)
438
439define float @fcvt_s_l(i64 %a) nounwind {
440; RV32IF-LABEL: fcvt_s_l:
441; RV32IF:       # %bb.0:
442; RV32IF-NEXT:    addi sp, sp, -16
443; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
444; RV32IF-NEXT:    call __floatdisf@plt
445; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
446; RV32IF-NEXT:    addi sp, sp, 16
447; RV32IF-NEXT:    ret
448;
449; RV64IF-LABEL: fcvt_s_l:
450; RV64IF:       # %bb.0:
451; RV64IF-NEXT:    fcvt.s.l ft0, a0
452; RV64IF-NEXT:    fmv.x.w a0, ft0
453; RV64IF-NEXT:    ret
454  %1 = sitofp i64 %a to float
455  ret float %1
456}
457
458define float @fcvt_s_lu(i64 %a) nounwind {
459; RV32IF-LABEL: fcvt_s_lu:
460; RV32IF:       # %bb.0:
461; RV32IF-NEXT:    addi sp, sp, -16
462; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
463; RV32IF-NEXT:    call __floatundisf@plt
464; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
465; RV32IF-NEXT:    addi sp, sp, 16
466; RV32IF-NEXT:    ret
467;
468; RV64IF-LABEL: fcvt_s_lu:
469; RV64IF:       # %bb.0:
470; RV64IF-NEXT:    fcvt.s.lu ft0, a0
471; RV64IF-NEXT:    fmv.x.w a0, ft0
472; RV64IF-NEXT:    ret
473  %1 = uitofp i64 %a to float
474  ret float %1
475}
476
477define float @fcvt_s_w_i8(i8 signext %a) nounwind {
478; RV32IF-LABEL: fcvt_s_w_i8:
479; RV32IF:       # %bb.0:
480; RV32IF-NEXT:    fcvt.s.w ft0, a0
481; RV32IF-NEXT:    fmv.x.w a0, ft0
482; RV32IF-NEXT:    ret
483;
484; RV64IF-LABEL: fcvt_s_w_i8:
485; RV64IF:       # %bb.0:
486; RV64IF-NEXT:    fcvt.s.w ft0, a0
487; RV64IF-NEXT:    fmv.x.w a0, ft0
488; RV64IF-NEXT:    ret
489  %1 = sitofp i8 %a to float
490  ret float %1
491}
492
493define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
494; RV32IF-LABEL: fcvt_s_wu_i8:
495; RV32IF:       # %bb.0:
496; RV32IF-NEXT:    fcvt.s.wu ft0, a0
497; RV32IF-NEXT:    fmv.x.w a0, ft0
498; RV32IF-NEXT:    ret
499;
500; RV64IF-LABEL: fcvt_s_wu_i8:
501; RV64IF:       # %bb.0:
502; RV64IF-NEXT:    fcvt.s.wu ft0, a0
503; RV64IF-NEXT:    fmv.x.w a0, ft0
504; RV64IF-NEXT:    ret
505  %1 = uitofp i8 %a to float
506  ret float %1
507}
508
509define float @fcvt_s_w_i16(i16 signext %a) nounwind {
510; RV32IF-LABEL: fcvt_s_w_i16:
511; RV32IF:       # %bb.0:
512; RV32IF-NEXT:    fcvt.s.w ft0, a0
513; RV32IF-NEXT:    fmv.x.w a0, ft0
514; RV32IF-NEXT:    ret
515;
516; RV64IF-LABEL: fcvt_s_w_i16:
517; RV64IF:       # %bb.0:
518; RV64IF-NEXT:    fcvt.s.w ft0, a0
519; RV64IF-NEXT:    fmv.x.w a0, ft0
520; RV64IF-NEXT:    ret
521  %1 = sitofp i16 %a to float
522  ret float %1
523}
524
525define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
526; RV32IF-LABEL: fcvt_s_wu_i16:
527; RV32IF:       # %bb.0:
528; RV32IF-NEXT:    fcvt.s.wu ft0, a0
529; RV32IF-NEXT:    fmv.x.w a0, ft0
530; RV32IF-NEXT:    ret
531;
532; RV64IF-LABEL: fcvt_s_wu_i16:
533; RV64IF:       # %bb.0:
534; RV64IF-NEXT:    fcvt.s.wu ft0, a0
535; RV64IF-NEXT:    fmv.x.w a0, ft0
536; RV64IF-NEXT:    ret
537  %1 = uitofp i16 %a to float
538  ret float %1
539}
540