1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
4; RUN:   | FileCheck -check-prefixes=CHECKIF,RV32IF %s
5; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
6; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
7; RUN:   | FileCheck -check-prefixes=CHECKIF,RV64IF %s
8; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
9; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
10; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
11; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
12
13define float @fadd_s(float %a, float %b) nounwind strictfp {
14; CHECKIF-LABEL: fadd_s:
15; CHECKIF:       # %bb.0:
16; CHECKIF-NEXT:    fadd.s fa0, fa0, fa1
17; CHECKIF-NEXT:    ret
18;
19; RV32I-LABEL: fadd_s:
20; RV32I:       # %bb.0:
21; RV32I-NEXT:    addi sp, sp, -16
22; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
23; RV32I-NEXT:    call __addsf3@plt
24; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
25; RV32I-NEXT:    addi sp, sp, 16
26; RV32I-NEXT:    ret
27;
28; RV64I-LABEL: fadd_s:
29; RV64I:       # %bb.0:
30; RV64I-NEXT:    addi sp, sp, -16
31; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
32; RV64I-NEXT:    call __addsf3@plt
33; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
34; RV64I-NEXT:    addi sp, sp, 16
35; RV64I-NEXT:    ret
36  %1 = call float @llvm.experimental.constrained.fadd.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
37  ret float %1
38}
39declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
40
41define float @fsub_s(float %a, float %b) nounwind strictfp {
42; CHECKIF-LABEL: fsub_s:
43; CHECKIF:       # %bb.0:
44; CHECKIF-NEXT:    fsub.s fa0, fa0, fa1
45; CHECKIF-NEXT:    ret
46;
47; RV32I-LABEL: fsub_s:
48; RV32I:       # %bb.0:
49; RV32I-NEXT:    addi sp, sp, -16
50; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
51; RV32I-NEXT:    call __subsf3@plt
52; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
53; RV32I-NEXT:    addi sp, sp, 16
54; RV32I-NEXT:    ret
55;
56; RV64I-LABEL: fsub_s:
57; RV64I:       # %bb.0:
58; RV64I-NEXT:    addi sp, sp, -16
59; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
60; RV64I-NEXT:    call __subsf3@plt
61; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
62; RV64I-NEXT:    addi sp, sp, 16
63; RV64I-NEXT:    ret
64  %1 = call float @llvm.experimental.constrained.fsub.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
65  ret float %1
66}
67declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
68
69define float @fmul_s(float %a, float %b) nounwind strictfp {
70; CHECKIF-LABEL: fmul_s:
71; CHECKIF:       # %bb.0:
72; CHECKIF-NEXT:    fmul.s fa0, fa0, fa1
73; CHECKIF-NEXT:    ret
74;
75; RV32I-LABEL: fmul_s:
76; RV32I:       # %bb.0:
77; RV32I-NEXT:    addi sp, sp, -16
78; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
79; RV32I-NEXT:    call __mulsf3@plt
80; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
81; RV32I-NEXT:    addi sp, sp, 16
82; RV32I-NEXT:    ret
83;
84; RV64I-LABEL: fmul_s:
85; RV64I:       # %bb.0:
86; RV64I-NEXT:    addi sp, sp, -16
87; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
88; RV64I-NEXT:    call __mulsf3@plt
89; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
90; RV64I-NEXT:    addi sp, sp, 16
91; RV64I-NEXT:    ret
92  %1 = call float @llvm.experimental.constrained.fmul.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
93  ret float %1
94}
95declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)
96
97define float @fdiv_s(float %a, float %b) nounwind strictfp {
98; CHECKIF-LABEL: fdiv_s:
99; CHECKIF:       # %bb.0:
100; CHECKIF-NEXT:    fdiv.s fa0, fa0, fa1
101; CHECKIF-NEXT:    ret
102;
103; RV32I-LABEL: fdiv_s:
104; RV32I:       # %bb.0:
105; RV32I-NEXT:    addi sp, sp, -16
106; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
107; RV32I-NEXT:    call __divsf3@plt
108; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
109; RV32I-NEXT:    addi sp, sp, 16
110; RV32I-NEXT:    ret
111;
112; RV64I-LABEL: fdiv_s:
113; RV64I:       # %bb.0:
114; RV64I-NEXT:    addi sp, sp, -16
115; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
116; RV64I-NEXT:    call __divsf3@plt
117; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
118; RV64I-NEXT:    addi sp, sp, 16
119; RV64I-NEXT:    ret
120  %1 = call float @llvm.experimental.constrained.fdiv.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
121  ret float %1
122}
123declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)
124
125define float @fsqrt_s(float %a) nounwind strictfp {
126; CHECKIF-LABEL: fsqrt_s:
127; CHECKIF:       # %bb.0:
128; CHECKIF-NEXT:    fsqrt.s fa0, fa0
129; CHECKIF-NEXT:    ret
130;
131; RV32I-LABEL: fsqrt_s:
132; RV32I:       # %bb.0:
133; RV32I-NEXT:    addi sp, sp, -16
134; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
135; RV32I-NEXT:    call sqrtf@plt
136; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
137; RV32I-NEXT:    addi sp, sp, 16
138; RV32I-NEXT:    ret
139;
140; RV64I-LABEL: fsqrt_s:
141; RV64I:       # %bb.0:
142; RV64I-NEXT:    addi sp, sp, -16
143; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
144; RV64I-NEXT:    call sqrtf@plt
145; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
146; RV64I-NEXT:    addi sp, sp, 16
147; RV64I-NEXT:    ret
148  %1 = call float @llvm.experimental.constrained.sqrt.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
149  ret float %1
150}
151declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
152
153define float @fmin_s(float %a, float %b) nounwind strictfp {
154; RV32IF-LABEL: fmin_s:
155; RV32IF:       # %bb.0:
156; RV32IF-NEXT:    addi sp, sp, -16
157; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
158; RV32IF-NEXT:    call fminf@plt
159; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
160; RV32IF-NEXT:    addi sp, sp, 16
161; RV32IF-NEXT:    ret
162;
163; RV64IF-LABEL: fmin_s:
164; RV64IF:       # %bb.0:
165; RV64IF-NEXT:    addi sp, sp, -16
166; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
167; RV64IF-NEXT:    call fminf@plt
168; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
169; RV64IF-NEXT:    addi sp, sp, 16
170; RV64IF-NEXT:    ret
171;
172; RV32I-LABEL: fmin_s:
173; RV32I:       # %bb.0:
174; RV32I-NEXT:    addi sp, sp, -16
175; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
176; RV32I-NEXT:    call fminf@plt
177; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
178; RV32I-NEXT:    addi sp, sp, 16
179; RV32I-NEXT:    ret
180;
181; RV64I-LABEL: fmin_s:
182; RV64I:       # %bb.0:
183; RV64I-NEXT:    addi sp, sp, -16
184; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
185; RV64I-NEXT:    call fminf@plt
186; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
187; RV64I-NEXT:    addi sp, sp, 16
188; RV64I-NEXT:    ret
189  %1 = call float @llvm.experimental.constrained.minnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
190  ret float %1
191}
192declare float @llvm.experimental.constrained.minnum.f32(float, float, metadata) strictfp
193
194define float @fmax_s(float %a, float %b) nounwind strictfp {
195; RV32IF-LABEL: fmax_s:
196; RV32IF:       # %bb.0:
197; RV32IF-NEXT:    addi sp, sp, -16
198; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
199; RV32IF-NEXT:    call fmaxf@plt
200; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
201; RV32IF-NEXT:    addi sp, sp, 16
202; RV32IF-NEXT:    ret
203;
204; RV64IF-LABEL: fmax_s:
205; RV64IF:       # %bb.0:
206; RV64IF-NEXT:    addi sp, sp, -16
207; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
208; RV64IF-NEXT:    call fmaxf@plt
209; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
210; RV64IF-NEXT:    addi sp, sp, 16
211; RV64IF-NEXT:    ret
212;
213; RV32I-LABEL: fmax_s:
214; RV32I:       # %bb.0:
215; RV32I-NEXT:    addi sp, sp, -16
216; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
217; RV32I-NEXT:    call fmaxf@plt
218; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
219; RV32I-NEXT:    addi sp, sp, 16
220; RV32I-NEXT:    ret
221;
222; RV64I-LABEL: fmax_s:
223; RV64I:       # %bb.0:
224; RV64I-NEXT:    addi sp, sp, -16
225; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
226; RV64I-NEXT:    call fmaxf@plt
227; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
228; RV64I-NEXT:    addi sp, sp, 16
229; RV64I-NEXT:    ret
230  %1 = call float @llvm.experimental.constrained.maxnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
231  ret float %1
232}
233declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) strictfp
234
235define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp {
236; CHECKIF-LABEL: fmadd_s:
237; CHECKIF:       # %bb.0:
238; CHECKIF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
239; CHECKIF-NEXT:    ret
240;
241; RV32I-LABEL: fmadd_s:
242; RV32I:       # %bb.0:
243; RV32I-NEXT:    addi sp, sp, -16
244; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
245; RV32I-NEXT:    call fmaf@plt
246; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
247; RV32I-NEXT:    addi sp, sp, 16
248; RV32I-NEXT:    ret
249;
250; RV64I-LABEL: fmadd_s:
251; RV64I:       # %bb.0:
252; RV64I-NEXT:    addi sp, sp, -16
253; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
254; RV64I-NEXT:    call fmaf@plt
255; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
256; RV64I-NEXT:    addi sp, sp, 16
257; RV64I-NEXT:    ret
258  %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
259  ret float %1
260}
261declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp
262
263define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
264; CHECKIF-LABEL: fmsub_s:
265; CHECKIF:       # %bb.0:
266; CHECKIF-NEXT:    fmv.w.x ft0, zero
267; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
268; CHECKIF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
269; CHECKIF-NEXT:    ret
270;
271; RV32I-LABEL: fmsub_s:
272; RV32I:       # %bb.0:
273; RV32I-NEXT:    addi sp, sp, -16
274; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
275; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
276; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
277; RV32I-NEXT:    mv s0, a1
278; RV32I-NEXT:    mv s1, a0
279; RV32I-NEXT:    mv a0, a2
280; RV32I-NEXT:    li a1, 0
281; RV32I-NEXT:    call __addsf3@plt
282; RV32I-NEXT:    lui a1, 524288
283; RV32I-NEXT:    xor a2, a0, a1
284; RV32I-NEXT:    mv a0, s1
285; RV32I-NEXT:    mv a1, s0
286; RV32I-NEXT:    call fmaf@plt
287; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
288; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
289; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
290; RV32I-NEXT:    addi sp, sp, 16
291; RV32I-NEXT:    ret
292;
293; RV64I-LABEL: fmsub_s:
294; RV64I:       # %bb.0:
295; RV64I-NEXT:    addi sp, sp, -32
296; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
297; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
298; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
299; RV64I-NEXT:    mv s0, a1
300; RV64I-NEXT:    mv s1, a0
301; RV64I-NEXT:    mv a0, a2
302; RV64I-NEXT:    li a1, 0
303; RV64I-NEXT:    call __addsf3@plt
304; RV64I-NEXT:    lui a1, 524288
305; RV64I-NEXT:    xor a2, a0, a1
306; RV64I-NEXT:    mv a0, s1
307; RV64I-NEXT:    mv a1, s0
308; RV64I-NEXT:    call fmaf@plt
309; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
310; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
311; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
312; RV64I-NEXT:    addi sp, sp, 32
313; RV64I-NEXT:    ret
314  %c_ = fadd float 0.0, %c ; avoid negation using xor
315  %negc = fneg float %c_
316  %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
317  ret float %1
318}
319
320define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
321; CHECKIF-LABEL: fnmadd_s:
322; CHECKIF:       # %bb.0:
323; CHECKIF-NEXT:    fmv.w.x ft0, zero
324; CHECKIF-NEXT:    fadd.s ft1, fa0, ft0
325; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
326; CHECKIF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
327; CHECKIF-NEXT:    ret
328;
329; RV32I-LABEL: fnmadd_s:
330; RV32I:       # %bb.0:
331; RV32I-NEXT:    addi sp, sp, -16
332; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
333; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
334; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
335; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
336; RV32I-NEXT:    mv s0, a2
337; RV32I-NEXT:    mv s1, a1
338; RV32I-NEXT:    li a1, 0
339; RV32I-NEXT:    call __addsf3@plt
340; RV32I-NEXT:    mv s2, a0
341; RV32I-NEXT:    mv a0, s0
342; RV32I-NEXT:    li a1, 0
343; RV32I-NEXT:    call __addsf3@plt
344; RV32I-NEXT:    lui a2, 524288
345; RV32I-NEXT:    xor a1, s2, a2
346; RV32I-NEXT:    xor a2, a0, a2
347; RV32I-NEXT:    mv a0, a1
348; RV32I-NEXT:    mv a1, s1
349; RV32I-NEXT:    call fmaf@plt
350; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
351; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
352; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
353; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
354; RV32I-NEXT:    addi sp, sp, 16
355; RV32I-NEXT:    ret
356;
357; RV64I-LABEL: fnmadd_s:
358; RV64I:       # %bb.0:
359; RV64I-NEXT:    addi sp, sp, -32
360; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
361; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
362; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
363; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
364; RV64I-NEXT:    mv s0, a2
365; RV64I-NEXT:    mv s1, a1
366; RV64I-NEXT:    li a1, 0
367; RV64I-NEXT:    call __addsf3@plt
368; RV64I-NEXT:    mv s2, a0
369; RV64I-NEXT:    mv a0, s0
370; RV64I-NEXT:    li a1, 0
371; RV64I-NEXT:    call __addsf3@plt
372; RV64I-NEXT:    lui a2, 524288
373; RV64I-NEXT:    xor a1, s2, a2
374; RV64I-NEXT:    xor a2, a0, a2
375; RV64I-NEXT:    mv a0, a1
376; RV64I-NEXT:    mv a1, s1
377; RV64I-NEXT:    call fmaf@plt
378; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
379; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
380; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
381; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
382; RV64I-NEXT:    addi sp, sp, 32
383; RV64I-NEXT:    ret
384  %a_ = fadd float 0.0, %a
385  %c_ = fadd float 0.0, %c
386  %nega = fneg float %a_
387  %negc = fneg float %c_
388  %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
389  ret float %1
390}
391
392define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
393; CHECKIF-LABEL: fnmadd_s_2:
394; CHECKIF:       # %bb.0:
395; CHECKIF-NEXT:    fmv.w.x ft0, zero
396; CHECKIF-NEXT:    fadd.s ft1, fa1, ft0
397; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
398; CHECKIF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
399; CHECKIF-NEXT:    ret
400;
401; RV32I-LABEL: fnmadd_s_2:
402; RV32I:       # %bb.0:
403; RV32I-NEXT:    addi sp, sp, -16
404; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
405; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
406; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
407; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
408; RV32I-NEXT:    mv s0, a2
409; RV32I-NEXT:    mv s1, a0
410; RV32I-NEXT:    mv a0, a1
411; RV32I-NEXT:    li a1, 0
412; RV32I-NEXT:    call __addsf3@plt
413; RV32I-NEXT:    mv s2, a0
414; RV32I-NEXT:    mv a0, s0
415; RV32I-NEXT:    li a1, 0
416; RV32I-NEXT:    call __addsf3@plt
417; RV32I-NEXT:    lui a2, 524288
418; RV32I-NEXT:    xor a1, s2, a2
419; RV32I-NEXT:    xor a2, a0, a2
420; RV32I-NEXT:    mv a0, s1
421; RV32I-NEXT:    call fmaf@plt
422; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
423; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
424; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
425; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
426; RV32I-NEXT:    addi sp, sp, 16
427; RV32I-NEXT:    ret
428;
429; RV64I-LABEL: fnmadd_s_2:
430; RV64I:       # %bb.0:
431; RV64I-NEXT:    addi sp, sp, -32
432; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
433; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
434; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
435; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
436; RV64I-NEXT:    mv s0, a2
437; RV64I-NEXT:    mv s1, a0
438; RV64I-NEXT:    mv a0, a1
439; RV64I-NEXT:    li a1, 0
440; RV64I-NEXT:    call __addsf3@plt
441; RV64I-NEXT:    mv s2, a0
442; RV64I-NEXT:    mv a0, s0
443; RV64I-NEXT:    li a1, 0
444; RV64I-NEXT:    call __addsf3@plt
445; RV64I-NEXT:    lui a2, 524288
446; RV64I-NEXT:    xor a1, s2, a2
447; RV64I-NEXT:    xor a2, a0, a2
448; RV64I-NEXT:    mv a0, s1
449; RV64I-NEXT:    call fmaf@plt
450; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
451; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
452; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
453; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
454; RV64I-NEXT:    addi sp, sp, 32
455; RV64I-NEXT:    ret
456  %b_ = fadd float 0.0, %b
457  %c_ = fadd float 0.0, %c
458  %negb = fneg float %b_
459  %negc = fneg float %c_
460  %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %negb, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
461  ret float %1
462}
463
464define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
465; CHECKIF-LABEL: fnmsub_s:
466; CHECKIF:       # %bb.0:
467; CHECKIF-NEXT:    fmv.w.x ft0, zero
468; CHECKIF-NEXT:    fadd.s ft0, fa0, ft0
469; CHECKIF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
470; CHECKIF-NEXT:    ret
471;
472; RV32I-LABEL: fnmsub_s:
473; RV32I:       # %bb.0:
474; RV32I-NEXT:    addi sp, sp, -16
475; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
476; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
477; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
478; RV32I-NEXT:    mv s0, a2
479; RV32I-NEXT:    mv s1, a1
480; RV32I-NEXT:    li a1, 0
481; RV32I-NEXT:    call __addsf3@plt
482; RV32I-NEXT:    lui a1, 524288
483; RV32I-NEXT:    xor a0, a0, a1
484; RV32I-NEXT:    mv a1, s1
485; RV32I-NEXT:    mv a2, s0
486; RV32I-NEXT:    call fmaf@plt
487; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
488; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
489; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
490; RV32I-NEXT:    addi sp, sp, 16
491; RV32I-NEXT:    ret
492;
493; RV64I-LABEL: fnmsub_s:
494; RV64I:       # %bb.0:
495; RV64I-NEXT:    addi sp, sp, -32
496; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
497; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
498; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
499; RV64I-NEXT:    mv s0, a2
500; RV64I-NEXT:    mv s1, a1
501; RV64I-NEXT:    li a1, 0
502; RV64I-NEXT:    call __addsf3@plt
503; RV64I-NEXT:    lui a1, 524288
504; RV64I-NEXT:    xor a0, a0, a1
505; RV64I-NEXT:    mv a1, s1
506; RV64I-NEXT:    mv a2, s0
507; RV64I-NEXT:    call fmaf@plt
508; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
509; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
510; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
511; RV64I-NEXT:    addi sp, sp, 32
512; RV64I-NEXT:    ret
513  %a_ = fadd float 0.0, %a
514  %nega = fneg float %a_
515  %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
516  ret float %1
517}
518
519define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp {
520; CHECKIF-LABEL: fnmsub_s_2:
521; CHECKIF:       # %bb.0:
522; CHECKIF-NEXT:    fmv.w.x ft0, zero
523; CHECKIF-NEXT:    fadd.s ft0, fa1, ft0
524; CHECKIF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
525; CHECKIF-NEXT:    ret
526;
527; RV32I-LABEL: fnmsub_s_2:
528; RV32I:       # %bb.0:
529; RV32I-NEXT:    addi sp, sp, -16
530; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
531; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
532; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
533; RV32I-NEXT:    mv s0, a2
534; RV32I-NEXT:    mv s1, a0
535; RV32I-NEXT:    mv a0, a1
536; RV32I-NEXT:    li a1, 0
537; RV32I-NEXT:    call __addsf3@plt
538; RV32I-NEXT:    lui a1, 524288
539; RV32I-NEXT:    xor a1, a0, a1
540; RV32I-NEXT:    mv a0, s1
541; RV32I-NEXT:    mv a2, s0
542; RV32I-NEXT:    call fmaf@plt
543; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
544; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
545; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
546; RV32I-NEXT:    addi sp, sp, 16
547; RV32I-NEXT:    ret
548;
549; RV64I-LABEL: fnmsub_s_2:
550; RV64I:       # %bb.0:
551; RV64I-NEXT:    addi sp, sp, -32
552; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
553; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
554; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
555; RV64I-NEXT:    mv s0, a2
556; RV64I-NEXT:    mv s1, a0
557; RV64I-NEXT:    mv a0, a1
558; RV64I-NEXT:    li a1, 0
559; RV64I-NEXT:    call __addsf3@plt
560; RV64I-NEXT:    lui a1, 524288
561; RV64I-NEXT:    xor a1, a0, a1
562; RV64I-NEXT:    mv a0, s1
563; RV64I-NEXT:    mv a2, s0
564; RV64I-NEXT:    call fmaf@plt
565; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
566; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
567; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
568; RV64I-NEXT:    addi sp, sp, 32
569; RV64I-NEXT:    ret
570  %b_ = fadd float 0.0, %b
571  %negb = fneg float %b_
572  %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %negb, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
573  ret float %1
574}
575