1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefixes=CHECK,NOZBS,RV32,RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefixes=CHECK,NOZBS,RV64,RV64I
6; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
7; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
8; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
9; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
10
11define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
12; CHECK-LABEL: bittest_7_i32:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    andi a0, a0, 128
15; CHECK-NEXT:    seqz a0, a0
16; CHECK-NEXT:    ret
17  %shr = lshr i32 %a, 7
18  %not = xor i32 %shr, -1
19  %and = and i32 %not, 1
20  ret i32 %and
21}
22
23define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
24; CHECK-LABEL: bittest_10_i32:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    andi a0, a0, 1024
27; CHECK-NEXT:    seqz a0, a0
28; CHECK-NEXT:    ret
29  %shr = lshr i32 %a, 10
30  %not = xor i32 %shr, -1
31  %and = and i32 %not, 1
32  ret i32 %and
33}
34
35define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
36; NOZBS-LABEL: bittest_11_i32:
37; NOZBS:       # %bb.0:
38; NOZBS-NEXT:    srli a0, a0, 11
39; NOZBS-NEXT:    not a0, a0
40; NOZBS-NEXT:    andi a0, a0, 1
41; NOZBS-NEXT:    ret
42;
43; ZBS-LABEL: bittest_11_i32:
44; ZBS:       # %bb.0:
45; ZBS-NEXT:    bexti a0, a0, 11
46; ZBS-NEXT:    xori a0, a0, 1
47; ZBS-NEXT:    ret
48  %shr = lshr i32 %a, 11
49  %not = xor i32 %shr, -1
50  %and = and i32 %not, 1
51  ret i32 %and
52}
53
54define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
55; RV32-LABEL: bittest_31_i32:
56; RV32:       # %bb.0:
57; RV32-NEXT:    not a0, a0
58; RV32-NEXT:    srli a0, a0, 31
59; RV32-NEXT:    ret
60;
61; RV64-LABEL: bittest_31_i32:
62; RV64:       # %bb.0:
63; RV64-NEXT:    not a0, a0
64; RV64-NEXT:    srliw a0, a0, 31
65; RV64-NEXT:    ret
66  %shr = lshr i32 %a, 31
67  %not = xor i32 %shr, -1
68  %and = and i32 %not, 1
69  ret i32 %and
70}
71
72define i64 @bittest_7_i64(i64 %a) nounwind {
73; RV32-LABEL: bittest_7_i64:
74; RV32:       # %bb.0:
75; RV32-NEXT:    andi a0, a0, 128
76; RV32-NEXT:    seqz a0, a0
77; RV32-NEXT:    li a1, 0
78; RV32-NEXT:    ret
79;
80; RV64-LABEL: bittest_7_i64:
81; RV64:       # %bb.0:
82; RV64-NEXT:    andi a0, a0, 128
83; RV64-NEXT:    seqz a0, a0
84; RV64-NEXT:    ret
85  %shr = lshr i64 %a, 7
86  %not = xor i64 %shr, -1
87  %and = and i64 %not, 1
88  ret i64 %and
89}
90
91define i64 @bittest_10_i64(i64 %a) nounwind {
92; RV32-LABEL: bittest_10_i64:
93; RV32:       # %bb.0:
94; RV32-NEXT:    andi a0, a0, 1024
95; RV32-NEXT:    seqz a0, a0
96; RV32-NEXT:    li a1, 0
97; RV32-NEXT:    ret
98;
99; RV64-LABEL: bittest_10_i64:
100; RV64:       # %bb.0:
101; RV64-NEXT:    andi a0, a0, 1024
102; RV64-NEXT:    seqz a0, a0
103; RV64-NEXT:    ret
104  %shr = lshr i64 %a, 10
105  %not = xor i64 %shr, -1
106  %and = and i64 %not, 1
107  ret i64 %and
108}
109
110define i64 @bittest_11_i64(i64 %a) nounwind {
111; RV32I-LABEL: bittest_11_i64:
112; RV32I:       # %bb.0:
113; RV32I-NEXT:    srli a0, a0, 11
114; RV32I-NEXT:    not a0, a0
115; RV32I-NEXT:    andi a0, a0, 1
116; RV32I-NEXT:    li a1, 0
117; RV32I-NEXT:    ret
118;
119; RV64I-LABEL: bittest_11_i64:
120; RV64I:       # %bb.0:
121; RV64I-NEXT:    srli a0, a0, 11
122; RV64I-NEXT:    not a0, a0
123; RV64I-NEXT:    andi a0, a0, 1
124; RV64I-NEXT:    ret
125;
126; RV32ZBS-LABEL: bittest_11_i64:
127; RV32ZBS:       # %bb.0:
128; RV32ZBS-NEXT:    bexti a0, a0, 11
129; RV32ZBS-NEXT:    xori a0, a0, 1
130; RV32ZBS-NEXT:    li a1, 0
131; RV32ZBS-NEXT:    ret
132;
133; RV64ZBS-LABEL: bittest_11_i64:
134; RV64ZBS:       # %bb.0:
135; RV64ZBS-NEXT:    bexti a0, a0, 11
136; RV64ZBS-NEXT:    xori a0, a0, 1
137; RV64ZBS-NEXT:    ret
138  %shr = lshr i64 %a, 11
139  %not = xor i64 %shr, -1
140  %and = and i64 %not, 1
141  ret i64 %and
142}
143
144define i64 @bittest_31_i64(i64 %a) nounwind {
145; RV32-LABEL: bittest_31_i64:
146; RV32:       # %bb.0:
147; RV32-NEXT:    not a0, a0
148; RV32-NEXT:    srli a0, a0, 31
149; RV32-NEXT:    li a1, 0
150; RV32-NEXT:    ret
151;
152; RV64I-LABEL: bittest_31_i64:
153; RV64I:       # %bb.0:
154; RV64I-NEXT:    srli a0, a0, 31
155; RV64I-NEXT:    not a0, a0
156; RV64I-NEXT:    andi a0, a0, 1
157; RV64I-NEXT:    ret
158;
159; RV64ZBS-LABEL: bittest_31_i64:
160; RV64ZBS:       # %bb.0:
161; RV64ZBS-NEXT:    bexti a0, a0, 31
162; RV64ZBS-NEXT:    xori a0, a0, 1
163; RV64ZBS-NEXT:    ret
164  %shr = lshr i64 %a, 31
165  %not = xor i64 %shr, -1
166  %and = and i64 %not, 1
167  ret i64 %and
168}
169
170define i64 @bittest_32_i64(i64 %a) nounwind {
171; RV32-LABEL: bittest_32_i64:
172; RV32:       # %bb.0:
173; RV32-NEXT:    not a0, a1
174; RV32-NEXT:    andi a0, a0, 1
175; RV32-NEXT:    li a1, 0
176; RV32-NEXT:    ret
177;
178; RV64I-LABEL: bittest_32_i64:
179; RV64I:       # %bb.0:
180; RV64I-NEXT:    srli a0, a0, 32
181; RV64I-NEXT:    not a0, a0
182; RV64I-NEXT:    andi a0, a0, 1
183; RV64I-NEXT:    ret
184;
185; RV64ZBS-LABEL: bittest_32_i64:
186; RV64ZBS:       # %bb.0:
187; RV64ZBS-NEXT:    bexti a0, a0, 32
188; RV64ZBS-NEXT:    xori a0, a0, 1
189; RV64ZBS-NEXT:    ret
190  %shr = lshr i64 %a, 32
191  %not = xor i64 %shr, -1
192  %and = and i64 %not, 1
193  ret i64 %and
194}
195
196define i64 @bittest_63_i64(i64 %a) nounwind {
197; RV32-LABEL: bittest_63_i64:
198; RV32:       # %bb.0:
199; RV32-NEXT:    not a0, a1
200; RV32-NEXT:    srli a0, a0, 31
201; RV32-NEXT:    li a1, 0
202; RV32-NEXT:    ret
203;
204; RV64-LABEL: bittest_63_i64:
205; RV64:       # %bb.0:
206; RV64-NEXT:    not a0, a0
207; RV64-NEXT:    srli a0, a0, 63
208; RV64-NEXT:    ret
209  %shr = lshr i64 %a, 63
210  %not = xor i64 %shr, -1
211  %and = and i64 %not, 1
212  ret i64 %and
213}
214