1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32,RV32I 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefixes=CHECK,RV64,RV64I 6; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \ 7; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS 8; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \ 9; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS 10 11define signext i32 @bittest_7_i32(i32 signext %a) nounwind { 12; CHECK-LABEL: bittest_7_i32: 13; CHECK: # %bb.0: 14; CHECK-NEXT: andi a0, a0, 128 15; CHECK-NEXT: seqz a0, a0 16; CHECK-NEXT: ret 17 %shr = lshr i32 %a, 7 18 %not = xor i32 %shr, -1 19 %and = and i32 %not, 1 20 ret i32 %and 21} 22 23define signext i32 @bittest_10_i32(i32 signext %a) nounwind { 24; CHECK-LABEL: bittest_10_i32: 25; CHECK: # %bb.0: 26; CHECK-NEXT: andi a0, a0, 1024 27; CHECK-NEXT: seqz a0, a0 28; CHECK-NEXT: ret 29 %shr = lshr i32 %a, 10 30 %not = xor i32 %shr, -1 31 %and = and i32 %not, 1 32 ret i32 %and 33} 34 35define signext i32 @bittest_11_i32(i32 signext %a) nounwind { 36; RV32I-LABEL: bittest_11_i32: 37; RV32I: # %bb.0: 38; RV32I-NEXT: not a0, a0 39; RV32I-NEXT: slli a0, a0, 20 40; RV32I-NEXT: srli a0, a0, 31 41; RV32I-NEXT: ret 42; 43; RV64I-LABEL: bittest_11_i32: 44; RV64I: # %bb.0: 45; RV64I-NEXT: not a0, a0 46; RV64I-NEXT: slli a0, a0, 52 47; RV64I-NEXT: srli a0, a0, 63 48; RV64I-NEXT: ret 49; 50; ZBS-LABEL: bittest_11_i32: 51; ZBS: # %bb.0: 52; ZBS-NEXT: not a0, a0 53; ZBS-NEXT: bexti a0, a0, 11 54; ZBS-NEXT: ret 55 %shr = lshr i32 %a, 11 56 %not = xor i32 %shr, -1 57 %and = and i32 %not, 1 58 ret i32 %and 59} 60 61define signext i32 @bittest_31_i32(i32 signext %a) nounwind { 62; RV32-LABEL: bittest_31_i32: 63; RV32: # %bb.0: 64; RV32-NEXT: not a0, a0 65; RV32-NEXT: srli a0, a0, 31 66; RV32-NEXT: ret 67; 68; RV64-LABEL: bittest_31_i32: 69; RV64: # %bb.0: 70; RV64-NEXT: not a0, a0 71; RV64-NEXT: srliw a0, a0, 31 72; RV64-NEXT: ret 73 %shr = lshr i32 %a, 31 74 %not = xor i32 %shr, -1 75 %and = and i32 %not, 1 76 ret i32 %and 77} 78 79define i64 @bittest_7_i64(i64 %a) nounwind { 80; RV32-LABEL: bittest_7_i64: 81; RV32: # %bb.0: 82; RV32-NEXT: andi a0, a0, 128 83; RV32-NEXT: seqz a0, a0 84; RV32-NEXT: li a1, 0 85; RV32-NEXT: ret 86; 87; RV64-LABEL: bittest_7_i64: 88; RV64: # %bb.0: 89; RV64-NEXT: andi a0, a0, 128 90; RV64-NEXT: seqz a0, a0 91; RV64-NEXT: ret 92 %shr = lshr i64 %a, 7 93 %not = xor i64 %shr, -1 94 %and = and i64 %not, 1 95 ret i64 %and 96} 97 98define i64 @bittest_10_i64(i64 %a) nounwind { 99; RV32-LABEL: bittest_10_i64: 100; RV32: # %bb.0: 101; RV32-NEXT: andi a0, a0, 1024 102; RV32-NEXT: seqz a0, a0 103; RV32-NEXT: li a1, 0 104; RV32-NEXT: ret 105; 106; RV64-LABEL: bittest_10_i64: 107; RV64: # %bb.0: 108; RV64-NEXT: andi a0, a0, 1024 109; RV64-NEXT: seqz a0, a0 110; RV64-NEXT: ret 111 %shr = lshr i64 %a, 10 112 %not = xor i64 %shr, -1 113 %and = and i64 %not, 1 114 ret i64 %and 115} 116 117define i64 @bittest_11_i64(i64 %a) nounwind { 118; RV32I-LABEL: bittest_11_i64: 119; RV32I: # %bb.0: 120; RV32I-NEXT: not a0, a0 121; RV32I-NEXT: slli a0, a0, 20 122; RV32I-NEXT: srli a0, a0, 31 123; RV32I-NEXT: li a1, 0 124; RV32I-NEXT: ret 125; 126; RV64I-LABEL: bittest_11_i64: 127; RV64I: # %bb.0: 128; RV64I-NEXT: not a0, a0 129; RV64I-NEXT: slli a0, a0, 52 130; RV64I-NEXT: srli a0, a0, 63 131; RV64I-NEXT: ret 132; 133; RV32ZBS-LABEL: bittest_11_i64: 134; RV32ZBS: # %bb.0: 135; RV32ZBS-NEXT: not a0, a0 136; RV32ZBS-NEXT: bexti a0, a0, 11 137; RV32ZBS-NEXT: li a1, 0 138; RV32ZBS-NEXT: ret 139; 140; RV64ZBS-LABEL: bittest_11_i64: 141; RV64ZBS: # %bb.0: 142; RV64ZBS-NEXT: not a0, a0 143; RV64ZBS-NEXT: bexti a0, a0, 11 144; RV64ZBS-NEXT: ret 145 %shr = lshr i64 %a, 11 146 %not = xor i64 %shr, -1 147 %and = and i64 %not, 1 148 ret i64 %and 149} 150 151define i64 @bittest_31_i64(i64 %a) nounwind { 152; RV32-LABEL: bittest_31_i64: 153; RV32: # %bb.0: 154; RV32-NEXT: not a0, a0 155; RV32-NEXT: srli a0, a0, 31 156; RV32-NEXT: li a1, 0 157; RV32-NEXT: ret 158; 159; RV64-LABEL: bittest_31_i64: 160; RV64: # %bb.0: 161; RV64-NEXT: not a0, a0 162; RV64-NEXT: srliw a0, a0, 31 163; RV64-NEXT: ret 164 %shr = lshr i64 %a, 31 165 %not = xor i64 %shr, -1 166 %and = and i64 %not, 1 167 ret i64 %and 168} 169 170define i64 @bittest_32_i64(i64 %a) nounwind { 171; RV32-LABEL: bittest_32_i64: 172; RV32: # %bb.0: 173; RV32-NEXT: not a0, a1 174; RV32-NEXT: andi a0, a0, 1 175; RV32-NEXT: li a1, 0 176; RV32-NEXT: ret 177; 178; RV64I-LABEL: bittest_32_i64: 179; RV64I: # %bb.0: 180; RV64I-NEXT: not a0, a0 181; RV64I-NEXT: slli a0, a0, 31 182; RV64I-NEXT: srli a0, a0, 63 183; RV64I-NEXT: ret 184; 185; RV64ZBS-LABEL: bittest_32_i64: 186; RV64ZBS: # %bb.0: 187; RV64ZBS-NEXT: not a0, a0 188; RV64ZBS-NEXT: bexti a0, a0, 32 189; RV64ZBS-NEXT: ret 190 %shr = lshr i64 %a, 32 191 %not = xor i64 %shr, -1 192 %and = and i64 %not, 1 193 ret i64 %and 194} 195 196define i64 @bittest_63_i64(i64 %a) nounwind { 197; RV32-LABEL: bittest_63_i64: 198; RV32: # %bb.0: 199; RV32-NEXT: not a0, a1 200; RV32-NEXT: srli a0, a0, 31 201; RV32-NEXT: li a1, 0 202; RV32-NEXT: ret 203; 204; RV64-LABEL: bittest_63_i64: 205; RV64: # %bb.0: 206; RV64-NEXT: not a0, a0 207; RV64-NEXT: srli a0, a0, 63 208; RV64-NEXT: ret 209 %shr = lshr i64 %a, 63 210 %not = xor i64 %shr, -1 211 %and = and i64 %not, 1 212 ret i64 %and 213} 214 215; Make sure we use (andi (srl X, Y), 1) or bext. 216define i1 @bittest_constant_by_var_shr_i32(i32 signext %b) nounwind { 217; RV32I-LABEL: bittest_constant_by_var_shr_i32: 218; RV32I: # %bb.0: 219; RV32I-NEXT: lui a1, 301408 220; RV32I-NEXT: addi a1, a1, 722 221; RV32I-NEXT: srl a0, a1, a0 222; RV32I-NEXT: andi a0, a0, 1 223; RV32I-NEXT: ret 224; 225; RV64I-LABEL: bittest_constant_by_var_shr_i32: 226; RV64I: # %bb.0: 227; RV64I-NEXT: lui a1, 301408 228; RV64I-NEXT: addiw a1, a1, 722 229; RV64I-NEXT: srlw a0, a1, a0 230; RV64I-NEXT: andi a0, a0, 1 231; RV64I-NEXT: ret 232; 233; RV32ZBS-LABEL: bittest_constant_by_var_shr_i32: 234; RV32ZBS: # %bb.0: 235; RV32ZBS-NEXT: lui a1, 301408 236; RV32ZBS-NEXT: addi a1, a1, 722 237; RV32ZBS-NEXT: bext a0, a1, a0 238; RV32ZBS-NEXT: ret 239; 240; RV64ZBS-LABEL: bittest_constant_by_var_shr_i32: 241; RV64ZBS: # %bb.0: 242; RV64ZBS-NEXT: lui a1, 301408 243; RV64ZBS-NEXT: addiw a1, a1, 722 244; RV64ZBS-NEXT: bext a0, a1, a0 245; RV64ZBS-NEXT: ret 246 %shl = lshr i32 1234567890, %b 247 %and = and i32 %shl, 1 248 %cmp = icmp ne i32 %and, 0 249 ret i1 %cmp 250} 251 252; Make sure we use (andi (srl X, Y), 1) or bext. 253define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind { 254; RV32I-LABEL: bittest_constant_by_var_shl_i32: 255; RV32I: # %bb.0: 256; RV32I-NEXT: lui a1, 301408 257; RV32I-NEXT: addi a1, a1, 722 258; RV32I-NEXT: srl a0, a1, a0 259; RV32I-NEXT: andi a0, a0, 1 260; RV32I-NEXT: ret 261; 262; RV64I-LABEL: bittest_constant_by_var_shl_i32: 263; RV64I: # %bb.0: 264; RV64I-NEXT: lui a1, 301408 265; RV64I-NEXT: addiw a1, a1, 722 266; RV64I-NEXT: srlw a0, a1, a0 267; RV64I-NEXT: andi a0, a0, 1 268; RV64I-NEXT: ret 269; 270; RV32ZBS-LABEL: bittest_constant_by_var_shl_i32: 271; RV32ZBS: # %bb.0: 272; RV32ZBS-NEXT: lui a1, 301408 273; RV32ZBS-NEXT: addi a1, a1, 722 274; RV32ZBS-NEXT: bext a0, a1, a0 275; RV32ZBS-NEXT: ret 276; 277; RV64ZBS-LABEL: bittest_constant_by_var_shl_i32: 278; RV64ZBS: # %bb.0: 279; RV64ZBS-NEXT: lui a1, 301408 280; RV64ZBS-NEXT: addiw a1, a1, 722 281; RV64ZBS-NEXT: bext a0, a1, a0 282; RV64ZBS-NEXT: ret 283 %shl = shl i32 1, %b 284 %and = and i32 %shl, 1234567890 285 %cmp = icmp ne i32 %and, 0 286 ret i1 %cmp 287} 288 289; Make sure we use (andi (srl X, Y), 1) or bext. 290define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind { 291; RV32-LABEL: bittest_constant_by_var_shr_i64: 292; RV32: # %bb.0: 293; RV32-NEXT: addi a1, a0, -32 294; RV32-NEXT: bltz a1, .LBB12_2 295; RV32-NEXT: # %bb.1: 296; RV32-NEXT: andi a0, zero, 1 297; RV32-NEXT: ret 298; RV32-NEXT: .LBB12_2: 299; RV32-NEXT: lui a1, 301408 300; RV32-NEXT: addi a1, a1, 722 301; RV32-NEXT: srl a0, a1, a0 302; RV32-NEXT: andi a0, a0, 1 303; RV32-NEXT: ret 304; 305; RV64I-LABEL: bittest_constant_by_var_shr_i64: 306; RV64I: # %bb.0: 307; RV64I-NEXT: lui a1, 301408 308; RV64I-NEXT: addiw a1, a1, 722 309; RV64I-NEXT: srl a0, a1, a0 310; RV64I-NEXT: andi a0, a0, 1 311; RV64I-NEXT: ret 312; 313; RV64ZBS-LABEL: bittest_constant_by_var_shr_i64: 314; RV64ZBS: # %bb.0: 315; RV64ZBS-NEXT: lui a1, 301408 316; RV64ZBS-NEXT: addiw a1, a1, 722 317; RV64ZBS-NEXT: bext a0, a1, a0 318; RV64ZBS-NEXT: ret 319 %shl = lshr i64 1234567890, %b 320 %and = and i64 %shl, 1 321 %cmp = icmp ne i64 %and, 0 322 ret i1 %cmp 323} 324 325; Make sure we use (andi (srl X, Y), 1) or bext. 326define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind { 327; RV32-LABEL: bittest_constant_by_var_shl_i64: 328; RV32: # %bb.0: 329; RV32-NEXT: addi a1, a0, -32 330; RV32-NEXT: bltz a1, .LBB13_2 331; RV32-NEXT: # %bb.1: 332; RV32-NEXT: andi a0, zero, 1 333; RV32-NEXT: ret 334; RV32-NEXT: .LBB13_2: 335; RV32-NEXT: lui a1, 301408 336; RV32-NEXT: addi a1, a1, 722 337; RV32-NEXT: srl a0, a1, a0 338; RV32-NEXT: andi a0, a0, 1 339; RV32-NEXT: ret 340; 341; RV64I-LABEL: bittest_constant_by_var_shl_i64: 342; RV64I: # %bb.0: 343; RV64I-NEXT: lui a1, 301408 344; RV64I-NEXT: addiw a1, a1, 722 345; RV64I-NEXT: srl a0, a1, a0 346; RV64I-NEXT: andi a0, a0, 1 347; RV64I-NEXT: ret 348; 349; RV64ZBS-LABEL: bittest_constant_by_var_shl_i64: 350; RV64ZBS: # %bb.0: 351; RV64ZBS-NEXT: lui a1, 301408 352; RV64ZBS-NEXT: addiw a1, a1, 722 353; RV64ZBS-NEXT: bext a0, a1, a0 354; RV64ZBS-NEXT: ret 355 %shl = shl i64 1, %b 356 %and = and i64 %shl, 1234567890 357 %cmp = icmp ne i64 %and, 0 358 ret i1 %cmp 359} 360 361; We want to use (andi (srl X, Y), 1) or bext before the beqz. 362define void @bittest_switch(i32 signext %0) { 363; RV32I-LABEL: bittest_switch: 364; RV32I: # %bb.0: 365; RV32I-NEXT: li a1, 31 366; RV32I-NEXT: bltu a1, a0, .LBB14_3 367; RV32I-NEXT: # %bb.1: 368; RV32I-NEXT: lui a1, 524291 369; RV32I-NEXT: addi a1, a1, 768 370; RV32I-NEXT: srl a0, a1, a0 371; RV32I-NEXT: andi a0, a0, 1 372; RV32I-NEXT: beqz a0, .LBB14_3 373; RV32I-NEXT: # %bb.2: 374; RV32I-NEXT: tail bar@plt 375; RV32I-NEXT: .LBB14_3: 376; RV32I-NEXT: ret 377; 378; RV64I-LABEL: bittest_switch: 379; RV64I: # %bb.0: 380; RV64I-NEXT: li a1, 31 381; RV64I-NEXT: bltu a1, a0, .LBB14_3 382; RV64I-NEXT: # %bb.1: 383; RV64I-NEXT: lui a1, 2048 384; RV64I-NEXT: addiw a1, a1, 51 385; RV64I-NEXT: slli a1, a1, 8 386; RV64I-NEXT: srl a0, a1, a0 387; RV64I-NEXT: andi a0, a0, 1 388; RV64I-NEXT: beqz a0, .LBB14_3 389; RV64I-NEXT: # %bb.2: 390; RV64I-NEXT: tail bar@plt 391; RV64I-NEXT: .LBB14_3: 392; RV64I-NEXT: ret 393; 394; RV32ZBS-LABEL: bittest_switch: 395; RV32ZBS: # %bb.0: 396; RV32ZBS-NEXT: li a1, 31 397; RV32ZBS-NEXT: bltu a1, a0, .LBB14_3 398; RV32ZBS-NEXT: # %bb.1: 399; RV32ZBS-NEXT: lui a1, 524291 400; RV32ZBS-NEXT: addi a1, a1, 768 401; RV32ZBS-NEXT: bext a0, a1, a0 402; RV32ZBS-NEXT: beqz a0, .LBB14_3 403; RV32ZBS-NEXT: # %bb.2: 404; RV32ZBS-NEXT: tail bar@plt 405; RV32ZBS-NEXT: .LBB14_3: 406; RV32ZBS-NEXT: ret 407; 408; RV64ZBS-LABEL: bittest_switch: 409; RV64ZBS: # %bb.0: 410; RV64ZBS-NEXT: li a1, 31 411; RV64ZBS-NEXT: bltu a1, a0, .LBB14_3 412; RV64ZBS-NEXT: # %bb.1: 413; RV64ZBS-NEXT: lui a1, 2048 414; RV64ZBS-NEXT: addiw a1, a1, 51 415; RV64ZBS-NEXT: slli a1, a1, 8 416; RV64ZBS-NEXT: bext a0, a1, a0 417; RV64ZBS-NEXT: beqz a0, .LBB14_3 418; RV64ZBS-NEXT: # %bb.2: 419; RV64ZBS-NEXT: tail bar@plt 420; RV64ZBS-NEXT: .LBB14_3: 421; RV64ZBS-NEXT: ret 422 switch i32 %0, label %3 [ 423 i32 8, label %2 424 i32 9, label %2 425 i32 12, label %2 426 i32 13, label %2 427 i32 31, label %2 428 ] 429 4302: 431 tail call void @bar() 432 br label %3 433 4343: 435 ret void 436} 437 438declare void @bar() 439 440define signext i32 @bit_10_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 441; CHECK-LABEL: bit_10_z_select_i32: 442; CHECK: # %bb.0: 443; CHECK-NEXT: andi a3, a0, 1024 444; CHECK-NEXT: mv a0, a1 445; CHECK-NEXT: beqz a3, .LBB15_2 446; CHECK-NEXT: # %bb.1: 447; CHECK-NEXT: mv a0, a2 448; CHECK-NEXT: .LBB15_2: 449; CHECK-NEXT: ret 450 %1 = and i32 %a, 1024 451 %2 = icmp eq i32 %1, 0 452 %3 = select i1 %2, i32 %b, i32 %c 453 ret i32 %3 454} 455 456define signext i32 @bit_10_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 457; RV32-LABEL: bit_10_nz_select_i32: 458; RV32: # %bb.0: 459; RV32-NEXT: slli a3, a0, 21 460; RV32-NEXT: mv a0, a1 461; RV32-NEXT: bltz a3, .LBB16_2 462; RV32-NEXT: # %bb.1: 463; RV32-NEXT: mv a0, a2 464; RV32-NEXT: .LBB16_2: 465; RV32-NEXT: ret 466; 467; RV64-LABEL: bit_10_nz_select_i32: 468; RV64: # %bb.0: 469; RV64-NEXT: slli a3, a0, 53 470; RV64-NEXT: mv a0, a1 471; RV64-NEXT: bltz a3, .LBB16_2 472; RV64-NEXT: # %bb.1: 473; RV64-NEXT: mv a0, a2 474; RV64-NEXT: .LBB16_2: 475; RV64-NEXT: ret 476 %1 = and i32 %a, 1024 477 %2 = icmp ne i32 %1, 0 478 %3 = select i1 %2, i32 %b, i32 %c 479 ret i32 %3 480} 481 482define signext i32 @bit_11_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 483; RV32-LABEL: bit_11_z_select_i32: 484; RV32: # %bb.0: 485; RV32-NEXT: slli a3, a0, 20 486; RV32-NEXT: mv a0, a1 487; RV32-NEXT: bgez a3, .LBB17_2 488; RV32-NEXT: # %bb.1: 489; RV32-NEXT: mv a0, a2 490; RV32-NEXT: .LBB17_2: 491; RV32-NEXT: ret 492; 493; RV64-LABEL: bit_11_z_select_i32: 494; RV64: # %bb.0: 495; RV64-NEXT: slli a3, a0, 52 496; RV64-NEXT: mv a0, a1 497; RV64-NEXT: bgez a3, .LBB17_2 498; RV64-NEXT: # %bb.1: 499; RV64-NEXT: mv a0, a2 500; RV64-NEXT: .LBB17_2: 501; RV64-NEXT: ret 502 %1 = and i32 %a, 2048 503 %2 = icmp eq i32 %1, 0 504 %3 = select i1 %2, i32 %b, i32 %c 505 ret i32 %3 506} 507 508define signext i32 @bit_11_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 509; RV32-LABEL: bit_11_nz_select_i32: 510; RV32: # %bb.0: 511; RV32-NEXT: slli a3, a0, 20 512; RV32-NEXT: mv a0, a1 513; RV32-NEXT: bltz a3, .LBB18_2 514; RV32-NEXT: # %bb.1: 515; RV32-NEXT: mv a0, a2 516; RV32-NEXT: .LBB18_2: 517; RV32-NEXT: ret 518; 519; RV64-LABEL: bit_11_nz_select_i32: 520; RV64: # %bb.0: 521; RV64-NEXT: slli a3, a0, 52 522; RV64-NEXT: mv a0, a1 523; RV64-NEXT: bltz a3, .LBB18_2 524; RV64-NEXT: # %bb.1: 525; RV64-NEXT: mv a0, a2 526; RV64-NEXT: .LBB18_2: 527; RV64-NEXT: ret 528 %1 = and i32 %a, 2048 529 %2 = icmp ne i32 %1, 0 530 %3 = select i1 %2, i32 %b, i32 %c 531 ret i32 %3 532} 533 534define signext i32 @bit_20_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 535; RV32-LABEL: bit_20_z_select_i32: 536; RV32: # %bb.0: 537; RV32-NEXT: slli a3, a0, 11 538; RV32-NEXT: mv a0, a1 539; RV32-NEXT: bgez a3, .LBB19_2 540; RV32-NEXT: # %bb.1: 541; RV32-NEXT: mv a0, a2 542; RV32-NEXT: .LBB19_2: 543; RV32-NEXT: ret 544; 545; RV64-LABEL: bit_20_z_select_i32: 546; RV64: # %bb.0: 547; RV64-NEXT: slli a3, a0, 43 548; RV64-NEXT: mv a0, a1 549; RV64-NEXT: bgez a3, .LBB19_2 550; RV64-NEXT: # %bb.1: 551; RV64-NEXT: mv a0, a2 552; RV64-NEXT: .LBB19_2: 553; RV64-NEXT: ret 554 %1 = and i32 %a, 1048576 555 %2 = icmp eq i32 %1, 0 556 %3 = select i1 %2, i32 %b, i32 %c 557 ret i32 %3 558} 559 560define signext i32 @bit_20_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 561; RV32-LABEL: bit_20_nz_select_i32: 562; RV32: # %bb.0: 563; RV32-NEXT: slli a3, a0, 11 564; RV32-NEXT: mv a0, a1 565; RV32-NEXT: bltz a3, .LBB20_2 566; RV32-NEXT: # %bb.1: 567; RV32-NEXT: mv a0, a2 568; RV32-NEXT: .LBB20_2: 569; RV32-NEXT: ret 570; 571; RV64-LABEL: bit_20_nz_select_i32: 572; RV64: # %bb.0: 573; RV64-NEXT: slli a3, a0, 43 574; RV64-NEXT: mv a0, a1 575; RV64-NEXT: bltz a3, .LBB20_2 576; RV64-NEXT: # %bb.1: 577; RV64-NEXT: mv a0, a2 578; RV64-NEXT: .LBB20_2: 579; RV64-NEXT: ret 580 %1 = and i32 %a, 1048576 581 %2 = icmp ne i32 %1, 0 582 %3 = select i1 %2, i32 %b, i32 %c 583 ret i32 %3 584} 585 586define signext i32 @bit_31_z_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 587; RV32-LABEL: bit_31_z_select_i32: 588; RV32: # %bb.0: 589; RV32-NEXT: bgez a0, .LBB21_2 590; RV32-NEXT: # %bb.1: 591; RV32-NEXT: mv a1, a2 592; RV32-NEXT: .LBB21_2: 593; RV32-NEXT: mv a0, a1 594; RV32-NEXT: ret 595; 596; RV64-LABEL: bit_31_z_select_i32: 597; RV64: # %bb.0: 598; RV64-NEXT: lui a3, 524288 599; RV64-NEXT: and a3, a0, a3 600; RV64-NEXT: mv a0, a1 601; RV64-NEXT: beqz a3, .LBB21_2 602; RV64-NEXT: # %bb.1: 603; RV64-NEXT: mv a0, a2 604; RV64-NEXT: .LBB21_2: 605; RV64-NEXT: ret 606 %1 = and i32 %a, 2147483648 607 %2 = icmp eq i32 %1, 0 608 %3 = select i1 %2, i32 %b, i32 %c 609 ret i32 %3 610} 611 612define signext i32 @bit_31_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) { 613; RV32-LABEL: bit_31_nz_select_i32: 614; RV32: # %bb.0: 615; RV32-NEXT: srli a3, a0, 31 616; RV32-NEXT: mv a0, a1 617; RV32-NEXT: bnez a3, .LBB22_2 618; RV32-NEXT: # %bb.1: 619; RV32-NEXT: mv a0, a2 620; RV32-NEXT: .LBB22_2: 621; RV32-NEXT: ret 622; 623; RV64-LABEL: bit_31_nz_select_i32: 624; RV64: # %bb.0: 625; RV64-NEXT: lui a3, 524288 626; RV64-NEXT: and a3, a0, a3 627; RV64-NEXT: mv a0, a1 628; RV64-NEXT: bnez a3, .LBB22_2 629; RV64-NEXT: # %bb.1: 630; RV64-NEXT: mv a0, a2 631; RV64-NEXT: .LBB22_2: 632; RV64-NEXT: ret 633 %1 = and i32 %a, 2147483648 634 %2 = icmp ne i32 %1, 0 635 %3 = select i1 %2, i32 %b, i32 %c 636 ret i32 %3 637} 638 639define i64 @bit_10_z_select_i64(i64 %a, i64 %b, i64 %c) { 640; RV32-LABEL: bit_10_z_select_i64: 641; RV32: # %bb.0: 642; RV32-NEXT: andi a6, a0, 1024 643; RV32-NEXT: mv a1, a3 644; RV32-NEXT: mv a0, a2 645; RV32-NEXT: beqz a6, .LBB23_2 646; RV32-NEXT: # %bb.1: 647; RV32-NEXT: mv a0, a4 648; RV32-NEXT: mv a1, a5 649; RV32-NEXT: .LBB23_2: 650; RV32-NEXT: ret 651; 652; RV64-LABEL: bit_10_z_select_i64: 653; RV64: # %bb.0: 654; RV64-NEXT: andi a3, a0, 1024 655; RV64-NEXT: mv a0, a1 656; RV64-NEXT: beqz a3, .LBB23_2 657; RV64-NEXT: # %bb.1: 658; RV64-NEXT: mv a0, a2 659; RV64-NEXT: .LBB23_2: 660; RV64-NEXT: ret 661 %1 = and i64 %a, 1024 662 %2 = icmp eq i64 %1, 0 663 %3 = select i1 %2, i64 %b, i64 %c 664 ret i64 %3 665} 666 667define i64 @bit_10_nz_select_i64(i64 %a, i64 %b, i64 %c) { 668; RV32I-LABEL: bit_10_nz_select_i64: 669; RV32I: # %bb.0: 670; RV32I-NEXT: slli a0, a0, 21 671; RV32I-NEXT: srli a6, a0, 31 672; RV32I-NEXT: mv a1, a3 673; RV32I-NEXT: mv a0, a2 674; RV32I-NEXT: bnez a6, .LBB24_2 675; RV32I-NEXT: # %bb.1: 676; RV32I-NEXT: mv a0, a4 677; RV32I-NEXT: mv a1, a5 678; RV32I-NEXT: .LBB24_2: 679; RV32I-NEXT: ret 680; 681; RV64-LABEL: bit_10_nz_select_i64: 682; RV64: # %bb.0: 683; RV64-NEXT: slli a3, a0, 53 684; RV64-NEXT: mv a0, a1 685; RV64-NEXT: bltz a3, .LBB24_2 686; RV64-NEXT: # %bb.1: 687; RV64-NEXT: mv a0, a2 688; RV64-NEXT: .LBB24_2: 689; RV64-NEXT: ret 690; 691; RV32ZBS-LABEL: bit_10_nz_select_i64: 692; RV32ZBS: # %bb.0: 693; RV32ZBS-NEXT: bexti a6, a0, 10 694; RV32ZBS-NEXT: mv a1, a3 695; RV32ZBS-NEXT: mv a0, a2 696; RV32ZBS-NEXT: bnez a6, .LBB24_2 697; RV32ZBS-NEXT: # %bb.1: 698; RV32ZBS-NEXT: mv a0, a4 699; RV32ZBS-NEXT: mv a1, a5 700; RV32ZBS-NEXT: .LBB24_2: 701; RV32ZBS-NEXT: ret 702 %1 = and i64 %a, 1024 703 %2 = icmp ne i64 %1, 0 704 %3 = select i1 %2, i64 %b, i64 %c 705 ret i64 %3 706} 707 708define i64 @bit_11_z_select_i64(i64 %a, i64 %b, i64 %c) { 709; RV32-LABEL: bit_11_z_select_i64: 710; RV32: # %bb.0: 711; RV32-NEXT: slli a6, a0, 20 712; RV32-NEXT: mv a1, a3 713; RV32-NEXT: mv a0, a2 714; RV32-NEXT: bgez a6, .LBB25_2 715; RV32-NEXT: # %bb.1: 716; RV32-NEXT: mv a0, a4 717; RV32-NEXT: mv a1, a5 718; RV32-NEXT: .LBB25_2: 719; RV32-NEXT: ret 720; 721; RV64-LABEL: bit_11_z_select_i64: 722; RV64: # %bb.0: 723; RV64-NEXT: slli a3, a0, 52 724; RV64-NEXT: mv a0, a1 725; RV64-NEXT: bgez a3, .LBB25_2 726; RV64-NEXT: # %bb.1: 727; RV64-NEXT: mv a0, a2 728; RV64-NEXT: .LBB25_2: 729; RV64-NEXT: ret 730 %1 = and i64 %a, 2048 731 %2 = icmp eq i64 %1, 0 732 %3 = select i1 %2, i64 %b, i64 %c 733 ret i64 %3 734} 735 736define i64 @bit_11_nz_select_i64(i64 %a, i64 %b, i64 %c) { 737; RV32I-LABEL: bit_11_nz_select_i64: 738; RV32I: # %bb.0: 739; RV32I-NEXT: slli a0, a0, 20 740; RV32I-NEXT: srli a6, a0, 31 741; RV32I-NEXT: mv a1, a3 742; RV32I-NEXT: mv a0, a2 743; RV32I-NEXT: bnez a6, .LBB26_2 744; RV32I-NEXT: # %bb.1: 745; RV32I-NEXT: mv a0, a4 746; RV32I-NEXT: mv a1, a5 747; RV32I-NEXT: .LBB26_2: 748; RV32I-NEXT: ret 749; 750; RV64-LABEL: bit_11_nz_select_i64: 751; RV64: # %bb.0: 752; RV64-NEXT: slli a3, a0, 52 753; RV64-NEXT: mv a0, a1 754; RV64-NEXT: bltz a3, .LBB26_2 755; RV64-NEXT: # %bb.1: 756; RV64-NEXT: mv a0, a2 757; RV64-NEXT: .LBB26_2: 758; RV64-NEXT: ret 759; 760; RV32ZBS-LABEL: bit_11_nz_select_i64: 761; RV32ZBS: # %bb.0: 762; RV32ZBS-NEXT: bexti a6, a0, 11 763; RV32ZBS-NEXT: mv a1, a3 764; RV32ZBS-NEXT: mv a0, a2 765; RV32ZBS-NEXT: bnez a6, .LBB26_2 766; RV32ZBS-NEXT: # %bb.1: 767; RV32ZBS-NEXT: mv a0, a4 768; RV32ZBS-NEXT: mv a1, a5 769; RV32ZBS-NEXT: .LBB26_2: 770; RV32ZBS-NEXT: ret 771 %1 = and i64 %a, 2048 772 %2 = icmp ne i64 %1, 0 773 %3 = select i1 %2, i64 %b, i64 %c 774 ret i64 %3 775} 776 777define i64 @bit_20_z_select_i64(i64 %a, i64 %b, i64 %c) { 778; RV32-LABEL: bit_20_z_select_i64: 779; RV32: # %bb.0: 780; RV32-NEXT: slli a6, a0, 11 781; RV32-NEXT: mv a1, a3 782; RV32-NEXT: mv a0, a2 783; RV32-NEXT: bgez a6, .LBB27_2 784; RV32-NEXT: # %bb.1: 785; RV32-NEXT: mv a0, a4 786; RV32-NEXT: mv a1, a5 787; RV32-NEXT: .LBB27_2: 788; RV32-NEXT: ret 789; 790; RV64-LABEL: bit_20_z_select_i64: 791; RV64: # %bb.0: 792; RV64-NEXT: slli a3, a0, 43 793; RV64-NEXT: mv a0, a1 794; RV64-NEXT: bgez a3, .LBB27_2 795; RV64-NEXT: # %bb.1: 796; RV64-NEXT: mv a0, a2 797; RV64-NEXT: .LBB27_2: 798; RV64-NEXT: ret 799 %1 = and i64 %a, 1048576 800 %2 = icmp eq i64 %1, 0 801 %3 = select i1 %2, i64 %b, i64 %c 802 ret i64 %3 803} 804 805define i64 @bit_20_nz_select_i64(i64 %a, i64 %b, i64 %c) { 806; RV32I-LABEL: bit_20_nz_select_i64: 807; RV32I: # %bb.0: 808; RV32I-NEXT: slli a0, a0, 11 809; RV32I-NEXT: srli a6, a0, 31 810; RV32I-NEXT: mv a1, a3 811; RV32I-NEXT: mv a0, a2 812; RV32I-NEXT: bnez a6, .LBB28_2 813; RV32I-NEXT: # %bb.1: 814; RV32I-NEXT: mv a0, a4 815; RV32I-NEXT: mv a1, a5 816; RV32I-NEXT: .LBB28_2: 817; RV32I-NEXT: ret 818; 819; RV64-LABEL: bit_20_nz_select_i64: 820; RV64: # %bb.0: 821; RV64-NEXT: slli a3, a0, 43 822; RV64-NEXT: mv a0, a1 823; RV64-NEXT: bltz a3, .LBB28_2 824; RV64-NEXT: # %bb.1: 825; RV64-NEXT: mv a0, a2 826; RV64-NEXT: .LBB28_2: 827; RV64-NEXT: ret 828; 829; RV32ZBS-LABEL: bit_20_nz_select_i64: 830; RV32ZBS: # %bb.0: 831; RV32ZBS-NEXT: bexti a6, a0, 20 832; RV32ZBS-NEXT: mv a1, a3 833; RV32ZBS-NEXT: mv a0, a2 834; RV32ZBS-NEXT: bnez a6, .LBB28_2 835; RV32ZBS-NEXT: # %bb.1: 836; RV32ZBS-NEXT: mv a0, a4 837; RV32ZBS-NEXT: mv a1, a5 838; RV32ZBS-NEXT: .LBB28_2: 839; RV32ZBS-NEXT: ret 840 %1 = and i64 %a, 1048576 841 %2 = icmp ne i64 %1, 0 842 %3 = select i1 %2, i64 %b, i64 %c 843 ret i64 %3 844} 845 846define i64 @bit_31_z_select_i64(i64 %a, i64 %b, i64 %c) { 847; RV32-LABEL: bit_31_z_select_i64: 848; RV32: # %bb.0: 849; RV32-NEXT: mv a1, a3 850; RV32-NEXT: bgez a0, .LBB29_2 851; RV32-NEXT: # %bb.1: 852; RV32-NEXT: mv a2, a4 853; RV32-NEXT: mv a1, a5 854; RV32-NEXT: .LBB29_2: 855; RV32-NEXT: mv a0, a2 856; RV32-NEXT: ret 857; 858; RV64-LABEL: bit_31_z_select_i64: 859; RV64: # %bb.0: 860; RV64-NEXT: slli a3, a0, 32 861; RV64-NEXT: mv a0, a1 862; RV64-NEXT: bgez a3, .LBB29_2 863; RV64-NEXT: # %bb.1: 864; RV64-NEXT: mv a0, a2 865; RV64-NEXT: .LBB29_2: 866; RV64-NEXT: ret 867 %1 = and i64 %a, 2147483648 868 %2 = icmp eq i64 %1, 0 869 %3 = select i1 %2, i64 %b, i64 %c 870 ret i64 %3 871} 872 873define i64 @bit_31_nz_select_i64(i64 %a, i64 %b, i64 %c) { 874; RV32-LABEL: bit_31_nz_select_i64: 875; RV32: # %bb.0: 876; RV32-NEXT: srli a6, a0, 31 877; RV32-NEXT: mv a1, a3 878; RV32-NEXT: mv a0, a2 879; RV32-NEXT: bnez a6, .LBB30_2 880; RV32-NEXT: # %bb.1: 881; RV32-NEXT: mv a0, a4 882; RV32-NEXT: mv a1, a5 883; RV32-NEXT: .LBB30_2: 884; RV32-NEXT: ret 885; 886; RV64-LABEL: bit_31_nz_select_i64: 887; RV64: # %bb.0: 888; RV64-NEXT: slli a3, a0, 32 889; RV64-NEXT: mv a0, a1 890; RV64-NEXT: bltz a3, .LBB30_2 891; RV64-NEXT: # %bb.1: 892; RV64-NEXT: mv a0, a2 893; RV64-NEXT: .LBB30_2: 894; RV64-NEXT: ret 895 %1 = and i64 %a, 2147483648 896 %2 = icmp ne i64 %1, 0 897 %3 = select i1 %2, i64 %b, i64 %c 898 ret i64 %3 899} 900 901define i64 @bit_32_z_select_i64(i64 %a, i64 %b, i64 %c) { 902; RV32-LABEL: bit_32_z_select_i64: 903; RV32: # %bb.0: 904; RV32-NEXT: andi a6, a1, 1 905; RV32-NEXT: mv a1, a3 906; RV32-NEXT: mv a0, a2 907; RV32-NEXT: beqz a6, .LBB31_2 908; RV32-NEXT: # %bb.1: 909; RV32-NEXT: mv a0, a4 910; RV32-NEXT: mv a1, a5 911; RV32-NEXT: .LBB31_2: 912; RV32-NEXT: ret 913; 914; RV64-LABEL: bit_32_z_select_i64: 915; RV64: # %bb.0: 916; RV64-NEXT: slli a3, a0, 31 917; RV64-NEXT: mv a0, a1 918; RV64-NEXT: bgez a3, .LBB31_2 919; RV64-NEXT: # %bb.1: 920; RV64-NEXT: mv a0, a2 921; RV64-NEXT: .LBB31_2: 922; RV64-NEXT: ret 923 %1 = and i64 %a, 4294967296 924 %2 = icmp eq i64 %1, 0 925 %3 = select i1 %2, i64 %b, i64 %c 926 ret i64 %3 927} 928 929define i64 @bit_32_nz_select_i64(i64 %a, i64 %b, i64 %c) { 930; RV32-LABEL: bit_32_nz_select_i64: 931; RV32: # %bb.0: 932; RV32-NEXT: andi a6, a1, 1 933; RV32-NEXT: mv a1, a3 934; RV32-NEXT: mv a0, a2 935; RV32-NEXT: bnez a6, .LBB32_2 936; RV32-NEXT: # %bb.1: 937; RV32-NEXT: mv a0, a4 938; RV32-NEXT: mv a1, a5 939; RV32-NEXT: .LBB32_2: 940; RV32-NEXT: ret 941; 942; RV64-LABEL: bit_32_nz_select_i64: 943; RV64: # %bb.0: 944; RV64-NEXT: slli a3, a0, 31 945; RV64-NEXT: mv a0, a1 946; RV64-NEXT: bltz a3, .LBB32_2 947; RV64-NEXT: # %bb.1: 948; RV64-NEXT: mv a0, a2 949; RV64-NEXT: .LBB32_2: 950; RV64-NEXT: ret 951 %1 = and i64 %a, 4294967296 952 %2 = icmp ne i64 %1, 0 953 %3 = select i1 %2, i64 %b, i64 %c 954 ret i64 %3 955} 956 957define i64 @bit_55_z_select_i64(i64 %a, i64 %b, i64 %c) { 958; RV32-LABEL: bit_55_z_select_i64: 959; RV32: # %bb.0: 960; RV32-NEXT: slli a6, a1, 8 961; RV32-NEXT: mv a1, a3 962; RV32-NEXT: mv a0, a2 963; RV32-NEXT: bgez a6, .LBB33_2 964; RV32-NEXT: # %bb.1: 965; RV32-NEXT: mv a0, a4 966; RV32-NEXT: mv a1, a5 967; RV32-NEXT: .LBB33_2: 968; RV32-NEXT: ret 969; 970; RV64-LABEL: bit_55_z_select_i64: 971; RV64: # %bb.0: 972; RV64-NEXT: slli a3, a0, 8 973; RV64-NEXT: mv a0, a1 974; RV64-NEXT: bgez a3, .LBB33_2 975; RV64-NEXT: # %bb.1: 976; RV64-NEXT: mv a0, a2 977; RV64-NEXT: .LBB33_2: 978; RV64-NEXT: ret 979 %1 = and i64 %a, 36028797018963968 980 %2 = icmp eq i64 %1, 0 981 %3 = select i1 %2, i64 %b, i64 %c 982 ret i64 %3 983} 984 985define i64 @bit_55_nz_select_i64(i64 %a, i64 %b, i64 %c) { 986; RV32I-LABEL: bit_55_nz_select_i64: 987; RV32I: # %bb.0: 988; RV32I-NEXT: slli a0, a1, 8 989; RV32I-NEXT: srli a6, a0, 31 990; RV32I-NEXT: mv a1, a3 991; RV32I-NEXT: mv a0, a2 992; RV32I-NEXT: bnez a6, .LBB34_2 993; RV32I-NEXT: # %bb.1: 994; RV32I-NEXT: mv a0, a4 995; RV32I-NEXT: mv a1, a5 996; RV32I-NEXT: .LBB34_2: 997; RV32I-NEXT: ret 998; 999; RV64-LABEL: bit_55_nz_select_i64: 1000; RV64: # %bb.0: 1001; RV64-NEXT: slli a3, a0, 8 1002; RV64-NEXT: mv a0, a1 1003; RV64-NEXT: bltz a3, .LBB34_2 1004; RV64-NEXT: # %bb.1: 1005; RV64-NEXT: mv a0, a2 1006; RV64-NEXT: .LBB34_2: 1007; RV64-NEXT: ret 1008; 1009; RV32ZBS-LABEL: bit_55_nz_select_i64: 1010; RV32ZBS: # %bb.0: 1011; RV32ZBS-NEXT: bexti a6, a1, 23 1012; RV32ZBS-NEXT: mv a1, a3 1013; RV32ZBS-NEXT: mv a0, a2 1014; RV32ZBS-NEXT: bnez a6, .LBB34_2 1015; RV32ZBS-NEXT: # %bb.1: 1016; RV32ZBS-NEXT: mv a0, a4 1017; RV32ZBS-NEXT: mv a1, a5 1018; RV32ZBS-NEXT: .LBB34_2: 1019; RV32ZBS-NEXT: ret 1020 %1 = and i64 %a, 36028797018963968 1021 %2 = icmp ne i64 %1, 0 1022 %3 = select i1 %2, i64 %b, i64 %c 1023 ret i64 %3 1024} 1025 1026define i64 @bit_63_z_select_i64(i64 %a, i64 %b, i64 %c) { 1027; RV32-LABEL: bit_63_z_select_i64: 1028; RV32: # %bb.0: 1029; RV32-NEXT: mv a0, a2 1030; RV32-NEXT: bgez a1, .LBB35_2 1031; RV32-NEXT: # %bb.1: 1032; RV32-NEXT: mv a0, a4 1033; RV32-NEXT: mv a3, a5 1034; RV32-NEXT: .LBB35_2: 1035; RV32-NEXT: mv a1, a3 1036; RV32-NEXT: ret 1037; 1038; RV64-LABEL: bit_63_z_select_i64: 1039; RV64: # %bb.0: 1040; RV64-NEXT: bgez a0, .LBB35_2 1041; RV64-NEXT: # %bb.1: 1042; RV64-NEXT: mv a1, a2 1043; RV64-NEXT: .LBB35_2: 1044; RV64-NEXT: mv a0, a1 1045; RV64-NEXT: ret 1046 %1 = and i64 %a, 9223372036854775808 1047 %2 = icmp eq i64 %1, 0 1048 %3 = select i1 %2, i64 %b, i64 %c 1049 ret i64 %3 1050} 1051 1052define i64 @bit_63_nz_select_i64(i64 %a, i64 %b, i64 %c) { 1053; RV32-LABEL: bit_63_nz_select_i64: 1054; RV32: # %bb.0: 1055; RV32-NEXT: srli a6, a1, 31 1056; RV32-NEXT: mv a1, a3 1057; RV32-NEXT: mv a0, a2 1058; RV32-NEXT: bnez a6, .LBB36_2 1059; RV32-NEXT: # %bb.1: 1060; RV32-NEXT: mv a0, a4 1061; RV32-NEXT: mv a1, a5 1062; RV32-NEXT: .LBB36_2: 1063; RV32-NEXT: ret 1064; 1065; RV64-LABEL: bit_63_nz_select_i64: 1066; RV64: # %bb.0: 1067; RV64-NEXT: srli a3, a0, 63 1068; RV64-NEXT: mv a0, a1 1069; RV64-NEXT: bnez a3, .LBB36_2 1070; RV64-NEXT: # %bb.1: 1071; RV64-NEXT: mv a0, a2 1072; RV64-NEXT: .LBB36_2: 1073; RV64-NEXT: ret 1074 %1 = and i64 %a, 9223372036854775808 1075 %2 = icmp ne i64 %1, 0 1076 %3 = select i1 %2, i64 %b, i64 %c 1077 ret i64 %3 1078} 1079 1080define void @bit_10_z_branch_i32(i32 signext %0) { 1081; CHECK-LABEL: bit_10_z_branch_i32: 1082; CHECK: # %bb.0: 1083; CHECK-NEXT: andi a0, a0, 1024 1084; CHECK-NEXT: bnez a0, .LBB37_2 1085; CHECK-NEXT: # %bb.1: 1086; CHECK-NEXT: tail bar@plt 1087; CHECK-NEXT: .LBB37_2: 1088; CHECK-NEXT: ret 1089 %2 = and i32 %0, 1024 1090 %3 = icmp eq i32 %2, 0 1091 br i1 %3, label %4, label %5 1092 10934: 1094 tail call void @bar() 1095 br label %5 1096 10975: 1098 ret void 1099} 1100 1101define void @bit_10_nz_branch_i32(i32 signext %0) { 1102; CHECK-LABEL: bit_10_nz_branch_i32: 1103; CHECK: # %bb.0: 1104; CHECK-NEXT: andi a0, a0, 1024 1105; CHECK-NEXT: beqz a0, .LBB38_2 1106; CHECK-NEXT: # %bb.1: 1107; CHECK-NEXT: tail bar@plt 1108; CHECK-NEXT: .LBB38_2: 1109; CHECK-NEXT: ret 1110 %2 = and i32 %0, 1024 1111 %3 = icmp ne i32 %2, 0 1112 br i1 %3, label %4, label %5 1113 11144: 1115 tail call void @bar() 1116 br label %5 1117 11185: 1119 ret void 1120} 1121 1122define void @bit_11_z_branch_i32(i32 signext %0) { 1123; RV32-LABEL: bit_11_z_branch_i32: 1124; RV32: # %bb.0: 1125; RV32-NEXT: slli a0, a0, 20 1126; RV32-NEXT: bltz a0, .LBB39_2 1127; RV32-NEXT: # %bb.1: 1128; RV32-NEXT: tail bar@plt 1129; RV32-NEXT: .LBB39_2: 1130; RV32-NEXT: ret 1131; 1132; RV64-LABEL: bit_11_z_branch_i32: 1133; RV64: # %bb.0: 1134; RV64-NEXT: slli a0, a0, 52 1135; RV64-NEXT: bltz a0, .LBB39_2 1136; RV64-NEXT: # %bb.1: 1137; RV64-NEXT: tail bar@plt 1138; RV64-NEXT: .LBB39_2: 1139; RV64-NEXT: ret 1140 %2 = and i32 %0, 2048 1141 %3 = icmp eq i32 %2, 0 1142 br i1 %3, label %4, label %5 1143 11444: 1145 tail call void @bar() 1146 br label %5 1147 11485: 1149 ret void 1150} 1151 1152define void @bit_11_nz_branch_i32(i32 signext %0) { 1153; RV32-LABEL: bit_11_nz_branch_i32: 1154; RV32: # %bb.0: 1155; RV32-NEXT: slli a0, a0, 20 1156; RV32-NEXT: bgez a0, .LBB40_2 1157; RV32-NEXT: # %bb.1: 1158; RV32-NEXT: tail bar@plt 1159; RV32-NEXT: .LBB40_2: 1160; RV32-NEXT: ret 1161; 1162; RV64-LABEL: bit_11_nz_branch_i32: 1163; RV64: # %bb.0: 1164; RV64-NEXT: slli a0, a0, 52 1165; RV64-NEXT: bgez a0, .LBB40_2 1166; RV64-NEXT: # %bb.1: 1167; RV64-NEXT: tail bar@plt 1168; RV64-NEXT: .LBB40_2: 1169; RV64-NEXT: ret 1170 %2 = and i32 %0, 2048 1171 %3 = icmp ne i32 %2, 0 1172 br i1 %3, label %4, label %5 1173 11744: 1175 tail call void @bar() 1176 br label %5 1177 11785: 1179 ret void 1180} 1181 1182define void @bit_24_z_branch_i32(i32 signext %0) { 1183; RV32-LABEL: bit_24_z_branch_i32: 1184; RV32: # %bb.0: 1185; RV32-NEXT: slli a0, a0, 7 1186; RV32-NEXT: bltz a0, .LBB41_2 1187; RV32-NEXT: # %bb.1: 1188; RV32-NEXT: tail bar@plt 1189; RV32-NEXT: .LBB41_2: 1190; RV32-NEXT: ret 1191; 1192; RV64-LABEL: bit_24_z_branch_i32: 1193; RV64: # %bb.0: 1194; RV64-NEXT: slli a0, a0, 39 1195; RV64-NEXT: bltz a0, .LBB41_2 1196; RV64-NEXT: # %bb.1: 1197; RV64-NEXT: tail bar@plt 1198; RV64-NEXT: .LBB41_2: 1199; RV64-NEXT: ret 1200 %2 = and i32 %0, 16777216 1201 %3 = icmp eq i32 %2, 0 1202 br i1 %3, label %4, label %5 1203 12044: 1205 tail call void @bar() 1206 br label %5 1207 12085: 1209 ret void 1210} 1211 1212define void @bit_24_nz_branch_i32(i32 signext %0) { 1213; RV32-LABEL: bit_24_nz_branch_i32: 1214; RV32: # %bb.0: 1215; RV32-NEXT: slli a0, a0, 7 1216; RV32-NEXT: bgez a0, .LBB42_2 1217; RV32-NEXT: # %bb.1: 1218; RV32-NEXT: tail bar@plt 1219; RV32-NEXT: .LBB42_2: 1220; RV32-NEXT: ret 1221; 1222; RV64-LABEL: bit_24_nz_branch_i32: 1223; RV64: # %bb.0: 1224; RV64-NEXT: slli a0, a0, 39 1225; RV64-NEXT: bgez a0, .LBB42_2 1226; RV64-NEXT: # %bb.1: 1227; RV64-NEXT: tail bar@plt 1228; RV64-NEXT: .LBB42_2: 1229; RV64-NEXT: ret 1230 %2 = and i32 %0, 16777216 1231 %3 = icmp ne i32 %2, 0 1232 br i1 %3, label %4, label %5 1233 12344: 1235 tail call void @bar() 1236 br label %5 1237 12385: 1239 ret void 1240} 1241 1242define void @bit_31_z_branch_i32(i32 signext %0) { 1243; RV32-LABEL: bit_31_z_branch_i32: 1244; RV32: # %bb.0: 1245; RV32-NEXT: bltz a0, .LBB43_2 1246; RV32-NEXT: # %bb.1: 1247; RV32-NEXT: tail bar@plt 1248; RV32-NEXT: .LBB43_2: 1249; RV32-NEXT: ret 1250; 1251; RV64-LABEL: bit_31_z_branch_i32: 1252; RV64: # %bb.0: 1253; RV64-NEXT: lui a1, 524288 1254; RV64-NEXT: and a0, a0, a1 1255; RV64-NEXT: bnez a0, .LBB43_2 1256; RV64-NEXT: # %bb.1: 1257; RV64-NEXT: tail bar@plt 1258; RV64-NEXT: .LBB43_2: 1259; RV64-NEXT: ret 1260 %2 = and i32 %0, 2147483648 1261 %3 = icmp eq i32 %2, 0 1262 br i1 %3, label %4, label %5 1263 12644: 1265 tail call void @bar() 1266 br label %5 1267 12685: 1269 ret void 1270} 1271 1272define void @bit_31_nz_branch_i32(i32 signext %0) { 1273; RV32-LABEL: bit_31_nz_branch_i32: 1274; RV32: # %bb.0: 1275; RV32-NEXT: bgez a0, .LBB44_2 1276; RV32-NEXT: # %bb.1: 1277; RV32-NEXT: tail bar@plt 1278; RV32-NEXT: .LBB44_2: 1279; RV32-NEXT: ret 1280; 1281; RV64-LABEL: bit_31_nz_branch_i32: 1282; RV64: # %bb.0: 1283; RV64-NEXT: lui a1, 524288 1284; RV64-NEXT: and a0, a0, a1 1285; RV64-NEXT: beqz a0, .LBB44_2 1286; RV64-NEXT: # %bb.1: 1287; RV64-NEXT: tail bar@plt 1288; RV64-NEXT: .LBB44_2: 1289; RV64-NEXT: ret 1290 %2 = and i32 %0, 2147483648 1291 %3 = icmp ne i32 %2, 0 1292 br i1 %3, label %4, label %5 1293 12944: 1295 tail call void @bar() 1296 br label %5 1297 12985: 1299 ret void 1300} 1301 1302define void @bit_10_z_branch_i64(i64 %0) { 1303; CHECK-LABEL: bit_10_z_branch_i64: 1304; CHECK: # %bb.0: 1305; CHECK-NEXT: andi a0, a0, 1024 1306; CHECK-NEXT: bnez a0, .LBB45_2 1307; CHECK-NEXT: # %bb.1: 1308; CHECK-NEXT: tail bar@plt 1309; CHECK-NEXT: .LBB45_2: 1310; CHECK-NEXT: ret 1311 %2 = and i64 %0, 1024 1312 %3 = icmp eq i64 %2, 0 1313 br i1 %3, label %4, label %5 1314 13154: 1316 tail call void @bar() 1317 br label %5 1318 13195: 1320 ret void 1321} 1322 1323define void @bit_10_nz_branch_i64(i64 %0) { 1324; CHECK-LABEL: bit_10_nz_branch_i64: 1325; CHECK: # %bb.0: 1326; CHECK-NEXT: andi a0, a0, 1024 1327; CHECK-NEXT: beqz a0, .LBB46_2 1328; CHECK-NEXT: # %bb.1: 1329; CHECK-NEXT: tail bar@plt 1330; CHECK-NEXT: .LBB46_2: 1331; CHECK-NEXT: ret 1332 %2 = and i64 %0, 1024 1333 %3 = icmp ne i64 %2, 0 1334 br i1 %3, label %4, label %5 1335 13364: 1337 tail call void @bar() 1338 br label %5 1339 13405: 1341 ret void 1342} 1343 1344define void @bit_11_z_branch_i64(i64 %0) { 1345; RV32-LABEL: bit_11_z_branch_i64: 1346; RV32: # %bb.0: 1347; RV32-NEXT: slli a0, a0, 20 1348; RV32-NEXT: bltz a0, .LBB47_2 1349; RV32-NEXT: # %bb.1: 1350; RV32-NEXT: tail bar@plt 1351; RV32-NEXT: .LBB47_2: 1352; RV32-NEXT: ret 1353; 1354; RV64-LABEL: bit_11_z_branch_i64: 1355; RV64: # %bb.0: 1356; RV64-NEXT: slli a0, a0, 52 1357; RV64-NEXT: bltz a0, .LBB47_2 1358; RV64-NEXT: # %bb.1: 1359; RV64-NEXT: tail bar@plt 1360; RV64-NEXT: .LBB47_2: 1361; RV64-NEXT: ret 1362 %2 = and i64 %0, 2048 1363 %3 = icmp eq i64 %2, 0 1364 br i1 %3, label %4, label %5 1365 13664: 1367 tail call void @bar() 1368 br label %5 1369 13705: 1371 ret void 1372} 1373 1374define void @bit_11_nz_branch_i64(i64 %0) { 1375; RV32-LABEL: bit_11_nz_branch_i64: 1376; RV32: # %bb.0: 1377; RV32-NEXT: slli a0, a0, 20 1378; RV32-NEXT: bgez a0, .LBB48_2 1379; RV32-NEXT: # %bb.1: 1380; RV32-NEXT: tail bar@plt 1381; RV32-NEXT: .LBB48_2: 1382; RV32-NEXT: ret 1383; 1384; RV64-LABEL: bit_11_nz_branch_i64: 1385; RV64: # %bb.0: 1386; RV64-NEXT: slli a0, a0, 52 1387; RV64-NEXT: bgez a0, .LBB48_2 1388; RV64-NEXT: # %bb.1: 1389; RV64-NEXT: tail bar@plt 1390; RV64-NEXT: .LBB48_2: 1391; RV64-NEXT: ret 1392 %2 = and i64 %0, 2048 1393 %3 = icmp ne i64 %2, 0 1394 br i1 %3, label %4, label %5 1395 13964: 1397 tail call void @bar() 1398 br label %5 1399 14005: 1401 ret void 1402} 1403 1404define void @bit_24_z_branch_i64(i64 %0) { 1405; RV32-LABEL: bit_24_z_branch_i64: 1406; RV32: # %bb.0: 1407; RV32-NEXT: slli a0, a0, 7 1408; RV32-NEXT: bltz a0, .LBB49_2 1409; RV32-NEXT: # %bb.1: 1410; RV32-NEXT: tail bar@plt 1411; RV32-NEXT: .LBB49_2: 1412; RV32-NEXT: ret 1413; 1414; RV64-LABEL: bit_24_z_branch_i64: 1415; RV64: # %bb.0: 1416; RV64-NEXT: slli a0, a0, 39 1417; RV64-NEXT: bltz a0, .LBB49_2 1418; RV64-NEXT: # %bb.1: 1419; RV64-NEXT: tail bar@plt 1420; RV64-NEXT: .LBB49_2: 1421; RV64-NEXT: ret 1422 %2 = and i64 %0, 16777216 1423 %3 = icmp eq i64 %2, 0 1424 br i1 %3, label %4, label %5 1425 14264: 1427 tail call void @bar() 1428 br label %5 1429 14305: 1431 ret void 1432} 1433 1434define void @bit_24_nz_branch_i64(i64 %0) { 1435; RV32-LABEL: bit_24_nz_branch_i64: 1436; RV32: # %bb.0: 1437; RV32-NEXT: slli a0, a0, 7 1438; RV32-NEXT: bgez a0, .LBB50_2 1439; RV32-NEXT: # %bb.1: 1440; RV32-NEXT: tail bar@plt 1441; RV32-NEXT: .LBB50_2: 1442; RV32-NEXT: ret 1443; 1444; RV64-LABEL: bit_24_nz_branch_i64: 1445; RV64: # %bb.0: 1446; RV64-NEXT: slli a0, a0, 39 1447; RV64-NEXT: bgez a0, .LBB50_2 1448; RV64-NEXT: # %bb.1: 1449; RV64-NEXT: tail bar@plt 1450; RV64-NEXT: .LBB50_2: 1451; RV64-NEXT: ret 1452 %2 = and i64 %0, 16777216 1453 %3 = icmp ne i64 %2, 0 1454 br i1 %3, label %4, label %5 1455 14564: 1457 tail call void @bar() 1458 br label %5 1459 14605: 1461 ret void 1462} 1463 1464define void @bit_31_z_branch_i64(i64 %0) { 1465; RV32-LABEL: bit_31_z_branch_i64: 1466; RV32: # %bb.0: 1467; RV32-NEXT: bltz a0, .LBB51_2 1468; RV32-NEXT: # %bb.1: 1469; RV32-NEXT: tail bar@plt 1470; RV32-NEXT: .LBB51_2: 1471; RV32-NEXT: ret 1472; 1473; RV64-LABEL: bit_31_z_branch_i64: 1474; RV64: # %bb.0: 1475; RV64-NEXT: slli a0, a0, 32 1476; RV64-NEXT: bltz a0, .LBB51_2 1477; RV64-NEXT: # %bb.1: 1478; RV64-NEXT: tail bar@plt 1479; RV64-NEXT: .LBB51_2: 1480; RV64-NEXT: ret 1481 %2 = and i64 %0, 2147483648 1482 %3 = icmp eq i64 %2, 0 1483 br i1 %3, label %4, label %5 1484 14854: 1486 tail call void @bar() 1487 br label %5 1488 14895: 1490 ret void 1491} 1492 1493define void @bit_31_nz_branch_i64(i64 %0) { 1494; RV32-LABEL: bit_31_nz_branch_i64: 1495; RV32: # %bb.0: 1496; RV32-NEXT: bgez a0, .LBB52_2 1497; RV32-NEXT: # %bb.1: 1498; RV32-NEXT: tail bar@plt 1499; RV32-NEXT: .LBB52_2: 1500; RV32-NEXT: ret 1501; 1502; RV64-LABEL: bit_31_nz_branch_i64: 1503; RV64: # %bb.0: 1504; RV64-NEXT: slli a0, a0, 32 1505; RV64-NEXT: bgez a0, .LBB52_2 1506; RV64-NEXT: # %bb.1: 1507; RV64-NEXT: tail bar@plt 1508; RV64-NEXT: .LBB52_2: 1509; RV64-NEXT: ret 1510 %2 = and i64 %0, 2147483648 1511 %3 = icmp ne i64 %2, 0 1512 br i1 %3, label %4, label %5 1513 15144: 1515 tail call void @bar() 1516 br label %5 1517 15185: 1519 ret void 1520} 1521 1522define void @bit_32_z_branch_i64(i64 %0) { 1523; RV32-LABEL: bit_32_z_branch_i64: 1524; RV32: # %bb.0: 1525; RV32-NEXT: andi a0, a1, 1 1526; RV32-NEXT: bnez a0, .LBB53_2 1527; RV32-NEXT: # %bb.1: 1528; RV32-NEXT: tail bar@plt 1529; RV32-NEXT: .LBB53_2: 1530; RV32-NEXT: ret 1531; 1532; RV64-LABEL: bit_32_z_branch_i64: 1533; RV64: # %bb.0: 1534; RV64-NEXT: slli a0, a0, 31 1535; RV64-NEXT: bltz a0, .LBB53_2 1536; RV64-NEXT: # %bb.1: 1537; RV64-NEXT: tail bar@plt 1538; RV64-NEXT: .LBB53_2: 1539; RV64-NEXT: ret 1540 %2 = and i64 %0, 4294967296 1541 %3 = icmp eq i64 %2, 0 1542 br i1 %3, label %4, label %5 1543 15444: 1545 tail call void @bar() 1546 br label %5 1547 15485: 1549 ret void 1550} 1551 1552define void @bit_32_nz_branch_i64(i64 %0) { 1553; RV32-LABEL: bit_32_nz_branch_i64: 1554; RV32: # %bb.0: 1555; RV32-NEXT: andi a0, a1, 1 1556; RV32-NEXT: beqz a0, .LBB54_2 1557; RV32-NEXT: # %bb.1: 1558; RV32-NEXT: tail bar@plt 1559; RV32-NEXT: .LBB54_2: 1560; RV32-NEXT: ret 1561; 1562; RV64-LABEL: bit_32_nz_branch_i64: 1563; RV64: # %bb.0: 1564; RV64-NEXT: slli a0, a0, 31 1565; RV64-NEXT: bgez a0, .LBB54_2 1566; RV64-NEXT: # %bb.1: 1567; RV64-NEXT: tail bar@plt 1568; RV64-NEXT: .LBB54_2: 1569; RV64-NEXT: ret 1570 %2 = and i64 %0, 4294967296 1571 %3 = icmp ne i64 %2, 0 1572 br i1 %3, label %4, label %5 1573 15744: 1575 tail call void @bar() 1576 br label %5 1577 15785: 1579 ret void 1580} 1581 1582define void @bit_62_z_branch_i64(i64 %0) { 1583; RV32-LABEL: bit_62_z_branch_i64: 1584; RV32: # %bb.0: 1585; RV32-NEXT: slli a0, a1, 1 1586; RV32-NEXT: bltz a0, .LBB55_2 1587; RV32-NEXT: # %bb.1: 1588; RV32-NEXT: tail bar@plt 1589; RV32-NEXT: .LBB55_2: 1590; RV32-NEXT: ret 1591; 1592; RV64-LABEL: bit_62_z_branch_i64: 1593; RV64: # %bb.0: 1594; RV64-NEXT: slli a0, a0, 1 1595; RV64-NEXT: bltz a0, .LBB55_2 1596; RV64-NEXT: # %bb.1: 1597; RV64-NEXT: tail bar@plt 1598; RV64-NEXT: .LBB55_2: 1599; RV64-NEXT: ret 1600 %2 = and i64 %0, 4611686018427387904 1601 %3 = icmp eq i64 %2, 0 1602 br i1 %3, label %4, label %5 1603 16044: 1605 tail call void @bar() 1606 br label %5 1607 16085: 1609 ret void 1610} 1611 1612define void @bit_62_nz_branch_i64(i64 %0) { 1613; RV32-LABEL: bit_62_nz_branch_i64: 1614; RV32: # %bb.0: 1615; RV32-NEXT: slli a0, a1, 1 1616; RV32-NEXT: bgez a0, .LBB56_2 1617; RV32-NEXT: # %bb.1: 1618; RV32-NEXT: tail bar@plt 1619; RV32-NEXT: .LBB56_2: 1620; RV32-NEXT: ret 1621; 1622; RV64-LABEL: bit_62_nz_branch_i64: 1623; RV64: # %bb.0: 1624; RV64-NEXT: slli a0, a0, 1 1625; RV64-NEXT: bgez a0, .LBB56_2 1626; RV64-NEXT: # %bb.1: 1627; RV64-NEXT: tail bar@plt 1628; RV64-NEXT: .LBB56_2: 1629; RV64-NEXT: ret 1630 %2 = and i64 %0, 4611686018427387904 1631 %3 = icmp ne i64 %2, 0 1632 br i1 %3, label %4, label %5 1633 16344: 1635 tail call void @bar() 1636 br label %5 1637 16385: 1639 ret void 1640} 1641 1642define void @bit_63_z_branch_i64(i64 %0) { 1643; RV32-LABEL: bit_63_z_branch_i64: 1644; RV32: # %bb.0: 1645; RV32-NEXT: bltz a1, .LBB57_2 1646; RV32-NEXT: # %bb.1: 1647; RV32-NEXT: tail bar@plt 1648; RV32-NEXT: .LBB57_2: 1649; RV32-NEXT: ret 1650; 1651; RV64-LABEL: bit_63_z_branch_i64: 1652; RV64: # %bb.0: 1653; RV64-NEXT: bltz a0, .LBB57_2 1654; RV64-NEXT: # %bb.1: 1655; RV64-NEXT: tail bar@plt 1656; RV64-NEXT: .LBB57_2: 1657; RV64-NEXT: ret 1658 %2 = and i64 %0, 9223372036854775808 1659 %3 = icmp eq i64 %2, 0 1660 br i1 %3, label %4, label %5 1661 16624: 1663 tail call void @bar() 1664 br label %5 1665 16665: 1667 ret void 1668} 1669 1670define void @bit_63_nz_branch_i64(i64 %0) { 1671; RV32-LABEL: bit_63_nz_branch_i64: 1672; RV32: # %bb.0: 1673; RV32-NEXT: bgez a1, .LBB58_2 1674; RV32-NEXT: # %bb.1: 1675; RV32-NEXT: tail bar@plt 1676; RV32-NEXT: .LBB58_2: 1677; RV32-NEXT: ret 1678; 1679; RV64-LABEL: bit_63_nz_branch_i64: 1680; RV64: # %bb.0: 1681; RV64-NEXT: bgez a0, .LBB58_2 1682; RV64-NEXT: # %bb.1: 1683; RV64-NEXT: tail bar@plt 1684; RV64-NEXT: .LBB58_2: 1685; RV64-NEXT: ret 1686 %2 = and i64 %0, 9223372036854775808 1687 %3 = icmp ne i64 %2, 0 1688 br i1 %3, label %4, label %5 1689 16904: 1691 tail call void @bar() 1692 br label %5 1693 16945: 1695 ret void 1696} 1697