1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE 4 5define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) { 6; CHECK-LE-LABEL: test_add1: 7; CHECK-LE: # %bb.0: # %entry 8; CHECK-LE-NEXT: vextubrx 3, 5, 2 9; CHECK-LE-NEXT: add 3, 3, 6 10; CHECK-LE-NEXT: clrldi 3, 3, 56 11; CHECK-LE-NEXT: blr 12; 13; CHECK-BE-LABEL: test_add1: 14; CHECK-BE: # %bb.0: # %entry 15; CHECK-BE-NEXT: vextublx 3, 5, 2 16; CHECK-BE-NEXT: add 3, 3, 6 17; CHECK-BE-NEXT: clrldi 3, 3, 56 18; CHECK-BE-NEXT: blr 19entry: 20 %vecext = extractelement <16 x i8> %a, i32 %index 21 %conv = zext i8 %vecext to i32 22 %conv1 = zext i8 %c to i32 23 %add = add nuw nsw i32 %conv, %conv1 24 %conv2 = trunc i32 %add to i8 25 ret i8 %conv2 26} 27 28define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) { 29; CHECK-LE-LABEL: test_add2: 30; CHECK-LE: # %bb.0: # %entry 31; CHECK-LE-NEXT: vextubrx 3, 5, 2 32; CHECK-LE-NEXT: add 3, 3, 6 33; CHECK-LE-NEXT: extsb 3, 3 34; CHECK-LE-NEXT: blr 35; 36; CHECK-BE-LABEL: test_add2: 37; CHECK-BE: # %bb.0: # %entry 38; CHECK-BE-NEXT: vextublx 3, 5, 2 39; CHECK-BE-NEXT: add 3, 3, 6 40; CHECK-BE-NEXT: extsb 3, 3 41; CHECK-BE-NEXT: blr 42entry: 43 %vecext = extractelement <16 x i8> %a, i32 %index 44 %conv3 = zext i8 %vecext to i32 45 %conv14 = zext i8 %c to i32 46 %add = add nuw nsw i32 %conv3, %conv14 47 %conv2 = trunc i32 %add to i8 48 ret i8 %conv2 49} 50 51define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) { 52; CHECK-LE-LABEL: test_add3: 53; CHECK-LE: # %bb.0: # %entry 54; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 55; CHECK-LE-NEXT: vextuhrx 3, 3, 2 56; CHECK-LE-NEXT: add 3, 3, 6 57; CHECK-LE-NEXT: clrldi 3, 3, 48 58; CHECK-LE-NEXT: blr 59; 60; CHECK-BE-LABEL: test_add3: 61; CHECK-BE: # %bb.0: # %entry 62; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 63; CHECK-BE-NEXT: vextuhlx 3, 3, 2 64; CHECK-BE-NEXT: add 3, 3, 6 65; CHECK-BE-NEXT: clrldi 3, 3, 48 66; CHECK-BE-NEXT: blr 67entry: 68 %vecext = extractelement <8 x i16> %a, i32 %index 69 %conv = zext i16 %vecext to i32 70 %conv1 = zext i16 %c to i32 71 %add = add nuw nsw i32 %conv, %conv1 72 %conv2 = trunc i32 %add to i16 73 ret i16 %conv2 74} 75 76define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) { 77; CHECK-LE-LABEL: test_add4: 78; CHECK-LE: # %bb.0: # %entry 79; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 80; CHECK-LE-NEXT: vextuhrx 3, 3, 2 81; CHECK-LE-NEXT: add 3, 3, 6 82; CHECK-LE-NEXT: extsh 3, 3 83; CHECK-LE-NEXT: blr 84; 85; CHECK-BE-LABEL: test_add4: 86; CHECK-BE: # %bb.0: # %entry 87; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 88; CHECK-BE-NEXT: vextuhlx 3, 3, 2 89; CHECK-BE-NEXT: add 3, 3, 6 90; CHECK-BE-NEXT: extsh 3, 3 91; CHECK-BE-NEXT: blr 92entry: 93 %vecext = extractelement <8 x i16> %a, i32 %index 94 %conv5 = zext i16 %vecext to i32 95 %conv16 = zext i16 %c to i32 96 %add = add nuw nsw i32 %conv5, %conv16 97 %conv2 = trunc i32 %add to i16 98 ret i16 %conv2 99} 100 101define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) { 102; CHECK-LE-LABEL: test_add5: 103; CHECK-LE: # %bb.0: # %entry 104; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 105; CHECK-LE-NEXT: vextuwrx 3, 3, 2 106; CHECK-LE-NEXT: add 3, 3, 6 107; CHECK-LE-NEXT: clrldi 3, 3, 32 108; CHECK-LE-NEXT: blr 109; 110; CHECK-BE-LABEL: test_add5: 111; CHECK-BE: # %bb.0: # %entry 112; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 113; CHECK-BE-NEXT: vextuwlx 3, 3, 2 114; CHECK-BE-NEXT: add 3, 3, 6 115; CHECK-BE-NEXT: clrldi 3, 3, 32 116; CHECK-BE-NEXT: blr 117entry: 118 %vecext = extractelement <4 x i32> %a, i32 %index 119 %add = add i32 %vecext, %c 120 ret i32 %add 121} 122 123define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) { 124; CHECK-LE-LABEL: test_add6: 125; CHECK-LE: # %bb.0: # %entry 126; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 127; CHECK-LE-NEXT: vextuwrx 3, 3, 2 128; CHECK-LE-NEXT: add 3, 3, 6 129; CHECK-LE-NEXT: extsw 3, 3 130; CHECK-LE-NEXT: blr 131; 132; CHECK-BE-LABEL: test_add6: 133; CHECK-BE: # %bb.0: # %entry 134; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 135; CHECK-BE-NEXT: vextuwlx 3, 3, 2 136; CHECK-BE-NEXT: add 3, 3, 6 137; CHECK-BE-NEXT: extsw 3, 3 138; CHECK-BE-NEXT: blr 139entry: 140 %vecext = extractelement <4 x i32> %a, i32 %index 141 %add = add nsw i32 %vecext, %c 142 ret i32 %add 143} 144 145; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx 146define zeroext i32 @test7(<4 x i32> %a) { 147; CHECK-LE-LABEL: test7: 148; CHECK-LE: # %bb.0: # %entry 149; CHECK-LE-NEXT: mfvsrwz 3, 34 150; CHECK-LE-NEXT: blr 151; 152; CHECK-BE-LABEL: test7: 153; CHECK-BE: # %bb.0: # %entry 154; CHECK-BE-NEXT: li 3, 8 155; CHECK-BE-NEXT: vextuwlx 3, 3, 2 156; CHECK-BE-NEXT: blr 157entry: 158 %vecext = extractelement <4 x i32> %a, i32 2 159 ret i32 %vecext 160} 161 162define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) { 163; CHECK-LE-LABEL: testadd_7: 164; CHECK-LE: # %bb.0: # %entry 165; CHECK-LE-NEXT: mfvsrwz 3, 34 166; CHECK-LE-NEXT: add 3, 3, 5 167; CHECK-LE-NEXT: clrldi 3, 3, 32 168; CHECK-LE-NEXT: blr 169; 170; CHECK-BE-LABEL: testadd_7: 171; CHECK-BE: # %bb.0: # %entry 172; CHECK-BE-NEXT: li 3, 8 173; CHECK-BE-NEXT: vextuwlx 3, 3, 2 174; CHECK-BE-NEXT: add 3, 3, 5 175; CHECK-BE-NEXT: clrldi 3, 3, 32 176; CHECK-BE-NEXT: blr 177entry: 178 %vecext = extractelement <4 x i32> %a, i32 2 179 %add = add i32 %vecext, %c 180 ret i32 %add 181} 182 183define signext i32 @test8(<4 x i32> %a) { 184; CHECK-LE-LABEL: test8: 185; CHECK-LE: # %bb.0: # %entry 186; CHECK-LE-NEXT: mfvsrwz 3, 34 187; CHECK-LE-NEXT: extsw 3, 3 188; CHECK-LE-NEXT: blr 189; 190; CHECK-BE-LABEL: test8: 191; CHECK-BE: # %bb.0: # %entry 192; CHECK-BE-NEXT: li 3, 8 193; CHECK-BE-NEXT: vextuwlx 3, 3, 2 194; CHECK-BE-NEXT: extsw 3, 3 195; CHECK-BE-NEXT: blr 196entry: 197 %vecext = extractelement <4 x i32> %a, i32 2 198 ret i32 %vecext 199} 200 201define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) { 202; CHECK-LE-LABEL: testadd_8: 203; CHECK-LE: # %bb.0: # %entry 204; CHECK-LE-NEXT: mfvsrwz 3, 34 205; CHECK-LE-NEXT: add 3, 3, 5 206; CHECK-LE-NEXT: extsw 3, 3 207; CHECK-LE-NEXT: blr 208; 209; CHECK-BE-LABEL: testadd_8: 210; CHECK-BE: # %bb.0: # %entry 211; CHECK-BE-NEXT: li 3, 8 212; CHECK-BE-NEXT: vextuwlx 3, 3, 2 213; CHECK-BE-NEXT: add 3, 3, 5 214; CHECK-BE-NEXT: extsw 3, 3 215; CHECK-BE-NEXT: blr 216entry: 217 %vecext = extractelement <4 x i32> %a, i32 2 218 %add = add nsw i32 %vecext, %c 219 ret i32 %add 220} 221 222; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx 223define signext i32 @test9(<4 x i32> %a) { 224; CHECK-LE-LABEL: test9: 225; CHECK-LE: # %bb.0: # %entry 226; CHECK-LE-NEXT: li 3, 4 227; CHECK-LE-NEXT: vextuwrx 3, 3, 2 228; CHECK-LE-NEXT: extsw 3, 3 229; CHECK-LE-NEXT: blr 230; 231; CHECK-BE-LABEL: test9: 232; CHECK-BE: # %bb.0: # %entry 233; CHECK-BE-NEXT: mfvsrwz 3, 34 234; CHECK-BE-NEXT: extsw 3, 3 235; CHECK-BE-NEXT: blr 236entry: 237 %vecext = extractelement <4 x i32> %a, i32 1 238 ret i32 %vecext 239} 240 241define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) { 242; CHECK-LE-LABEL: testadd_9: 243; CHECK-LE: # %bb.0: # %entry 244; CHECK-LE-NEXT: li 3, 4 245; CHECK-LE-NEXT: vextuwrx 3, 3, 2 246; CHECK-LE-NEXT: add 3, 3, 5 247; CHECK-LE-NEXT: extsw 3, 3 248; CHECK-LE-NEXT: blr 249; 250; CHECK-BE-LABEL: testadd_9: 251; CHECK-BE: # %bb.0: # %entry 252; CHECK-BE-NEXT: mfvsrwz 3, 34 253; CHECK-BE-NEXT: add 3, 3, 5 254; CHECK-BE-NEXT: extsw 3, 3 255; CHECK-BE-NEXT: blr 256entry: 257 %vecext = extractelement <4 x i32> %a, i32 1 258 %add = add nsw i32 %vecext, %c 259 ret i32 %add 260} 261