1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
4
5define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
6; CHECK-LE-LABEL: test1:
7; CHECK-LE:       # %bb.0: # %entry
8; CHECK-LE-NEXT:    vextubrx 3, 5, 2
9; CHECK-LE-NEXT:    clrldi 3, 3, 56
10; CHECK-LE-NEXT:    blr
11;
12; CHECK-BE-LABEL: test1:
13; CHECK-BE:       # %bb.0: # %entry
14; CHECK-BE-NEXT:    vextublx 3, 5, 2
15; CHECK-BE-NEXT:    clrldi 3, 3, 56
16; CHECK-BE-NEXT:    blr
17
18entry:
19  %vecext = extractelement <16 x i8> %a, i32 %index
20  ret i8 %vecext
21}
22
23define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
24; CHECK-LE-LABEL: test2:
25; CHECK-LE:       # %bb.0: # %entry
26; CHECK-LE-NEXT:    vextubrx 3, 5, 2
27; CHECK-LE-NEXT:    extsb 3, 3
28; CHECK-LE-NEXT:    blr
29;
30; CHECK-BE-LABEL: test2:
31; CHECK-BE:       # %bb.0: # %entry
32; CHECK-BE-NEXT:    vextublx 3, 5, 2
33; CHECK-BE-NEXT:    extsb 3, 3
34; CHECK-BE-NEXT:    blr
35
36entry:
37  %vecext = extractelement <16 x i8> %a, i32 %index
38  ret i8 %vecext
39}
40
41define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
42; CHECK-LE-LABEL: test3:
43; CHECK-LE:       # %bb.0: # %entry
44; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
45; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
46; CHECK-LE-NEXT:    clrldi 3, 3, 48
47; CHECK-LE-NEXT:    blr
48;
49; CHECK-BE-LABEL: test3:
50; CHECK-BE:       # %bb.0: # %entry
51; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
52; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
53; CHECK-BE-NEXT:    clrldi 3, 3, 48
54; CHECK-BE-NEXT:    blr
55
56entry:
57  %vecext = extractelement <8 x i16> %a, i32 %index
58  ret i16 %vecext
59}
60
61define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
62; CHECK-LE-LABEL: test4:
63; CHECK-LE:       # %bb.0: # %entry
64; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
65; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
66; CHECK-LE-NEXT:    extsh 3, 3
67; CHECK-LE-NEXT:    blr
68;
69; CHECK-BE-LABEL: test4:
70; CHECK-BE:       # %bb.0: # %entry
71; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
72; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
73; CHECK-BE-NEXT:    extsh 3, 3
74; CHECK-BE-NEXT:    blr
75
76entry:
77  %vecext = extractelement <8 x i16> %a, i32 %index
78  ret i16 %vecext
79}
80
81define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
82; CHECK-LE-LABEL: test5:
83; CHECK-LE:       # %bb.0: # %entry
84; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
85; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
86; CHECK-LE-NEXT:    blr
87;
88; CHECK-BE-LABEL: test5:
89; CHECK-BE:       # %bb.0: # %entry
90; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
91; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
92; CHECK-BE-NEXT:    blr
93
94entry:
95  %vecext = extractelement <4 x i32> %a, i32 %index
96  ret i32 %vecext
97}
98
99define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
100; CHECK-LE-LABEL: test6:
101; CHECK-LE:       # %bb.0: # %entry
102; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
103; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
104; CHECK-LE-NEXT:    extsw 3, 3
105; CHECK-LE-NEXT:    blr
106;
107; CHECK-BE-LABEL: test6:
108; CHECK-BE:       # %bb.0: # %entry
109; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
110; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
111; CHECK-BE-NEXT:    extsw 3, 3
112; CHECK-BE-NEXT:    blr
113
114entry:
115  %vecext = extractelement <4 x i32> %a, i32 %index
116  ret i32 %vecext
117}
118
119; Test with immediate index
120define zeroext i8 @test7(<16 x i8> %a) {
121; CHECK-LE-LABEL: test7:
122; CHECK-LE:       # %bb.0: # %entry
123; CHECK-LE-NEXT:    li 3, 1
124; CHECK-LE-NEXT:    vextubrx 3, 3, 2
125; CHECK-LE-NEXT:    clrldi 3, 3, 56
126; CHECK-LE-NEXT:    blr
127;
128; CHECK-BE-LABEL: test7:
129; CHECK-BE:       # %bb.0: # %entry
130; CHECK-BE-NEXT:    li 3, 1
131; CHECK-BE-NEXT:    vextublx 3, 3, 2
132; CHECK-BE-NEXT:    clrldi 3, 3, 56
133; CHECK-BE-NEXT:    blr
134
135entry:
136  %vecext = extractelement <16 x i8> %a, i32 1
137  ret i8 %vecext
138}
139
140define zeroext i16 @test8(<8 x i16> %a) {
141; CHECK-LE-LABEL: test8:
142; CHECK-LE:       # %bb.0: # %entry
143; CHECK-LE-NEXT:    li 3, 2
144; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
145; CHECK-LE-NEXT:    clrldi 3, 3, 48
146; CHECK-LE-NEXT:    blr
147;
148; CHECK-BE-LABEL: test8:
149; CHECK-BE:       # %bb.0: # %entry
150; CHECK-BE-NEXT:    li 3, 2
151; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
152; CHECK-BE-NEXT:    clrldi 3, 3, 48
153; CHECK-BE-NEXT:    blr
154
155entry:
156  %vecext = extractelement <8 x i16> %a, i32 1
157  ret i16 %vecext
158}
159
160define zeroext i32 @test9(<4 x i32> %a) {
161; CHECK-LE-LABEL: test9:
162; CHECK-LE:       # %bb.0: # %entry
163; CHECK-LE-NEXT:    li 3, 12
164; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
165; CHECK-LE-NEXT:    blr
166;
167; CHECK-BE-LABEL: test9:
168; CHECK-BE:       # %bb.0: # %entry
169; CHECK-BE-NEXT:    li 3, 12
170; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
171; CHECK-BE-NEXT:    blr
172
173entry:
174  %vecext = extractelement <4 x i32> %a, i32 3
175  ret i32 %vecext
176}
177
178define double @test10(<4 x i32> %a, <4 x i32> %b) {
179; CHECK-LE-LABEL: test10:
180; CHECK-LE:       # %bb.0: # %entry
181; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
182; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
183; CHECK-LE-NEXT:    lxv 36, 0(3)
184; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
185; CHECK-LE-NEXT:    lfs 0, .LCPI9_1@toc@l(3)
186; CHECK-LE-NEXT:    vperm 2, 3, 2, 4
187; CHECK-LE-NEXT:    xsadddp 1, 34, 0
188; CHECK-LE-NEXT:    blr
189;
190; CHECK-BE-LABEL: test10:
191; CHECK-BE:       # %bb.0: # %entry
192; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
193; CHECK-BE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
194; CHECK-BE-NEXT:    lxv 36, 0(3)
195; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
196; CHECK-BE-NEXT:    lfs 0, .LCPI9_1@toc@l(3)
197; CHECK-BE-NEXT:    vperm 2, 3, 2, 4
198; CHECK-BE-NEXT:    xsadddp 1, 34, 0
199; CHECK-BE-NEXT:    blr
200entry:
201  %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>
202  %cast = bitcast <4 x i32> %shuffle to <2 x double>
203  %extract = extractelement <2 x double> %cast, i32 0
204  %add = fadd double %extract, 1.0000
205  ret double %add
206}
207