1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s
3
4; ISEL matches address mode xaddr.
5define i8 @test_xaddr(i8* %p) {
6; CHECK-LABEL: test_xaddr:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    li r4, 0
9; CHECK-NEXT:    std r3, -8(r1)
10; CHECK-NEXT:    ori r4, r4, 40000
11; CHECK-NEXT:    lbzx r3, r3, r4
12; CHECK-NEXT:    blr
13entry:
14  %p.addr = alloca i8*, align 8
15  store i8* %p, i8** %p.addr, align 8
16  %0 = load i8*, i8** %p.addr, align 8
17  %add.ptr = getelementptr inbounds i8, i8* %0, i64 40000
18  %1 = load i8, i8* %add.ptr, align 1
19  ret i8 %1
20}
21
22; ISEL matches address mode xaddrX4.
23define i64 @test_xaddrX4(i8* %p) {
24; CHECK-LABEL: test_xaddrX4:
25; CHECK:       # %bb.0: # %entry
26; CHECK-NEXT:    li r4, 3
27; CHECK-NEXT:    std r3, -8(r1)
28; CHECK-NEXT:    ldx r3, r3, r4
29; CHECK-NEXT:    blr
30entry:
31  %p.addr = alloca i8*, align 8
32  store i8* %p, i8** %p.addr, align 8
33  %0 = load i8*, i8** %p.addr, align 8
34  %add.ptr = getelementptr inbounds i8, i8* %0, i64 3
35  %1 = bitcast i8* %add.ptr to i64*
36  %2 = load i64, i64* %1, align 8
37  ret i64 %2
38}
39
40; ISEL matches address mode xaddrX16.
41define <2 x double> @test_xaddrX16(double* %arr) {
42; CHECK-LABEL: test_xaddrX16:
43; CHECK:       # %bb.0: # %entry
44; CHECK-NEXT:    li r4, 40
45; CHECK-NEXT:    lxvx vs34, r3, r4
46; CHECK-NEXT:    blr
47entry:
48  %arrayidx1 = getelementptr inbounds double, double* %arr, i64 5
49  %0 = bitcast double* %arrayidx1 to <2 x double>*
50  %1 = load <2 x double>, <2 x double>* %0, align 16
51  ret <2 x double> %1
52}
53
54; ISEL matches address mode xoaddr.
55define void @test_xoaddr(i32* %arr, i32* %arrTo) {
56; CHECK-LABEL: test_xoaddr:
57; CHECK:       # %bb.0: # %entry
58; CHECK-NEXT:    li r5, 8
59; CHECK-NEXT:    lxvx vs0, r3, r5
60; CHECK-NEXT:    li r3, 4
61; CHECK-NEXT:    stxvx vs0, r4, r3
62; CHECK-NEXT:    blr
63entry:
64  %arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
65  %0 = bitcast i32* %arrayidx to <4 x i32>*
66  %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
67  %1 = bitcast i32* %arrayidx1 to <4 x i32>*
68  %2 = load <4 x i32>, <4 x i32>* %1, align 8
69  store <4 x i32> %2, <4 x i32>* %0, align 8
70  ret void
71}
72
73; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
74; loop.
75define i64 @test_xaddrX4_loop(i8* %p) {
76; CHECK-LABEL: test_xaddrX4_loop:
77; CHECK:       # %bb.0: # %entry
78; CHECK-NEXT:    addi r4, r3, -8
79; CHECK-NEXT:    li r3, 8
80; CHECK-NEXT:    li r5, 3
81; CHECK-NEXT:    mtctr r3
82; CHECK-NEXT:    li r3, 0
83; CHECK-NEXT:    .p2align 4
84; CHECK-NEXT:  .LBB4_1: # %for.body
85; CHECK-NEXT:    #
86; CHECK-NEXT:    ldu r6, 8(r4)
87; CHECK-NEXT:    ldx r7, r4, r5
88; CHECK-NEXT:    maddld r3, r7, r6, r3
89; CHECK-NEXT:    bdnz .LBB4_1
90; CHECK-NEXT:  # %bb.2: # %for.end
91; CHECK-NEXT:    blr
92; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
93entry:
94  br label %for.body
95
96for.body:                                         ; preds = %for.body, %entry
97  %i.015 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
98  %res.014 = phi i64 [ 0, %entry ], [ %add, %for.body ]
99  %mul = shl i64 %i.015, 3
100  %add.ptr = getelementptr inbounds i8, i8* %p, i64 %mul
101  %0 = bitcast i8* %add.ptr to i64*
102  %1 = load i64, i64* %0, align 8
103  %add.ptr3 = getelementptr inbounds i8, i8* %add.ptr, i64 3
104  %2 = bitcast i8* %add.ptr3 to i64*
105  %3 = load i64, i64* %2, align 8
106  %mul4 = mul i64 %3, %1
107  %add = add i64 %mul4, %res.014
108  %inc = add nuw nsw i64 %i.015, 1
109  %exitcond = icmp eq i64 %inc, 8
110  br i1 %exitcond, label %for.end, label %for.body
111
112for.end:                                          ; preds = %for.body
113  ret i64 %add
114
115}
116