1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
4; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
7; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
8; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
9; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
10; RUN:  -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-LE-P9
11; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
12; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
13; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7
14; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
15; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
16; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8
17; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
18; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
19; RUN:  -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
20; xscvdpsxws and uxws is only available on Power7 and above
21; Codgen is different for LE Power7 and Power8
22
23define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
24; CHECK-LE-P7-LABEL: test:
25; CHECK-LE-P7:       # %bb.0: # %entry
26; CHECK-LE-P7-NEXT:    xscvdpsxws f0, f1
27; CHECK-LE-P7-NEXT:    addi r3, r1, -4
28; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
29; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI0_0@toc@l
30; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
31; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
32; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
33; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
34; CHECK-LE-P7-NEXT:    addi r3, r1, -32
35; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
36; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
37; CHECK-LE-P7-NEXT:    blr
38;
39; CHECK-LE-P8-LABEL: test:
40; CHECK-LE-P8:       # %bb.0: # %entry
41; CHECK-LE-P8-NEXT:    xscvdpsxws f0, f1
42; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
43; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
44; CHECK-LE-P8-NEXT:    lvx v3, 0, r3
45; CHECK-LE-P8-NEXT:    mffprwz r4, f0
46; CHECK-LE-P8-NEXT:    mtvsrwz v4, r4
47; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
48; CHECK-LE-P8-NEXT:    blr
49;
50; CHECK-LE-P9-LABEL: test:
51; CHECK-LE-P9:       # %bb.0: # %entry
52; CHECK-LE-P9-NEXT:    xscvdpsxws f0, f1
53; CHECK-LE-P9-NEXT:    mffprwz r3, f0
54; CHECK-LE-P9-NEXT:    mtfprwz f0, r3
55; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
56; CHECK-LE-P9-NEXT:    blr
57;
58; CHECK-BE-P7-LABEL: test:
59; CHECK-BE-P7:       # %bb.0: # %entry
60; CHECK-BE-P7-NEXT:    xscvdpsxws f0, f1
61; CHECK-BE-P7-NEXT:    addi r3, r1, -4
62; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
63; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
64; CHECK-BE-P7-NEXT:    xxsldwi vs0, v2, v2, 3
65; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
66; CHECK-BE-P7-NEXT:    addi r3, r1, -32
67; CHECK-BE-P7-NEXT:    lxvw4x vs1, 0, r3
68; CHECK-BE-P7-NEXT:    xxsldwi v2, vs0, vs1, 1
69; CHECK-BE-P7-NEXT:    blr
70;
71; CHECK-BE-P8-LABEL: test:
72; CHECK-BE-P8:       # %bb.0: # %entry
73; CHECK-BE-P8-NEXT:    xscvdpsxws f0, f1
74; CHECK-BE-P8-NEXT:    mffprwz r3, f0
75; CHECK-BE-P8-NEXT:    mtvsrwz v3, r3
76; CHECK-BE-P8-NEXT:    vmrghw v3, v2, v3
77; CHECK-BE-P8-NEXT:    xxsldwi vs0, v3, v2, 3
78; CHECK-BE-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
79; CHECK-BE-P8-NEXT:    blr
80;
81; CHECK-BE-P9-LABEL: test:
82; CHECK-BE-P9:       # %bb.0: # %entry
83; CHECK-BE-P9-NEXT:    xscvdpsxws f0, f1
84; CHECK-BE-P9-NEXT:    mffprwz r3, f0
85; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
86; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
87; CHECK-BE-P9-NEXT:    blr
88entry:
89  %conv = fptosi double %b to i32
90  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
91  ret <4 x i32> %vecins
92}
93
94define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
95; CHECK-LE-P7-LABEL: test2:
96; CHECK-LE-P7:       # %bb.0: # %entry
97; CHECK-LE-P7-NEXT:    xscvdpsxws f0, f1
98; CHECK-LE-P7-NEXT:    addi r3, r1, -4
99; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
100; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI1_0@toc@l
101; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
102; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
103; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
104; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
105; CHECK-LE-P7-NEXT:    addi r3, r1, -32
106; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
107; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
108; CHECK-LE-P7-NEXT:    blr
109;
110; CHECK-LE-P8-LABEL: test2:
111; CHECK-LE-P8:       # %bb.0: # %entry
112; CHECK-LE-P8-NEXT:    xscvdpsxws f0, f1
113; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
114; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
115; CHECK-LE-P8-NEXT:    lvx v3, 0, r3
116; CHECK-LE-P8-NEXT:    mffprwz r4, f0
117; CHECK-LE-P8-NEXT:    mtvsrwz v4, r4
118; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
119; CHECK-LE-P8-NEXT:    blr
120;
121; CHECK-LE-P9-LABEL: test2:
122; CHECK-LE-P9:       # %bb.0: # %entry
123; CHECK-LE-P9-NEXT:    xscvdpsxws f0, f1
124; CHECK-LE-P9-NEXT:    mffprwz r3, f0
125; CHECK-LE-P9-NEXT:    mtfprwz f0, r3
126; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
127; CHECK-LE-P9-NEXT:    blr
128;
129; CHECK-BE-P7-LABEL: test2:
130; CHECK-BE-P7:       # %bb.0: # %entry
131; CHECK-BE-P7-NEXT:    xscvdpsxws f0, f1
132; CHECK-BE-P7-NEXT:    addi r3, r1, -4
133; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
134; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
135; CHECK-BE-P7-NEXT:    xxsldwi vs0, v2, v2, 3
136; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
137; CHECK-BE-P7-NEXT:    addi r3, r1, -32
138; CHECK-BE-P7-NEXT:    lxvw4x vs1, 0, r3
139; CHECK-BE-P7-NEXT:    xxsldwi v2, vs0, vs1, 1
140; CHECK-BE-P7-NEXT:    blr
141;
142; CHECK-BE-P8-LABEL: test2:
143; CHECK-BE-P8:       # %bb.0: # %entry
144; CHECK-BE-P8-NEXT:    xscvdpsxws f0, f1
145; CHECK-BE-P8-NEXT:    mffprwz r3, f0
146; CHECK-BE-P8-NEXT:    mtvsrwz v3, r3
147; CHECK-BE-P8-NEXT:    vmrghw v3, v2, v3
148; CHECK-BE-P8-NEXT:    xxsldwi vs0, v3, v2, 3
149; CHECK-BE-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
150; CHECK-BE-P8-NEXT:    blr
151;
152; CHECK-BE-P9-LABEL: test2:
153; CHECK-BE-P9:       # %bb.0: # %entry
154; CHECK-BE-P9-NEXT:    xscvdpsxws f0, f1
155; CHECK-BE-P9-NEXT:    mffprwz r3, f0
156; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
157; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
158; CHECK-BE-P9-NEXT:    blr
159entry:
160  %conv = fptosi float %b to i32
161  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
162  ret <4 x i32> %vecins
163}
164
165define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
166; CHECK-LE-P7-LABEL: test3:
167; CHECK-LE-P7:       # %bb.0: # %entry
168; CHECK-LE-P7-NEXT:    xscvdpuxws f0, f1
169; CHECK-LE-P7-NEXT:    addi r3, r1, -4
170; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
171; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI2_0@toc@l
172; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
173; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
174; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
175; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
176; CHECK-LE-P7-NEXT:    addi r3, r1, -32
177; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
178; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
179; CHECK-LE-P7-NEXT:    blr
180;
181; CHECK-LE-P8-LABEL: test3:
182; CHECK-LE-P8:       # %bb.0: # %entry
183; CHECK-LE-P8-NEXT:    xscvdpuxws f0, f1
184; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
185; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
186; CHECK-LE-P8-NEXT:    lvx v3, 0, r3
187; CHECK-LE-P8-NEXT:    mffprwz r4, f0
188; CHECK-LE-P8-NEXT:    mtvsrwz v4, r4
189; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
190; CHECK-LE-P8-NEXT:    blr
191;
192; CHECK-LE-P9-LABEL: test3:
193; CHECK-LE-P9:       # %bb.0: # %entry
194; CHECK-LE-P9-NEXT:    xscvdpuxws f0, f1
195; CHECK-LE-P9-NEXT:    mffprwz r3, f0
196; CHECK-LE-P9-NEXT:    mtfprwz f0, r3
197; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
198; CHECK-LE-P9-NEXT:    blr
199;
200; CHECK-BE-P7-LABEL: test3:
201; CHECK-BE-P7:       # %bb.0: # %entry
202; CHECK-BE-P7-NEXT:    xscvdpuxws f0, f1
203; CHECK-BE-P7-NEXT:    addi r3, r1, -4
204; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
205; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
206; CHECK-BE-P7-NEXT:    xxsldwi vs0, v2, v2, 3
207; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
208; CHECK-BE-P7-NEXT:    addi r3, r1, -32
209; CHECK-BE-P7-NEXT:    lxvw4x vs1, 0, r3
210; CHECK-BE-P7-NEXT:    xxsldwi v2, vs0, vs1, 1
211; CHECK-BE-P7-NEXT:    blr
212;
213; CHECK-BE-P8-LABEL: test3:
214; CHECK-BE-P8:       # %bb.0: # %entry
215; CHECK-BE-P8-NEXT:    xscvdpuxws f0, f1
216; CHECK-BE-P8-NEXT:    mffprwz r3, f0
217; CHECK-BE-P8-NEXT:    mtvsrwz v3, r3
218; CHECK-BE-P8-NEXT:    vmrghw v3, v2, v3
219; CHECK-BE-P8-NEXT:    xxsldwi vs0, v3, v2, 3
220; CHECK-BE-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
221; CHECK-BE-P8-NEXT:    blr
222;
223; CHECK-BE-P9-LABEL: test3:
224; CHECK-BE-P9:       # %bb.0: # %entry
225; CHECK-BE-P9-NEXT:    xscvdpuxws f0, f1
226; CHECK-BE-P9-NEXT:    mffprwz r3, f0
227; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
228; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
229; CHECK-BE-P9-NEXT:    blr
230entry:
231  %conv = fptoui double %b to i32
232  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
233  ret <4 x i32> %vecins
234}
235
236define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
237; CHECK-LE-P7-LABEL: test4:
238; CHECK-LE-P7:       # %bb.0: # %entry
239; CHECK-LE-P7-NEXT:    xscvdpuxws f0, f1
240; CHECK-LE-P7-NEXT:    addi r3, r1, -4
241; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
242; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI3_0@toc@l
243; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
244; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
245; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
246; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
247; CHECK-LE-P7-NEXT:    addi r3, r1, -32
248; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
249; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
250; CHECK-LE-P7-NEXT:    blr
251;
252; CHECK-LE-P8-LABEL: test4:
253; CHECK-LE-P8:       # %bb.0: # %entry
254; CHECK-LE-P8-NEXT:    xscvdpuxws f0, f1
255; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
256; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
257; CHECK-LE-P8-NEXT:    lvx v3, 0, r3
258; CHECK-LE-P8-NEXT:    mffprwz r4, f0
259; CHECK-LE-P8-NEXT:    mtvsrwz v4, r4
260; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
261; CHECK-LE-P8-NEXT:    blr
262;
263; CHECK-LE-P9-LABEL: test4:
264; CHECK-LE-P9:       # %bb.0: # %entry
265; CHECK-LE-P9-NEXT:    xscvdpuxws f0, f1
266; CHECK-LE-P9-NEXT:    mffprwz r3, f0
267; CHECK-LE-P9-NEXT:    mtfprwz f0, r3
268; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
269; CHECK-LE-P9-NEXT:    blr
270;
271; CHECK-BE-P7-LABEL: test4:
272; CHECK-BE-P7:       # %bb.0: # %entry
273; CHECK-BE-P7-NEXT:    xscvdpuxws f0, f1
274; CHECK-BE-P7-NEXT:    addi r3, r1, -4
275; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
276; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
277; CHECK-BE-P7-NEXT:    xxsldwi vs0, v2, v2, 3
278; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
279; CHECK-BE-P7-NEXT:    addi r3, r1, -32
280; CHECK-BE-P7-NEXT:    lxvw4x vs1, 0, r3
281; CHECK-BE-P7-NEXT:    xxsldwi v2, vs0, vs1, 1
282; CHECK-BE-P7-NEXT:    blr
283;
284; CHECK-BE-P8-LABEL: test4:
285; CHECK-BE-P8:       # %bb.0: # %entry
286; CHECK-BE-P8-NEXT:    xscvdpuxws f0, f1
287; CHECK-BE-P8-NEXT:    mffprwz r3, f0
288; CHECK-BE-P8-NEXT:    mtvsrwz v3, r3
289; CHECK-BE-P8-NEXT:    vmrghw v3, v2, v3
290; CHECK-BE-P8-NEXT:    xxsldwi vs0, v3, v2, 3
291; CHECK-BE-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
292; CHECK-BE-P8-NEXT:    blr
293;
294; CHECK-BE-P9-LABEL: test4:
295; CHECK-BE-P9:       # %bb.0: # %entry
296; CHECK-BE-P9-NEXT:    xscvdpuxws f0, f1
297; CHECK-BE-P9-NEXT:    mffprwz r3, f0
298; CHECK-BE-P9-NEXT:    mtfprwz f0, r3
299; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
300; CHECK-BE-P9-NEXT:    blr
301entry:
302  %conv = fptoui float %b to i32
303  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
304  ret <4 x i32> %vecins
305}
306