1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
4; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
7; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
8; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
9; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
10; RUN:  -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-LE-P9
11; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
12; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
13; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7
14; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
15; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
16; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8
17; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
18; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
19; RUN:  -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
20; xscvdpsxws and xscvdpsxws is only available on Power7 and above
21; Codgen is different for Power7, Power8, and Power9.
22
23define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
24; CHECK-LE-P7-LABEL: test:
25; CHECK-LE-P7:       # %bb.0: # %entry
26; CHECK-LE-P7-NEXT:    xscvdpsxws f0, f1
27; CHECK-LE-P7-NEXT:    addi r3, r1, -4
28; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
29; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI0_0@toc@l
30; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
31; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
32; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
33; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
34; CHECK-LE-P7-NEXT:    addi r3, r1, -32
35; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
36; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
37; CHECK-LE-P7-NEXT:    blr
38;
39; CHECK-LE-P8-LABEL: test:
40; CHECK-LE-P8:       # %bb.0: # %entry
41; CHECK-LE-P8-NEXT:    xscvdpsxws v3, f1
42; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
43; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
44; CHECK-LE-P8-NEXT:    lvx v4, 0, r3
45; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
46; CHECK-LE-P8-NEXT:    blr
47;
48; CHECK-LE-P9-LABEL: test:
49; CHECK-LE-P9:       # %bb.0: # %entry
50; CHECK-LE-P9-NEXT:    xscvdpsxws f0, f1
51; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
52; CHECK-LE-P9-NEXT:    blr
53;
54; CHECK-BE-P7-LABEL: test:
55; CHECK-BE-P7:       # %bb.0: # %entry
56; CHECK-BE-P7-NEXT:    xscvdpsxws f0, f1
57; CHECK-BE-P7-NEXT:    addi r3, r1, -4
58; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
59; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
60; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
61; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
62; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI0_0@toc@l
63; CHECK-BE-P7-NEXT:    addi r4, r1, -32
64; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
65; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
66; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
67; CHECK-BE-P7-NEXT:    blr
68;
69; CHECK-BE-P8-LABEL: test:
70; CHECK-BE-P8:       # %bb.0: # %entry
71; CHECK-BE-P8-NEXT:    xscvdpsxws v3, f1
72; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
73; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
74; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r3
75; CHECK-BE-P8-NEXT:    vperm v2, v2, v3, v4
76; CHECK-BE-P8-NEXT:    blr
77;
78; CHECK-BE-P9-LABEL: test:
79; CHECK-BE-P9:       # %bb.0: # %entry
80; CHECK-BE-P9-NEXT:    xscvdpsxws f0, f1
81; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
82; CHECK-BE-P9-NEXT:    blr
83entry:
84  %conv = fptosi double %b to i32
85  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
86  ret <4 x i32> %vecins
87}
88
89define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
90; CHECK-LE-P7-LABEL: test2:
91; CHECK-LE-P7:       # %bb.0: # %entry
92; CHECK-LE-P7-NEXT:    xscvdpsxws f0, f1
93; CHECK-LE-P7-NEXT:    addi r3, r1, -4
94; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
95; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI1_0@toc@l
96; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
97; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
98; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
99; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
100; CHECK-LE-P7-NEXT:    addi r3, r1, -32
101; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
102; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
103; CHECK-LE-P7-NEXT:    blr
104;
105; CHECK-LE-P8-LABEL: test2:
106; CHECK-LE-P8:       # %bb.0: # %entry
107; CHECK-LE-P8-NEXT:    xscvdpsxws v3, f1
108; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
109; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
110; CHECK-LE-P8-NEXT:    lvx v4, 0, r3
111; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
112; CHECK-LE-P8-NEXT:    blr
113;
114; CHECK-LE-P9-LABEL: test2:
115; CHECK-LE-P9:       # %bb.0: # %entry
116; CHECK-LE-P9-NEXT:    xscvdpsxws f0, f1
117; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
118; CHECK-LE-P9-NEXT:    blr
119;
120; CHECK-BE-P7-LABEL: test2:
121; CHECK-BE-P7:       # %bb.0: # %entry
122; CHECK-BE-P7-NEXT:    xscvdpsxws f0, f1
123; CHECK-BE-P7-NEXT:    addi r3, r1, -4
124; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
125; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
126; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
127; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
128; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI1_0@toc@l
129; CHECK-BE-P7-NEXT:    addi r4, r1, -32
130; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
131; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
132; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
133; CHECK-BE-P7-NEXT:    blr
134;
135; CHECK-BE-P8-LABEL: test2:
136; CHECK-BE-P8:       # %bb.0: # %entry
137; CHECK-BE-P8-NEXT:    xscvdpsxws v3, f1
138; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
139; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
140; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r3
141; CHECK-BE-P8-NEXT:    vperm v2, v2, v3, v4
142; CHECK-BE-P8-NEXT:    blr
143;
144; CHECK-BE-P9-LABEL: test2:
145; CHECK-BE-P9:       # %bb.0: # %entry
146; CHECK-BE-P9-NEXT:    xscvdpsxws f0, f1
147; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
148; CHECK-BE-P9-NEXT:    blr
149entry:
150  %conv = fptosi float %b to i32
151  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
152  ret <4 x i32> %vecins
153}
154
155define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
156; CHECK-LE-P7-LABEL: test3:
157; CHECK-LE-P7:       # %bb.0: # %entry
158; CHECK-LE-P7-NEXT:    xscvdpuxws f0, f1
159; CHECK-LE-P7-NEXT:    addi r3, r1, -4
160; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
161; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI2_0@toc@l
162; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
163; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
164; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
165; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
166; CHECK-LE-P7-NEXT:    addi r3, r1, -32
167; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
168; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
169; CHECK-LE-P7-NEXT:    blr
170;
171; CHECK-LE-P8-LABEL: test3:
172; CHECK-LE-P8:       # %bb.0: # %entry
173; CHECK-LE-P8-NEXT:    xscvdpuxws v3, f1
174; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
175; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
176; CHECK-LE-P8-NEXT:    lvx v4, 0, r3
177; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
178; CHECK-LE-P8-NEXT:    blr
179;
180; CHECK-LE-P9-LABEL: test3:
181; CHECK-LE-P9:       # %bb.0: # %entry
182; CHECK-LE-P9-NEXT:    xscvdpuxws f0, f1
183; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
184; CHECK-LE-P9-NEXT:    blr
185;
186; CHECK-BE-P7-LABEL: test3:
187; CHECK-BE-P7:       # %bb.0: # %entry
188; CHECK-BE-P7-NEXT:    xscvdpuxws f0, f1
189; CHECK-BE-P7-NEXT:    addi r3, r1, -4
190; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
191; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
192; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
193; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
194; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI2_0@toc@l
195; CHECK-BE-P7-NEXT:    addi r4, r1, -32
196; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
197; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
198; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
199; CHECK-BE-P7-NEXT:    blr
200;
201; CHECK-BE-P8-LABEL: test3:
202; CHECK-BE-P8:       # %bb.0: # %entry
203; CHECK-BE-P8-NEXT:    xscvdpuxws v3, f1
204; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
205; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
206; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r3
207; CHECK-BE-P8-NEXT:    vperm v2, v2, v3, v4
208; CHECK-BE-P8-NEXT:    blr
209;
210; CHECK-BE-P9-LABEL: test3:
211; CHECK-BE-P9:       # %bb.0: # %entry
212; CHECK-BE-P9-NEXT:    xscvdpuxws f0, f1
213; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
214; CHECK-BE-P9-NEXT:    blr
215entry:
216  %conv = fptoui double %b to i32
217  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
218  ret <4 x i32> %vecins
219}
220
221define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
222; CHECK-LE-P7-LABEL: test4:
223; CHECK-LE-P7:       # %bb.0: # %entry
224; CHECK-LE-P7-NEXT:    xscvdpuxws f0, f1
225; CHECK-LE-P7-NEXT:    addi r3, r1, -4
226; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
227; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI3_0@toc@l
228; CHECK-LE-P7-NEXT:    lvx v3, 0, r4
229; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
230; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
231; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
232; CHECK-LE-P7-NEXT:    addi r3, r1, -32
233; CHECK-LE-P7-NEXT:    lvx v4, 0, r3
234; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
235; CHECK-LE-P7-NEXT:    blr
236;
237; CHECK-LE-P8-LABEL: test4:
238; CHECK-LE-P8:       # %bb.0: # %entry
239; CHECK-LE-P8-NEXT:    xscvdpuxws v3, f1
240; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
241; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
242; CHECK-LE-P8-NEXT:    lvx v4, 0, r3
243; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
244; CHECK-LE-P8-NEXT:    blr
245;
246; CHECK-LE-P9-LABEL: test4:
247; CHECK-LE-P9:       # %bb.0: # %entry
248; CHECK-LE-P9-NEXT:    xscvdpuxws f0, f1
249; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
250; CHECK-LE-P9-NEXT:    blr
251;
252; CHECK-BE-P7-LABEL: test4:
253; CHECK-BE-P7:       # %bb.0: # %entry
254; CHECK-BE-P7-NEXT:    xscvdpuxws f0, f1
255; CHECK-BE-P7-NEXT:    addi r3, r1, -4
256; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
257; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
258; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
259; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
260; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI3_0@toc@l
261; CHECK-BE-P7-NEXT:    addi r4, r1, -32
262; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
263; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
264; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
265; CHECK-BE-P7-NEXT:    blr
266;
267; CHECK-BE-P8-LABEL: test4:
268; CHECK-BE-P8:       # %bb.0: # %entry
269; CHECK-BE-P8-NEXT:    xscvdpuxws v3, f1
270; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
271; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
272; CHECK-BE-P8-NEXT:    lxvw4x v4, 0, r3
273; CHECK-BE-P8-NEXT:    vperm v2, v2, v3, v4
274; CHECK-BE-P8-NEXT:    blr
275;
276; CHECK-BE-P9-LABEL: test4:
277; CHECK-BE-P9:       # %bb.0: # %entry
278; CHECK-BE-P9-NEXT:    xscvdpuxws f0, f1
279; CHECK-BE-P9-NEXT:    xxinsertw v2, vs0, 12
280; CHECK-BE-P9-NEXT:    blr
281entry:
282  %conv = fptoui float %b to i32
283  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
284  ret <4 x i32> %vecins
285}
286