1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
3
4; If positive...
5
6define i32 @zext_ifpos(i32 %x) {
7; CHECK-LABEL: zext_ifpos:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
10; CHECK-NEXT:    xori 3, 3, 1
11; CHECK-NEXT:    blr
12  %c = icmp sgt i32 %x, -1
13  %e = zext i1 %c to i32
14  ret i32 %e
15}
16
17define i32 @add_zext_ifpos(i32 %x) {
18; CHECK-LABEL: add_zext_ifpos:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    srawi 3, 3, 31
21; CHECK-NEXT:    addi 3, 3, 42
22; CHECK-NEXT:    blr
23  %c = icmp sgt i32 %x, -1
24  %e = zext i1 %c to i32
25  %r = add i32 %e, 41
26  ret i32 %r
27}
28
29define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
30; CHECK-LABEL: add_zext_ifpos_vec_splat:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    xxleqv 35, 35, 35
33; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
34; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
35; CHECK-NEXT:    vcmpgtsw 2, 2, 3
36; CHECK-NEXT:    lxvd2x 0, 0, 3
37; CHECK-NEXT:    xxswapd 35, 0
38; CHECK-NEXT:    vsubuwm 2, 3, 2
39; CHECK-NEXT:    blr
40  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
41  %e = zext <4 x i1> %c to <4 x i32>
42  %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
43  ret <4 x i32> %r
44}
45
46define i32 @sel_ifpos_tval_bigger(i32 %x) {
47; CHECK-LABEL: sel_ifpos_tval_bigger:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
50; CHECK-NEXT:    xori 3, 3, 1
51; CHECK-NEXT:    addi 3, 3, 41
52; CHECK-NEXT:    blr
53  %c = icmp sgt i32 %x, -1
54  %r = select i1 %c, i32 42, i32 41
55  ret i32 %r
56}
57
58define i32 @sext_ifpos(i32 %x) {
59; CHECK-LABEL: sext_ifpos:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    not 3, 3
62; CHECK-NEXT:    srawi 3, 3, 31
63; CHECK-NEXT:    blr
64  %c = icmp sgt i32 %x, -1
65  %e = sext i1 %c to i32
66  ret i32 %e
67}
68
69define i32 @add_sext_ifpos(i32 %x) {
70; CHECK-LABEL: add_sext_ifpos:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    srwi 3, 3, 31
73; CHECK-NEXT:    addi 3, 3, 41
74; CHECK-NEXT:    blr
75  %c = icmp sgt i32 %x, -1
76  %e = sext i1 %c to i32
77  %r = add i32 %e, 42
78  ret i32 %r
79}
80
81define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
82; CHECK-LABEL: add_sext_ifpos_vec_splat:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    xxleqv 35, 35, 35
85; CHECK-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
86; CHECK-NEXT:    addi 3, 3, .LCPI6_0@toc@l
87; CHECK-NEXT:    vcmpgtsw 2, 2, 3
88; CHECK-NEXT:    lxvd2x 0, 0, 3
89; CHECK-NEXT:    xxswapd 35, 0
90; CHECK-NEXT:    vadduwm 2, 2, 3
91; CHECK-NEXT:    blr
92  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
93  %e = sext <4 x i1> %c to <4 x i32>
94  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
95  ret <4 x i32> %r
96}
97
98define i32 @sel_ifpos_fval_bigger(i32 %x) {
99; CHECK-LABEL: sel_ifpos_fval_bigger:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
102; CHECK-NEXT:    xori 3, 3, 1
103; CHECK-NEXT:    subfic 3, 3, 42
104; CHECK-NEXT:    blr
105  %c = icmp sgt i32 %x, -1
106  %r = select i1 %c, i32 41, i32 42
107  ret i32 %r
108}
109
110; If negative...
111
112define i32 @zext_ifneg(i32 %x) {
113; CHECK-LABEL: zext_ifneg:
114; CHECK:       # %bb.0:
115; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
116; CHECK-NEXT:    blr
117  %c = icmp slt i32 %x, 0
118  %r = zext i1 %c to i32
119  ret i32 %r
120}
121
122define i32 @add_zext_ifneg(i32 %x) {
123; CHECK-LABEL: add_zext_ifneg:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    srwi 3, 3, 31
126; CHECK-NEXT:    addi 3, 3, 41
127; CHECK-NEXT:    blr
128  %c = icmp slt i32 %x, 0
129  %e = zext i1 %c to i32
130  %r = add i32 %e, 41
131  ret i32 %r
132}
133
134define i32 @sel_ifneg_tval_bigger(i32 %x) {
135; CHECK-LABEL: sel_ifneg_tval_bigger:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
138; CHECK-NEXT:    addi 3, 3, 41
139; CHECK-NEXT:    blr
140  %c = icmp slt i32 %x, 0
141  %r = select i1 %c, i32 42, i32 41
142  ret i32 %r
143}
144
145define i32 @sext_ifneg(i32 %x) {
146; CHECK-LABEL: sext_ifneg:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    srawi 3, 3, 31
149; CHECK-NEXT:    blr
150  %c = icmp slt i32 %x, 0
151  %r = sext i1 %c to i32
152  ret i32 %r
153}
154
155define i32 @add_sext_ifneg(i32 %x) {
156; CHECK-LABEL: add_sext_ifneg:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    srawi 3, 3, 31
159; CHECK-NEXT:    addi 3, 3, 42
160; CHECK-NEXT:    blr
161  %c = icmp slt i32 %x, 0
162  %e = sext i1 %c to i32
163  %r = add i32 %e, 42
164  ret i32 %r
165}
166
167define i32 @sel_ifneg_fval_bigger(i32 %x) {
168; CHECK-LABEL: sel_ifneg_fval_bigger:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
171; CHECK-NEXT:    subfic 3, 3, 42
172; CHECK-NEXT:    blr
173  %c = icmp slt i32 %x, 0
174  %r = select i1 %c, i32 41, i32 42
175  ret i32 %r
176}
177
178define i32 @add_lshr_not(i32 %x) {
179; CHECK-LABEL: add_lshr_not:
180; CHECK:       # %bb.0:
181; CHECK-NEXT:    srawi 3, 3, 31
182; CHECK-NEXT:    addi 3, 3, 42
183; CHECK-NEXT:    blr
184  %not = xor i32 %x, -1
185  %sh = lshr i32 %not, 31
186  %r = add i32 %sh, 41
187  ret i32 %r
188}
189
190define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
191; CHECK-LABEL: add_lshr_not_vec_splat:
192; CHECK:       # %bb.0:
193; CHECK-NEXT:    vspltisw 3, -16
194; CHECK-NEXT:    vspltisw 4, 15
195; CHECK-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
196; CHECK-NEXT:    addi 3, 3, .LCPI15_0@toc@l
197; CHECK-NEXT:    lxvd2x 0, 0, 3
198; CHECK-NEXT:    vsubuwm 3, 4, 3
199; CHECK-NEXT:    vsraw 2, 2, 3
200; CHECK-NEXT:    xxswapd 35, 0
201; CHECK-NEXT:    vadduwm 2, 2, 3
202; CHECK-NEXT:    blr
203  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
204  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
205  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
206  ret <4 x i32> %r
207}
208
209define i32 @sub_lshr_not(i32 %x) {
210; CHECK-LABEL: sub_lshr_not:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    srwi 3, 3, 31
213; CHECK-NEXT:    ori 3, 3, 42
214; CHECK-NEXT:    blr
215  %not = xor i32 %x, -1
216  %sh = lshr i32 %not, 31
217  %r = sub i32 43, %sh
218  ret i32 %r
219}
220
221define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
222; CHECK-LABEL: sub_lshr_not_vec_splat:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vspltisw 3, -16
225; CHECK-NEXT:    vspltisw 4, 15
226; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
227; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
228; CHECK-NEXT:    lxvd2x 0, 0, 3
229; CHECK-NEXT:    vsubuwm 3, 4, 3
230; CHECK-NEXT:    vsrw 2, 2, 3
231; CHECK-NEXT:    xxswapd 35, 0
232; CHECK-NEXT:    vadduwm 2, 2, 3
233; CHECK-NEXT:    blr
234  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
235  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
236  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
237  ret <4 x i32> %r
238}
239
240define i32 @sub_lshr(i32 %x, i32 %y) {
241; CHECK-LABEL: sub_lshr:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    srawi 3, 3, 31
244; CHECK-NEXT:    add 3, 4, 3
245; CHECK-NEXT:    blr
246  %sh = lshr i32 %x, 31
247  %r = sub i32 %y, %sh
248  ret i32 %r
249}
250
251define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
252; CHECK-LABEL: sub_lshr_vec:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    vspltisw 4, -16
255; CHECK-NEXT:    vspltisw 5, 15
256; CHECK-NEXT:    vsubuwm 4, 5, 4
257; CHECK-NEXT:    vsraw 2, 2, 4
258; CHECK-NEXT:    vadduwm 2, 3, 2
259; CHECK-NEXT:    blr
260  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
261  %r = sub <4 x i32> %y, %sh
262  ret <4 x i32> %r
263}
264
265define i32 @sub_const_op_lshr(i32 %x) {
266; CHECK-LABEL: sub_const_op_lshr:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    srawi 3, 3, 31
269; CHECK-NEXT:    addi 3, 3, 43
270; CHECK-NEXT:    blr
271  %sh = lshr i32 %x, 31
272  %r = sub i32 43, %sh
273  ret i32 %r
274}
275
276define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
277; CHECK-LABEL: sub_const_op_lshr_vec:
278; CHECK:       # %bb.0:
279; CHECK-NEXT:    vspltisw 3, -16
280; CHECK-NEXT:    vspltisw 4, 15
281; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
282; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
283; CHECK-NEXT:    lxvd2x 0, 0, 3
284; CHECK-NEXT:    vsubuwm 3, 4, 3
285; CHECK-NEXT:    vsraw 2, 2, 3
286; CHECK-NEXT:    xxswapd 35, 0
287; CHECK-NEXT:    vadduwm 2, 2, 3
288; CHECK-NEXT:    blr
289  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
290  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
291  ret <4 x i32> %r
292}
293
294