1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
3; RUN:   -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
4; RUN:   -check-prefix=CHECK-LE %s
5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
6; RUN:   -mtriple=powerpc-linux-gnu < %s | FileCheck \
7; RUN:   -check-prefix=CHECK-32 %s
8
9define i64 @f0(i64 %x) {
10; CHECK-LE-LABEL: f0:
11; CHECK-LE:       # %bb.0:
12; CHECK-LE-NEXT:    li r4, 125
13; CHECK-LE-NEXT:    cmpdi r3, 0
14; CHECK-LE-NEXT:    li r3, -3
15; CHECK-LE-NEXT:    isellt r3, r3, r4
16; CHECK-LE-NEXT:    blr
17;
18; CHECK-32-LABEL: f0:
19; CHECK-32:       # %bb.0:
20; CHECK-32-NEXT:    li r4, 125
21; CHECK-32-NEXT:    li r5, -3
22; CHECK-32-NEXT:    cmpwi r3, 0
23; CHECK-32-NEXT:    bc 12, lt, .LBB0_1
24; CHECK-32-NEXT:    b .LBB0_2
25; CHECK-32-NEXT:  .LBB0_1:
26; CHECK-32-NEXT:    addi r4, r5, 0
27; CHECK-32-NEXT:  .LBB0_2:
28; CHECK-32-NEXT:    srawi r3, r3, 31
29; CHECK-32-NEXT:    blr
30  %c = icmp slt i64 %x, 0
31  %r = select i1 %c, i64 -3, i64 125
32  ret i64 %r
33}
34
35define i64 @f1(i64 %x) {
36; CHECK-LE-LABEL: f1:
37; CHECK-LE:       # %bb.0:
38; CHECK-LE-NEXT:    li r4, 512
39; CHECK-LE-NEXT:    cmpdi r3, 0
40; CHECK-LE-NEXT:    li r3, 64
41; CHECK-LE-NEXT:    isellt r3, r3, r4
42; CHECK-LE-NEXT:    blr
43;
44; CHECK-32-LABEL: f1:
45; CHECK-32:       # %bb.0:
46; CHECK-32-NEXT:    li r4, 512
47; CHECK-32-NEXT:    cmpwi r3, 0
48; CHECK-32-NEXT:    li r3, 64
49; CHECK-32-NEXT:    bc 12, lt, .LBB1_1
50; CHECK-32-NEXT:    b .LBB1_2
51; CHECK-32-NEXT:  .LBB1_1:
52; CHECK-32-NEXT:    addi r4, r3, 0
53; CHECK-32-NEXT:  .LBB1_2:
54; CHECK-32-NEXT:    li r3, 0
55; CHECK-32-NEXT:    blr
56  %c = icmp slt i64 %x, 0
57  %r = select i1 %c, i64 64, i64 512
58  ret i64 %r
59}
60
61define i64 @f2(i64 %x) {
62; CHECK-LE-LABEL: f2:
63; CHECK-LE:       # %bb.0:
64; CHECK-LE-NEXT:    li r4, 1024
65; CHECK-LE-NEXT:    cmpdi r3, 0
66; CHECK-LE-NEXT:    iseleq r3, 0, r4
67; CHECK-LE-NEXT:    blr
68;
69; CHECK-32-LABEL: f2:
70; CHECK-32:       # %bb.0:
71; CHECK-32-NEXT:    or. r3, r4, r3
72; CHECK-32-NEXT:    li r3, 1024
73; CHECK-32-NEXT:    bc 12, eq, .LBB2_2
74; CHECK-32-NEXT:  # %bb.1:
75; CHECK-32-NEXT:    ori r4, r3, 0
76; CHECK-32-NEXT:    b .LBB2_3
77; CHECK-32-NEXT:  .LBB2_2:
78; CHECK-32-NEXT:    li r4, 0
79; CHECK-32-NEXT:  .LBB2_3:
80; CHECK-32-NEXT:    li r3, 0
81; CHECK-32-NEXT:    blr
82  %c = icmp eq i64 %x, 0
83  %r = select i1 %c, i64 0, i64 1024
84  ret i64 %r
85}
86
87define i64 @f3(i64 %x, i64 %y) {
88; CHECK-LE-LABEL: f3:
89; CHECK-LE:       # %bb.0:
90; CHECK-LE-NEXT:    cmpldi r3, 0
91; CHECK-LE-NEXT:    iseleq r3, 0, r4
92; CHECK-LE-NEXT:    blr
93;
94; CHECK-32-LABEL: f3:
95; CHECK-32:       # %bb.0:
96; CHECK-32-NEXT:    or. r3, r4, r3
97; CHECK-32-NEXT:    bc 12, eq, .LBB3_2
98; CHECK-32-NEXT:  # %bb.1:
99; CHECK-32-NEXT:    ori r3, r5, 0
100; CHECK-32-NEXT:    ori r4, r6, 0
101; CHECK-32-NEXT:    blr
102; CHECK-32-NEXT:  .LBB3_2:
103; CHECK-32-NEXT:    li r3, 0
104; CHECK-32-NEXT:    li r4, 0
105; CHECK-32-NEXT:    blr
106  %c = icmp eq i64 %x, 0
107  %r = select i1 %c, i64 0, i64 %y
108  ret i64 %r
109}
110
111define i64 @f4(i64 %x) {
112; CHECK-LE-LABEL: f4:
113; CHECK-LE:       # %bb.0:
114; CHECK-LE-NEXT:    neg r4, r3
115; CHECK-LE-NEXT:    cmpdi r3, 0
116; CHECK-LE-NEXT:    iselgt r3, r4, r3
117; CHECK-LE-NEXT:    blr
118;
119; CHECK-32-LABEL: f4:
120; CHECK-32:       # %bb.0:
121; CHECK-32-NEXT:    cmplwi r3, 0
122; CHECK-32-NEXT:    cmpwi cr1, r3, 0
123; CHECK-32-NEXT:    crandc 4*cr5+lt, 4*cr1+gt, eq
124; CHECK-32-NEXT:    cmpwi cr1, r4, 0
125; CHECK-32-NEXT:    subfic r5, r4, 0
126; CHECK-32-NEXT:    crandc 4*cr5+gt, eq, 4*cr1+eq
127; CHECK-32-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
128; CHECK-32-NEXT:    subfze r6, r3
129; CHECK-32-NEXT:    bc 12, 4*cr5+lt, .LBB4_1
130; CHECK-32-NEXT:    blr
131; CHECK-32-NEXT:  .LBB4_1:
132; CHECK-32-NEXT:    addi r3, r6, 0
133; CHECK-32-NEXT:    addi r4, r5, 0
134; CHECK-32-NEXT:    blr
135  %c = icmp sgt i64 %x, 0
136  %x.neg = sub i64 0, %x
137  %r = select i1 %c, i64 %x.neg, i64 %x
138  ret i64 %r
139}
140
141define i64 @f4_sge_0(i64 %x) {
142; CHECK-LE-LABEL: f4_sge_0:
143; CHECK-LE:       # %bb.0:
144; CHECK-LE-NEXT:    neg r4, r3
145; CHECK-LE-NEXT:    cmpdi r3, -1
146; CHECK-LE-NEXT:    iselgt r3, r4, r3
147; CHECK-LE-NEXT:    blr
148;
149; CHECK-32-LABEL: f4_sge_0:
150; CHECK-32:       # %bb.0:
151; CHECK-32-NEXT:    subfic r5, r4, 0
152; CHECK-32-NEXT:    subfze r6, r3
153; CHECK-32-NEXT:    cmpwi r3, -1
154; CHECK-32-NEXT:    bc 12, gt, .LBB5_1
155; CHECK-32-NEXT:    blr
156; CHECK-32-NEXT:  .LBB5_1:
157; CHECK-32-NEXT:    addi r3, r6, 0
158; CHECK-32-NEXT:    addi r4, r5, 0
159; CHECK-32-NEXT:    blr
160  %c = icmp sge i64 %x, 0
161  %x.neg = sub i64 0, %x
162  %r = select i1 %c, i64 %x.neg, i64 %x
163  ret i64 %r
164}
165
166define i64 @f4_slt_0(i64 %x) {
167; CHECK-LE-LABEL: f4_slt_0:
168; CHECK-LE:       # %bb.0:
169; CHECK-LE-NEXT:    neg r4, r3
170; CHECK-LE-NEXT:    cmpdi r3, 0
171; CHECK-LE-NEXT:    isellt r3, r3, r4
172; CHECK-LE-NEXT:    blr
173;
174; CHECK-32-LABEL: f4_slt_0:
175; CHECK-32:       # %bb.0:
176; CHECK-32-NEXT:    subfic r5, r4, 0
177; CHECK-32-NEXT:    subfze r6, r3
178; CHECK-32-NEXT:    cmpwi r3, 0
179; CHECK-32-NEXT:    bclr 12, lt, 0
180; CHECK-32-NEXT:  # %bb.1:
181; CHECK-32-NEXT:    ori r3, r6, 0
182; CHECK-32-NEXT:    ori r4, r5, 0
183; CHECK-32-NEXT:    blr
184  %c = icmp slt i64 %x, 0
185  %x.neg = sub i64 0, %x
186  %r = select i1 %c, i64 %x, i64 %x.neg
187  ret i64 %r
188}
189
190define i64 @f4_sle_0(i64 %x) {
191; CHECK-LE-LABEL: f4_sle_0:
192; CHECK-LE:       # %bb.0:
193; CHECK-LE-NEXT:    neg r4, r3
194; CHECK-LE-NEXT:    cmpdi r3, 1
195; CHECK-LE-NEXT:    isellt r3, r3, r4
196; CHECK-LE-NEXT:    blr
197;
198; CHECK-32-LABEL: f4_sle_0:
199; CHECK-32:       # %bb.0:
200; CHECK-32-NEXT:    cmplwi r3, 0
201; CHECK-32-NEXT:    cmpwi cr1, r3, 0
202; CHECK-32-NEXT:    crandc 4*cr5+lt, 4*cr1+lt, eq
203; CHECK-32-NEXT:    cmpwi cr1, r4, 0
204; CHECK-32-NEXT:    subfic r5, r4, 0
205; CHECK-32-NEXT:    crand 4*cr5+gt, eq, 4*cr1+eq
206; CHECK-32-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
207; CHECK-32-NEXT:    subfze r6, r3
208; CHECK-32-NEXT:    bclr 12, 4*cr5+lt, 0
209; CHECK-32-NEXT:  # %bb.1:
210; CHECK-32-NEXT:    ori r3, r6, 0
211; CHECK-32-NEXT:    ori r4, r5, 0
212; CHECK-32-NEXT:    blr
213  %c = icmp sle i64 %x, 0
214  %x.neg = sub i64 0, %x
215  %r = select i1 %c, i64 %x, i64 %x.neg
216  ret i64 %r
217}
218
219define i64 @f4_sgt_m1(i64 %x) {
220; CHECK-LE-LABEL: f4_sgt_m1:
221; CHECK-LE:       # %bb.0:
222; CHECK-LE-NEXT:    neg r4, r3
223; CHECK-LE-NEXT:    cmpdi r3, -1
224; CHECK-LE-NEXT:    iselgt r3, r4, r3
225; CHECK-LE-NEXT:    blr
226;
227; CHECK-32-LABEL: f4_sgt_m1:
228; CHECK-32:       # %bb.0:
229; CHECK-32-NEXT:    subfic r5, r4, 0
230; CHECK-32-NEXT:    subfze r6, r3
231; CHECK-32-NEXT:    cmpwi r3, -1
232; CHECK-32-NEXT:    bc 12, gt, .LBB8_1
233; CHECK-32-NEXT:    blr
234; CHECK-32-NEXT:  .LBB8_1:
235; CHECK-32-NEXT:    addi r3, r6, 0
236; CHECK-32-NEXT:    addi r4, r5, 0
237; CHECK-32-NEXT:    blr
238  %c = icmp sgt i64 %x, -1
239  %x.neg = sub i64 0, %x
240  %r = select i1 %c, i64 %x.neg, i64 %x
241  ret i64 %r
242}
243