1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
3; RUN:   -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
4; RUN:   -check-prefix=CHECK-LE %s
5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
6; RUN:   -mtriple=powerpc-linux-gnu < %s | FileCheck \
7; RUN:   -check-prefix=CHECK-32 %s
8
9define i64 @f0(i64 %x) {
10; CHECK-LE-LABEL: f0:
11; CHECK-LE:       # %bb.0:
12; CHECK-LE-NEXT:    li r4, 125
13; CHECK-LE-NEXT:    cmpdi r3, 0
14; CHECK-LE-NEXT:    li r3, -3
15; CHECK-LE-NEXT:    isellt r3, r3, r4
16; CHECK-LE-NEXT:    blr
17;
18; CHECK-32-LABEL: f0:
19; CHECK-32:       # %bb.0:
20; CHECK-32-NEXT:    li r4, 125
21; CHECK-32-NEXT:    li r5, -3
22; CHECK-32-NEXT:    cmpwi r3, 0
23; CHECK-32-NEXT:    bc 12, lt, .LBB0_1
24; CHECK-32-NEXT:    b .LBB0_2
25; CHECK-32-NEXT:  .LBB0_1:
26; CHECK-32-NEXT:    addi r4, r5, 0
27; CHECK-32-NEXT:  .LBB0_2:
28; CHECK-32-NEXT:    srawi r3, r3, 31
29; CHECK-32-NEXT:    blr
30  %c = icmp slt i64 %x, 0
31  %r = select i1 %c, i64 -3, i64 125
32  ret i64 %r
33}
34
35define i64 @f1(i64 %x) {
36; CHECK-LE-LABEL: f1:
37; CHECK-LE:       # %bb.0:
38; CHECK-LE-NEXT:    li r4, 512
39; CHECK-LE-NEXT:    cmpdi r3, 0
40; CHECK-LE-NEXT:    li r3, 64
41; CHECK-LE-NEXT:    isellt r3, r3, r4
42; CHECK-LE-NEXT:    blr
43;
44; CHECK-32-LABEL: f1:
45; CHECK-32:       # %bb.0:
46; CHECK-32-NEXT:    li r4, 512
47; CHECK-32-NEXT:    cmpwi r3, 0
48; CHECK-32-NEXT:    li r3, 64
49; CHECK-32-NEXT:    bc 12, lt, .LBB1_1
50; CHECK-32-NEXT:    b .LBB1_2
51; CHECK-32-NEXT:  .LBB1_1:
52; CHECK-32-NEXT:    addi r4, r3, 0
53; CHECK-32-NEXT:  .LBB1_2:
54; CHECK-32-NEXT:    li r3, 0
55; CHECK-32-NEXT:    blr
56  %c = icmp slt i64 %x, 0
57  %r = select i1 %c, i64 64, i64 512
58  ret i64 %r
59}
60
61define i64 @f2(i64 %x) {
62; CHECK-LE-LABEL: f2:
63; CHECK-LE:       # %bb.0:
64; CHECK-LE-NEXT:    li r4, 1024
65; CHECK-LE-NEXT:    cmpdi r3, 0
66; CHECK-LE-NEXT:    iseleq r3, 0, r4
67; CHECK-LE-NEXT:    blr
68;
69; CHECK-32-LABEL: f2:
70; CHECK-32:       # %bb.0:
71; CHECK-32-NEXT:    or. r3, r4, r3
72; CHECK-32-NEXT:    li r3, 1024
73; CHECK-32-NEXT:    bc 12, eq, .LBB2_2
74; CHECK-32-NEXT:  # %bb.1:
75; CHECK-32-NEXT:    ori r4, r3, 0
76; CHECK-32-NEXT:    b .LBB2_3
77; CHECK-32-NEXT:  .LBB2_2:
78; CHECK-32-NEXT:    li r4, 0
79; CHECK-32-NEXT:  .LBB2_3:
80; CHECK-32-NEXT:    li r3, 0
81; CHECK-32-NEXT:    blr
82  %c = icmp eq i64 %x, 0
83  %r = select i1 %c, i64 0, i64 1024
84  ret i64 %r
85}
86
87define i64 @f3(i64 %x, i64 %y) {
88; CHECK-LE-LABEL: f3:
89; CHECK-LE:       # %bb.0:
90; CHECK-LE-NEXT:    cmpldi r3, 0
91; CHECK-LE-NEXT:    iseleq r3, 0, r4
92; CHECK-LE-NEXT:    blr
93;
94; CHECK-32-LABEL: f3:
95; CHECK-32:       # %bb.0:
96; CHECK-32-NEXT:    or. r3, r4, r3
97; CHECK-32-NEXT:    bc 12, eq, .LBB3_2
98; CHECK-32-NEXT:  # %bb.1:
99; CHECK-32-NEXT:    ori r3, r5, 0
100; CHECK-32-NEXT:    ori r4, r6, 0
101; CHECK-32-NEXT:    blr
102; CHECK-32-NEXT:  .LBB3_2:
103; CHECK-32-NEXT:    li r3, 0
104; CHECK-32-NEXT:    li r4, 0
105; CHECK-32-NEXT:    blr
106  %c = icmp eq i64 %x, 0
107  %r = select i1 %c, i64 0, i64 %y
108  ret i64 %r
109}
110
111define i64 @f4(i64 %x) {
112; CHECK-LE-LABEL: f4:
113; CHECK-LE:       # %bb.0:
114; CHECK-LE-NEXT:    sradi r4, r3, 63
115; CHECK-LE-NEXT:    xor r3, r3, r4
116; CHECK-LE-NEXT:    sub r3, r4, r3
117; CHECK-LE-NEXT:    blr
118;
119; CHECK-32-LABEL: f4:
120; CHECK-32:       # %bb.0:
121; CHECK-32-NEXT:    srawi r5, r3, 31
122; CHECK-32-NEXT:    xor r4, r4, r5
123; CHECK-32-NEXT:    xor r3, r3, r5
124; CHECK-32-NEXT:    subc r4, r5, r4
125; CHECK-32-NEXT:    subfe r3, r3, r5
126; CHECK-32-NEXT:    blr
127  %c = icmp sgt i64 %x, 0
128  %x.neg = sub i64 0, %x
129  %r = select i1 %c, i64 %x.neg, i64 %x
130  ret i64 %r
131}
132
133define i64 @f4_sge_0(i64 %x) {
134; CHECK-LE-LABEL: f4_sge_0:
135; CHECK-LE:       # %bb.0:
136; CHECK-LE-NEXT:    neg r4, r3
137; CHECK-LE-NEXT:    cmpdi r3, -1
138; CHECK-LE-NEXT:    iselgt r3, r4, r3
139; CHECK-LE-NEXT:    blr
140;
141; CHECK-32-LABEL: f4_sge_0:
142; CHECK-32:       # %bb.0:
143; CHECK-32-NEXT:    subfic r5, r4, 0
144; CHECK-32-NEXT:    subfze r6, r3
145; CHECK-32-NEXT:    cmpwi r3, -1
146; CHECK-32-NEXT:    bc 12, gt, .LBB5_1
147; CHECK-32-NEXT:    blr
148; CHECK-32-NEXT:  .LBB5_1:
149; CHECK-32-NEXT:    addi r3, r6, 0
150; CHECK-32-NEXT:    addi r4, r5, 0
151; CHECK-32-NEXT:    blr
152  %c = icmp sge i64 %x, 0
153  %x.neg = sub i64 0, %x
154  %r = select i1 %c, i64 %x.neg, i64 %x
155  ret i64 %r
156}
157
158define i64 @f4_slt_0(i64 %x) {
159; CHECK-LE-LABEL: f4_slt_0:
160; CHECK-LE:       # %bb.0:
161; CHECK-LE-NEXT:    sradi r4, r3, 63
162; CHECK-LE-NEXT:    xor r3, r3, r4
163; CHECK-LE-NEXT:    sub r3, r4, r3
164; CHECK-LE-NEXT:    blr
165;
166; CHECK-32-LABEL: f4_slt_0:
167; CHECK-32:       # %bb.0:
168; CHECK-32-NEXT:    srawi r5, r3, 31
169; CHECK-32-NEXT:    xor r4, r4, r5
170; CHECK-32-NEXT:    xor r3, r3, r5
171; CHECK-32-NEXT:    subc r4, r5, r4
172; CHECK-32-NEXT:    subfe r3, r3, r5
173; CHECK-32-NEXT:    blr
174  %c = icmp slt i64 %x, 0
175  %x.neg = sub i64 0, %x
176  %r = select i1 %c, i64 %x, i64 %x.neg
177  ret i64 %r
178}
179
180define i64 @f4_sle_0(i64 %x) {
181; CHECK-LE-LABEL: f4_sle_0:
182; CHECK-LE:       # %bb.0:
183; CHECK-LE-NEXT:    neg r4, r3
184; CHECK-LE-NEXT:    cmpdi r3, 1
185; CHECK-LE-NEXT:    isellt r3, r3, r4
186; CHECK-LE-NEXT:    blr
187;
188; CHECK-32-LABEL: f4_sle_0:
189; CHECK-32:       # %bb.0:
190; CHECK-32-NEXT:    cmplwi r3, 0
191; CHECK-32-NEXT:    cmpwi cr1, r3, 0
192; CHECK-32-NEXT:    crandc 4*cr5+lt, 4*cr1+lt, eq
193; CHECK-32-NEXT:    cmpwi cr1, r4, 0
194; CHECK-32-NEXT:    subfic r5, r4, 0
195; CHECK-32-NEXT:    crand 4*cr5+gt, eq, 4*cr1+eq
196; CHECK-32-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
197; CHECK-32-NEXT:    subfze r6, r3
198; CHECK-32-NEXT:    bclr 12, 4*cr5+lt, 0
199; CHECK-32-NEXT:  # %bb.1:
200; CHECK-32-NEXT:    ori r3, r6, 0
201; CHECK-32-NEXT:    ori r4, r5, 0
202; CHECK-32-NEXT:    blr
203  %c = icmp sle i64 %x, 0
204  %x.neg = sub i64 0, %x
205  %r = select i1 %c, i64 %x, i64 %x.neg
206  ret i64 %r
207}
208
209define i64 @f4_sgt_m1(i64 %x) {
210; CHECK-LE-LABEL: f4_sgt_m1:
211; CHECK-LE:       # %bb.0:
212; CHECK-LE-NEXT:    sradi r4, r3, 63
213; CHECK-LE-NEXT:    xor r3, r3, r4
214; CHECK-LE-NEXT:    sub r3, r4, r3
215; CHECK-LE-NEXT:    blr
216;
217; CHECK-32-LABEL: f4_sgt_m1:
218; CHECK-32:       # %bb.0:
219; CHECK-32-NEXT:    srawi r5, r3, 31
220; CHECK-32-NEXT:    xor r4, r4, r5
221; CHECK-32-NEXT:    xor r3, r3, r5
222; CHECK-32-NEXT:    subc r4, r5, r4
223; CHECK-32-NEXT:    subfe r3, r3, r5
224; CHECK-32-NEXT:    blr
225  %c = icmp sgt i64 %x, -1
226  %x.neg = sub i64 0, %x
227  %r = select i1 %c, i64 %x.neg, i64 %x
228  ret i64 %r
229}
230
231define i64 @f5(i64 %x, i64 %y) {
232; CHECK-LE-LABEL: f5:
233; CHECK-LE:       # %bb.0:
234; CHECK-LE-NEXT:    li r5, 0
235; CHECK-LE-NEXT:    cmpldi r3, 0
236; CHECK-LE-NEXT:    iseleq r3, r4, r5
237; CHECK-LE-NEXT:    blr
238;
239; CHECK-32-LABEL: f5:
240; CHECK-32:       # %bb.0:
241; CHECK-32-NEXT:    li r7, 0
242; CHECK-32-NEXT:    or. r3, r4, r3
243; CHECK-32-NEXT:    bc 12, eq, .LBB9_2
244; CHECK-32-NEXT:  # %bb.1:
245; CHECK-32-NEXT:    ori r3, r7, 0
246; CHECK-32-NEXT:    ori r4, r7, 0
247; CHECK-32-NEXT:    blr
248; CHECK-32-NEXT:  .LBB9_2:
249; CHECK-32-NEXT:    addi r3, r5, 0
250; CHECK-32-NEXT:    addi r4, r6, 0
251; CHECK-32-NEXT:    blr
252  %c = icmp eq i64 %x, 0
253  %r = select i1 %c, i64 %y, i64 0
254  ret i64 %r
255}
256
257define i32 @f5_i32(i32 %x, i32 %y) {
258; CHECK-LE-LABEL: f5_i32:
259; CHECK-LE:       # %bb.0:
260; CHECK-LE-NEXT:    li r5, 0
261; CHECK-LE-NEXT:    cmplwi r3, 0
262; CHECK-LE-NEXT:    iseleq r3, r4, r5
263; CHECK-LE-NEXT:    blr
264;
265; CHECK-32-LABEL: f5_i32:
266; CHECK-32:       # %bb.0:
267; CHECK-32-NEXT:    li r5, 0
268; CHECK-32-NEXT:    cmplwi r3, 0
269; CHECK-32-NEXT:    bc 12, eq, .LBB10_2
270; CHECK-32-NEXT:  # %bb.1:
271; CHECK-32-NEXT:    ori r3, r5, 0
272; CHECK-32-NEXT:    blr
273; CHECK-32-NEXT:  .LBB10_2:
274; CHECK-32-NEXT:    addi r3, r4, 0
275; CHECK-32-NEXT:    blr
276  %c = icmp eq i32 %x, 0
277  %r = select i1 %c, i32 %y, i32 0
278  ret i32 %r
279}
280
281define i64 @f6(i64 %x) {
282; CHECK-LE-LABEL: f6:
283; CHECK-LE:       # %bb.0:
284; CHECK-LE-NEXT:    cntlzd r3, r3
285; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
286; CHECK-LE-NEXT:    blr
287;
288; CHECK-32-LABEL: f6:
289; CHECK-32:       # %bb.0:
290; CHECK-32-NEXT:    or r3, r4, r3
291; CHECK-32-NEXT:    cntlzw r3, r3
292; CHECK-32-NEXT:    rlwinm r4, r3, 27, 31, 31
293; CHECK-32-NEXT:    li r3, 0
294; CHECK-32-NEXT:    blr
295  %c = icmp ne i64 %x, 0
296  %r = select i1 %c, i64 0, i64 1
297  ret i64 %r
298}
299
300define i32 @f6_i32(i32 %x) {
301; CHECK-LE-LABEL: f6_i32:
302; CHECK-LE:       # %bb.0:
303; CHECK-LE-NEXT:    cntlzw r3, r3
304; CHECK-LE-NEXT:    srwi r3, r3, 5
305; CHECK-LE-NEXT:    blr
306;
307; CHECK-32-LABEL: f6_i32:
308; CHECK-32:       # %bb.0:
309; CHECK-32-NEXT:    cntlzw r3, r3
310; CHECK-32-NEXT:    rlwinm r3, r3, 27, 31, 31
311; CHECK-32-NEXT:    blr
312  %c = icmp ne i32 %x, 0
313  %r = select i1 %c, i32 0, i32 1
314  ret i32 %r
315}
316