1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s
3
4; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not.
5; Test each of those patterns with i8/i16/i32/i64.
6; Test each of those with a constant operand and a variable operand.
7; Test each of those with a 128-bit vector type.
8
9define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
10; CHECK-LABEL: unsigned_sat_constant_i8_using_min:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    clrlwi 5, 3, 24
13; CHECK-NEXT:    li 4, -43
14; CHECK-NEXT:    cmplwi 5, 213
15; CHECK-NEXT:    isel 3, 3, 4, 0
16; CHECK-NEXT:    addi 3, 3, 42
17; CHECK-NEXT:    blr
18  %c = icmp ult i8 %x, -43
19  %s = select i1 %c, i8 %x, i8 -43
20  %r = add i8 %s, 42
21  ret i8 %r
22}
23
24define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
25; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    clrlwi 3, 3, 24
28; CHECK-NEXT:    addi 3, 3, 42
29; CHECK-NEXT:    andi. 4, 3, 256
30; CHECK-NEXT:    li 4, -1
31; CHECK-NEXT:    isel 3, 3, 4, 2
32; CHECK-NEXT:    blr
33  %a = add i8 %x, 42
34  %c = icmp ugt i8 %x, %a
35  %r = select i1 %c, i8 -1, i8 %a
36  ret i8 %r
37}
38
39define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) {
40; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_notval:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    clrlwi 5, 3, 24
43; CHECK-NEXT:    li 4, -1
44; CHECK-NEXT:    addi 3, 3, 42
45; CHECK-NEXT:    cmplwi 5, 213
46; CHECK-NEXT:    isel 3, 4, 3, 1
47; CHECK-NEXT:    blr
48  %a = add i8 %x, 42
49  %c = icmp ugt i8 %x, -43
50  %r = select i1 %c, i8 -1, i8 %a
51  ret i8 %r
52}
53
54define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
55; CHECK-LABEL: unsigned_sat_constant_i16_using_min:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    clrlwi 5, 3, 16
58; CHECK-NEXT:    li 4, -43
59; CHECK-NEXT:    cmplwi 5, 65493
60; CHECK-NEXT:    isel 3, 3, 4, 0
61; CHECK-NEXT:    addi 3, 3, 42
62; CHECK-NEXT:    blr
63  %c = icmp ult i16 %x, -43
64  %s = select i1 %c, i16 %x, i16 -43
65  %r = add i16 %s, 42
66  ret i16 %r
67}
68
69define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
70; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    clrlwi 3, 3, 16
73; CHECK-NEXT:    addi 3, 3, 42
74; CHECK-NEXT:    andis. 4, 3, 1
75; CHECK-NEXT:    li 4, -1
76; CHECK-NEXT:    isel 3, 3, 4, 2
77; CHECK-NEXT:    blr
78  %a = add i16 %x, 42
79  %c = icmp ugt i16 %x, %a
80  %r = select i1 %c, i16 -1, i16 %a
81  ret i16 %r
82}
83
84define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) {
85; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval:
86; CHECK:       # %bb.0:
87; CHECK-NEXT:    clrlwi 5, 3, 16
88; CHECK-NEXT:    li 4, -1
89; CHECK-NEXT:    addi 3, 3, 42
90; CHECK-NEXT:    cmplwi 5, 65493
91; CHECK-NEXT:    isel 3, 4, 3, 1
92; CHECK-NEXT:    blr
93  %a = add i16 %x, 42
94  %c = icmp ugt i16 %x, -43
95  %r = select i1 %c, i16 -1, i16 %a
96  ret i16 %r
97}
98
99define i32 @unsigned_sat_constant_i32_using_min(i32 %x) {
100; CHECK-LABEL: unsigned_sat_constant_i32_using_min:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    li 4, -43
103; CHECK-NEXT:    cmplw 3, 4
104; CHECK-NEXT:    isel 3, 3, 4, 0
105; CHECK-NEXT:    addi 3, 3, 42
106; CHECK-NEXT:    blr
107  %c = icmp ult i32 %x, -43
108  %s = select i1 %c, i32 %x, i32 -43
109  %r = add i32 %s, 42
110  ret i32 %r
111}
112
113define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {
114; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    addi 5, 3, 42
117; CHECK-NEXT:    li 4, -1
118; CHECK-NEXT:    cmplw 5, 3
119; CHECK-NEXT:    isel 3, 4, 5, 0
120; CHECK-NEXT:    blr
121  %a = add i32 %x, 42
122  %c = icmp ugt i32 %x, %a
123  %r = select i1 %c, i32 -1, i32 %a
124  ret i32 %r
125}
126
127define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {
128; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    li 4, -43
131; CHECK-NEXT:    addi 5, 3, 42
132; CHECK-NEXT:    cmplw 3, 4
133; CHECK-NEXT:    li 3, -1
134; CHECK-NEXT:    isel 3, 3, 5, 1
135; CHECK-NEXT:    blr
136  %a = add i32 %x, 42
137  %c = icmp ugt i32 %x, -43
138  %r = select i1 %c, i32 -1, i32 %a
139  ret i32 %r
140}
141
142define i64 @unsigned_sat_constant_i64_using_min(i64 %x) {
143; CHECK-LABEL: unsigned_sat_constant_i64_using_min:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    li 4, -43
146; CHECK-NEXT:    cmpld 3, 4
147; CHECK-NEXT:    isel 3, 3, 4, 0
148; CHECK-NEXT:    addi 3, 3, 42
149; CHECK-NEXT:    blr
150  %c = icmp ult i64 %x, -43
151  %s = select i1 %c, i64 %x, i64 -43
152  %r = add i64 %s, 42
153  ret i64 %r
154}
155
156define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) {
157; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_sum:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    addi 5, 3, 42
160; CHECK-NEXT:    li 4, -1
161; CHECK-NEXT:    cmpld 5, 3
162; CHECK-NEXT:    isel 3, 4, 5, 0
163; CHECK-NEXT:    blr
164  %a = add i64 %x, 42
165  %c = icmp ugt i64 %x, %a
166  %r = select i1 %c, i64 -1, i64 %a
167  ret i64 %r
168}
169
170define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
171; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    li 4, -43
174; CHECK-NEXT:    addi 5, 3, 42
175; CHECK-NEXT:    cmpld 3, 4
176; CHECK-NEXT:    li 3, -1
177; CHECK-NEXT:    isel 3, 3, 5, 1
178; CHECK-NEXT:    blr
179  %a = add i64 %x, 42
180  %c = icmp ugt i64 %x, -43
181  %r = select i1 %c, i64 -1, i64 %a
182  ret i64 %r
183}
184
185define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
186; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    nor 5, 4, 4
189; CHECK-NEXT:    clrlwi 6, 3, 24
190; CHECK-NEXT:    clrlwi 7, 5, 24
191; CHECK-NEXT:    cmplw 6, 7
192; CHECK-NEXT:    isel 3, 3, 5, 0
193; CHECK-NEXT:    add 3, 3, 4
194; CHECK-NEXT:    blr
195  %noty = xor i8 %y, -1
196  %c = icmp ult i8 %x, %noty
197  %s = select i1 %c, i8 %x, i8 %noty
198  %r = add i8 %s, %y
199  ret i8 %r
200}
201
202define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
203; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
204; CHECK:       # %bb.0:
205; CHECK-NEXT:    clrlwi 4, 4, 24
206; CHECK-NEXT:    clrlwi 3, 3, 24
207; CHECK-NEXT:    add 3, 3, 4
208; CHECK-NEXT:    andi. 4, 3, 256
209; CHECK-NEXT:    li 4, -1
210; CHECK-NEXT:    isel 3, 3, 4, 2
211; CHECK-NEXT:    blr
212  %a = add i8 %x, %y
213  %c = icmp ugt i8 %x, %a
214  %r = select i1 %c, i8 -1, i8 %a
215  ret i8 %r
216}
217
218define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
219; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    nor 6, 4, 4
222; CHECK-NEXT:    clrlwi 7, 3, 24
223; CHECK-NEXT:    li 5, -1
224; CHECK-NEXT:    add 3, 3, 4
225; CHECK-NEXT:    clrlwi 6, 6, 24
226; CHECK-NEXT:    cmplw 7, 6
227; CHECK-NEXT:    isel 3, 5, 3, 1
228; CHECK-NEXT:    blr
229  %noty = xor i8 %y, -1
230  %a = add i8 %x, %y
231  %c = icmp ugt i8 %x, %noty
232  %r = select i1 %c, i8 -1, i8 %a
233  ret i8 %r
234}
235
236define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
237; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    nor 5, 4, 4
240; CHECK-NEXT:    clrlwi 6, 3, 16
241; CHECK-NEXT:    clrlwi 7, 5, 16
242; CHECK-NEXT:    cmplw 6, 7
243; CHECK-NEXT:    isel 3, 3, 5, 0
244; CHECK-NEXT:    add 3, 3, 4
245; CHECK-NEXT:    blr
246  %noty = xor i16 %y, -1
247  %c = icmp ult i16 %x, %noty
248  %s = select i1 %c, i16 %x, i16 %noty
249  %r = add i16 %s, %y
250  ret i16 %r
251}
252
253define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
254; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    clrlwi 4, 4, 16
257; CHECK-NEXT:    clrlwi 3, 3, 16
258; CHECK-NEXT:    add 3, 3, 4
259; CHECK-NEXT:    andis. 4, 3, 1
260; CHECK-NEXT:    li 4, -1
261; CHECK-NEXT:    isel 3, 3, 4, 2
262; CHECK-NEXT:    blr
263  %a = add i16 %x, %y
264  %c = icmp ugt i16 %x, %a
265  %r = select i1 %c, i16 -1, i16 %a
266  ret i16 %r
267}
268
269define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
270; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    nor 6, 4, 4
273; CHECK-NEXT:    clrlwi 7, 3, 16
274; CHECK-NEXT:    li 5, -1
275; CHECK-NEXT:    add 3, 3, 4
276; CHECK-NEXT:    clrlwi 6, 6, 16
277; CHECK-NEXT:    cmplw 7, 6
278; CHECK-NEXT:    isel 3, 5, 3, 1
279; CHECK-NEXT:    blr
280  %noty = xor i16 %y, -1
281  %a = add i16 %x, %y
282  %c = icmp ugt i16 %x, %noty
283  %r = select i1 %c, i16 -1, i16 %a
284  ret i16 %r
285}
286
287define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) {
288; CHECK-LABEL: unsigned_sat_variable_i32_using_min:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    nor 5, 4, 4
291; CHECK-NEXT:    cmplw 3, 5
292; CHECK-NEXT:    isel 3, 3, 5, 0
293; CHECK-NEXT:    add 3, 3, 4
294; CHECK-NEXT:    blr
295  %noty = xor i32 %y, -1
296  %c = icmp ult i32 %x, %noty
297  %s = select i1 %c, i32 %x, i32 %noty
298  %r = add i32 %s, %y
299  ret i32 %r
300}
301
302define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
303; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_sum:
304; CHECK:       # %bb.0:
305; CHECK-NEXT:    add 4, 3, 4
306; CHECK-NEXT:    li 5, -1
307; CHECK-NEXT:    cmplw 4, 3
308; CHECK-NEXT:    isel 3, 5, 4, 0
309; CHECK-NEXT:    blr
310  %a = add i32 %x, %y
311  %c = icmp ugt i32 %x, %a
312  %r = select i1 %c, i32 -1, i32 %a
313  ret i32 %r
314}
315
316define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {
317; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:
318; CHECK:       # %bb.0:
319; CHECK-NEXT:    nor 6, 4, 4
320; CHECK-NEXT:    li 5, -1
321; CHECK-NEXT:    cmplw 3, 6
322; CHECK-NEXT:    add 3, 3, 4
323; CHECK-NEXT:    isel 3, 5, 3, 1
324; CHECK-NEXT:    blr
325  %noty = xor i32 %y, -1
326  %a = add i32 %x, %y
327  %c = icmp ugt i32 %x, %noty
328  %r = select i1 %c, i32 -1, i32 %a
329  ret i32 %r
330}
331
332define i64 @unsigned_sat_variable_i64_using_min(i64 %x, i64 %y) {
333; CHECK-LABEL: unsigned_sat_variable_i64_using_min:
334; CHECK:       # %bb.0:
335; CHECK-NEXT:    not 5, 4
336; CHECK-NEXT:    cmpld 3, 5
337; CHECK-NEXT:    isel 3, 3, 5, 0
338; CHECK-NEXT:    add 3, 3, 4
339; CHECK-NEXT:    blr
340  %noty = xor i64 %y, -1
341  %c = icmp ult i64 %x, %noty
342  %s = select i1 %c, i64 %x, i64 %noty
343  %r = add i64 %s, %y
344  ret i64 %r
345}
346
347define i64 @unsigned_sat_variable_i64_using_cmp_sum(i64 %x, i64 %y) {
348; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_sum:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    add 4, 3, 4
351; CHECK-NEXT:    li 5, -1
352; CHECK-NEXT:    cmpld 4, 3
353; CHECK-NEXT:    isel 3, 5, 4, 0
354; CHECK-NEXT:    blr
355  %a = add i64 %x, %y
356  %c = icmp ugt i64 %x, %a
357  %r = select i1 %c, i64 -1, i64 %a
358  ret i64 %r
359}
360
361define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {
362; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_notval:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    not 6, 4
365; CHECK-NEXT:    li 5, -1
366; CHECK-NEXT:    cmpld 3, 6
367; CHECK-NEXT:    add 3, 3, 4
368; CHECK-NEXT:    isel 3, 5, 3, 1
369; CHECK-NEXT:    blr
370  %noty = xor i64 %y, -1
371  %a = add i64 %x, %y
372  %c = icmp ugt i64 %x, %noty
373  %r = select i1 %c, i64 -1, i64 %a
374  ret i64 %r
375}
376
377define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
378; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min:
379; CHECK:       # %bb.0:
380; CHECK-NEXT:    addis 3, 2, .LCPI24_0@toc@ha
381; CHECK-NEXT:    addi 3, 3, .LCPI24_0@toc@l
382; CHECK-NEXT:    lvx 3, 0, 3
383; CHECK-NEXT:    addis 3, 2, .LCPI24_1@toc@ha
384; CHECK-NEXT:    addi 3, 3, .LCPI24_1@toc@l
385; CHECK-NEXT:    vminub 2, 2, 3
386; CHECK-NEXT:    lvx 3, 0, 3
387; CHECK-NEXT:    vaddubm 2, 2, 3
388; CHECK-NEXT:    blr
389  %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
390  %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
391  %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
392  ret <16 x i8> %r
393}
394
395define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
396; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
399; CHECK-NEXT:    xxleqv 0, 0, 0
400; CHECK-NEXT:    addi 3, 3, .LCPI25_0@toc@l
401; CHECK-NEXT:    lvx 3, 0, 3
402; CHECK-NEXT:    vaddubm 3, 2, 3
403; CHECK-NEXT:    vcmpgtub 2, 2, 3
404; CHECK-NEXT:    xxsel 34, 35, 0, 34
405; CHECK-NEXT:    blr
406  %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
407  %c = icmp ugt <16 x i8> %x, %a
408  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
409  ret <16 x i8> %r
410}
411
412define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
413; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    addis 3, 2, .LCPI26_1@toc@ha
416; CHECK-NEXT:    xxleqv 0, 0, 0
417; CHECK-NEXT:    addi 3, 3, .LCPI26_1@toc@l
418; CHECK-NEXT:    lvx 3, 0, 3
419; CHECK-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
420; CHECK-NEXT:    addi 3, 3, .LCPI26_0@toc@l
421; CHECK-NEXT:    vcmpgtub 3, 2, 3
422; CHECK-NEXT:    lvx 4, 0, 3
423; CHECK-NEXT:    vaddubm 2, 2, 4
424; CHECK-NEXT:    xxsel 34, 34, 0, 35
425; CHECK-NEXT:    blr
426  %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
427  %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
428  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
429  ret <16 x i8> %r
430}
431
432define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
433; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min:
434; CHECK:       # %bb.0:
435; CHECK-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
436; CHECK-NEXT:    addi 3, 3, .LCPI27_0@toc@l
437; CHECK-NEXT:    lvx 3, 0, 3
438; CHECK-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
439; CHECK-NEXT:    addi 3, 3, .LCPI27_1@toc@l
440; CHECK-NEXT:    vminuh 2, 2, 3
441; CHECK-NEXT:    lvx 3, 0, 3
442; CHECK-NEXT:    vadduhm 2, 2, 3
443; CHECK-NEXT:    blr
444  %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
445  %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
446  %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
447  ret <8 x i16> %r
448}
449
450define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
451; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
452; CHECK:       # %bb.0:
453; CHECK-NEXT:    addis 3, 2, .LCPI28_0@toc@ha
454; CHECK-NEXT:    xxleqv 0, 0, 0
455; CHECK-NEXT:    addi 3, 3, .LCPI28_0@toc@l
456; CHECK-NEXT:    lvx 3, 0, 3
457; CHECK-NEXT:    vadduhm 3, 2, 3
458; CHECK-NEXT:    vcmpgtuh 2, 2, 3
459; CHECK-NEXT:    xxsel 34, 35, 0, 34
460; CHECK-NEXT:    blr
461  %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
462  %c = icmp ugt <8 x i16> %x, %a
463  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
464  ret <8 x i16> %r
465}
466
467define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
468; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    addis 3, 2, .LCPI29_1@toc@ha
471; CHECK-NEXT:    xxleqv 0, 0, 0
472; CHECK-NEXT:    addi 3, 3, .LCPI29_1@toc@l
473; CHECK-NEXT:    lvx 3, 0, 3
474; CHECK-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
475; CHECK-NEXT:    addi 3, 3, .LCPI29_0@toc@l
476; CHECK-NEXT:    vcmpgtuh 3, 2, 3
477; CHECK-NEXT:    lvx 4, 0, 3
478; CHECK-NEXT:    vadduhm 2, 2, 4
479; CHECK-NEXT:    xxsel 34, 34, 0, 35
480; CHECK-NEXT:    blr
481  %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
482  %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
483  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
484  ret <8 x i16> %r
485}
486
487define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
488; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    addis 3, 2, .LCPI30_0@toc@ha
491; CHECK-NEXT:    addi 3, 3, .LCPI30_0@toc@l
492; CHECK-NEXT:    lvx 3, 0, 3
493; CHECK-NEXT:    addis 3, 2, .LCPI30_1@toc@ha
494; CHECK-NEXT:    addi 3, 3, .LCPI30_1@toc@l
495; CHECK-NEXT:    vminuw 2, 2, 3
496; CHECK-NEXT:    lvx 3, 0, 3
497; CHECK-NEXT:    vadduwm 2, 2, 3
498; CHECK-NEXT:    blr
499  %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
500  %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43>
501  %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>
502  ret <4 x i32> %r
503}
504
505define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
506; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
509; CHECK-NEXT:    xxleqv 0, 0, 0
510; CHECK-NEXT:    addi 3, 3, .LCPI31_0@toc@l
511; CHECK-NEXT:    lvx 3, 0, 3
512; CHECK-NEXT:    vadduwm 3, 2, 3
513; CHECK-NEXT:    vcmpgtuw 2, 2, 3
514; CHECK-NEXT:    xxsel 34, 35, 0, 34
515; CHECK-NEXT:    blr
516  %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
517  %c = icmp ugt <4 x i32> %x, %a
518  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
519  ret <4 x i32> %r
520}
521
522define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
523; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    addis 3, 2, .LCPI32_1@toc@ha
526; CHECK-NEXT:    xxleqv 0, 0, 0
527; CHECK-NEXT:    addi 3, 3, .LCPI32_1@toc@l
528; CHECK-NEXT:    lvx 3, 0, 3
529; CHECK-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
530; CHECK-NEXT:    addi 3, 3, .LCPI32_0@toc@l
531; CHECK-NEXT:    vcmpgtuw 3, 2, 3
532; CHECK-NEXT:    lvx 4, 0, 3
533; CHECK-NEXT:    vadduwm 2, 2, 4
534; CHECK-NEXT:    xxsel 34, 34, 0, 35
535; CHECK-NEXT:    blr
536  %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
537  %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
538  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
539  ret <4 x i32> %r
540}
541
542define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
543; CHECK-LABEL: unsigned_sat_constant_v2i64_using_min:
544; CHECK:       # %bb.0:
545; CHECK-NEXT:    addis 3, 2, .LCPI33_0@toc@ha
546; CHECK-NEXT:    addi 3, 3, .LCPI33_0@toc@l
547; CHECK-NEXT:    lxvd2x 0, 0, 3
548; CHECK-NEXT:    addis 3, 2, .LCPI33_1@toc@ha
549; CHECK-NEXT:    addi 3, 3, .LCPI33_1@toc@l
550; CHECK-NEXT:    xxswapd 35, 0
551; CHECK-NEXT:    lxvd2x 0, 0, 3
552; CHECK-NEXT:    vminud 2, 2, 3
553; CHECK-NEXT:    xxswapd 35, 0
554; CHECK-NEXT:    vaddudm 2, 2, 3
555; CHECK-NEXT:    blr
556  %c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>
557  %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>
558  %r = add <2 x i64> %s, <i64 42, i64 42>
559  ret <2 x i64> %r
560}
561
562define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
563; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
564; CHECK:       # %bb.0:
565; CHECK-NEXT:    addis 3, 2, .LCPI34_0@toc@ha
566; CHECK-NEXT:    addi 3, 3, .LCPI34_0@toc@l
567; CHECK-NEXT:    lxvd2x 0, 0, 3
568; CHECK-NEXT:    xxswapd 35, 0
569; CHECK-NEXT:    xxleqv 0, 0, 0
570; CHECK-NEXT:    vaddudm 3, 2, 3
571; CHECK-NEXT:    vcmpgtud 2, 2, 3
572; CHECK-NEXT:    xxsel 34, 35, 0, 34
573; CHECK-NEXT:    blr
574  %a = add <2 x i64> %x, <i64 42, i64 42>
575  %c = icmp ugt <2 x i64> %x, %a
576  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
577  ret <2 x i64> %r
578}
579
580define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
581; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
582; CHECK:       # %bb.0:
583; CHECK-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
584; CHECK-NEXT:    addi 3, 3, .LCPI35_1@toc@l
585; CHECK-NEXT:    lxvd2x 0, 0, 3
586; CHECK-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
587; CHECK-NEXT:    addi 3, 3, .LCPI35_0@toc@l
588; CHECK-NEXT:    lxvd2x 1, 0, 3
589; CHECK-NEXT:    xxswapd 35, 0
590; CHECK-NEXT:    xxleqv 0, 0, 0
591; CHECK-NEXT:    xxswapd 36, 1
592; CHECK-NEXT:    vcmpgtud 3, 2, 3
593; CHECK-NEXT:    vaddudm 2, 2, 4
594; CHECK-NEXT:    xxsel 34, 34, 0, 35
595; CHECK-NEXT:    blr
596  %a = add <2 x i64> %x, <i64 42, i64 42>
597  %c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
598  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
599  ret <2 x i64> %r
600}
601
602define <16 x i8> @unsigned_sat_variable_v16i8_using_min(<16 x i8> %x, <16 x i8> %y) {
603; CHECK-LABEL: unsigned_sat_variable_v16i8_using_min:
604; CHECK:       # %bb.0:
605; CHECK-NEXT:    xxlnor 36, 35, 35
606; CHECK-NEXT:    vminub 2, 2, 4
607; CHECK-NEXT:    vaddubm 2, 2, 3
608; CHECK-NEXT:    blr
609  %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
610  %c = icmp ult <16 x i8> %x, %noty
611  %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %noty
612  %r = add <16 x i8> %s, %y
613  ret <16 x i8> %r
614}
615
616define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x i8> %y) {
617; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum:
618; CHECK:       # %bb.0:
619; CHECK-NEXT:    vaddubm 3, 2, 3
620; CHECK-NEXT:    xxleqv 0, 0, 0
621; CHECK-NEXT:    vcmpgtub 2, 2, 3
622; CHECK-NEXT:    xxsel 34, 35, 0, 34
623; CHECK-NEXT:    blr
624  %a = add <16 x i8> %x, %y
625  %c = icmp ugt <16 x i8> %x, %a
626  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
627  ret <16 x i8> %r
628}
629
630define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16 x i8> %y) {
631; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval:
632; CHECK:       # %bb.0:
633; CHECK-NEXT:    xxlnor 36, 35, 35
634; CHECK-NEXT:    xxleqv 0, 0, 0
635; CHECK-NEXT:    vcmpgtub 4, 2, 4
636; CHECK-NEXT:    vaddubm 2, 2, 3
637; CHECK-NEXT:    xxsel 34, 34, 0, 36
638; CHECK-NEXT:    blr
639  %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
640  %a = add <16 x i8> %x, %y
641  %c = icmp ugt <16 x i8> %x, %noty
642  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
643  ret <16 x i8> %r
644}
645
646define <8 x i16> @unsigned_sat_variable_v8i16_using_min(<8 x i16> %x, <8 x i16> %y) {
647; CHECK-LABEL: unsigned_sat_variable_v8i16_using_min:
648; CHECK:       # %bb.0:
649; CHECK-NEXT:    xxlnor 36, 35, 35
650; CHECK-NEXT:    vminuh 2, 2, 4
651; CHECK-NEXT:    vadduhm 2, 2, 3
652; CHECK-NEXT:    blr
653  %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
654  %c = icmp ult <8 x i16> %x, %noty
655  %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %noty
656  %r = add <8 x i16> %s, %y
657  ret <8 x i16> %r
658}
659
660define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i16> %y) {
661; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum:
662; CHECK:       # %bb.0:
663; CHECK-NEXT:    vadduhm 3, 2, 3
664; CHECK-NEXT:    xxleqv 0, 0, 0
665; CHECK-NEXT:    vcmpgtuh 2, 2, 3
666; CHECK-NEXT:    xxsel 34, 35, 0, 34
667; CHECK-NEXT:    blr
668  %a = add <8 x i16> %x, %y
669  %c = icmp ugt <8 x i16> %x, %a
670  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
671  ret <8 x i16> %r
672}
673
674define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8 x i16> %y) {
675; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval:
676; CHECK:       # %bb.0:
677; CHECK-NEXT:    xxlnor 36, 35, 35
678; CHECK-NEXT:    xxleqv 0, 0, 0
679; CHECK-NEXT:    vcmpgtuh 4, 2, 4
680; CHECK-NEXT:    vadduhm 2, 2, 3
681; CHECK-NEXT:    xxsel 34, 34, 0, 36
682; CHECK-NEXT:    blr
683  %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
684  %a = add <8 x i16> %x, %y
685  %c = icmp ugt <8 x i16> %x, %noty
686  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
687  ret <8 x i16> %r
688}
689
690define <4 x i32> @unsigned_sat_variable_v4i32_using_min(<4 x i32> %x, <4 x i32> %y) {
691; CHECK-LABEL: unsigned_sat_variable_v4i32_using_min:
692; CHECK:       # %bb.0:
693; CHECK-NEXT:    xxlnor 36, 35, 35
694; CHECK-NEXT:    vminuw 2, 2, 4
695; CHECK-NEXT:    vadduwm 2, 2, 3
696; CHECK-NEXT:    blr
697  %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
698  %c = icmp ult <4 x i32> %x, %noty
699  %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %noty
700  %r = add <4 x i32> %s, %y
701  ret <4 x i32> %r
702}
703
704define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i32> %y) {
705; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum:
706; CHECK:       # %bb.0:
707; CHECK-NEXT:    vadduwm 3, 2, 3
708; CHECK-NEXT:    xxleqv 0, 0, 0
709; CHECK-NEXT:    vcmpgtuw 2, 2, 3
710; CHECK-NEXT:    xxsel 34, 35, 0, 34
711; CHECK-NEXT:    blr
712  %a = add <4 x i32> %x, %y
713  %c = icmp ugt <4 x i32> %x, %a
714  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
715  ret <4 x i32> %r
716}
717
718define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4 x i32> %y) {
719; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval:
720; CHECK:       # %bb.0:
721; CHECK-NEXT:    xxlnor 36, 35, 35
722; CHECK-NEXT:    xxleqv 0, 0, 0
723; CHECK-NEXT:    vcmpgtuw 4, 2, 4
724; CHECK-NEXT:    vadduwm 2, 2, 3
725; CHECK-NEXT:    xxsel 34, 34, 0, 36
726; CHECK-NEXT:    blr
727  %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
728  %a = add <4 x i32> %x, %y
729  %c = icmp ugt <4 x i32> %x, %noty
730  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
731  ret <4 x i32> %r
732}
733
734define <2 x i64> @unsigned_sat_variable_v2i64_using_min(<2 x i64> %x, <2 x i64> %y) {
735; CHECK-LABEL: unsigned_sat_variable_v2i64_using_min:
736; CHECK:       # %bb.0:
737; CHECK-NEXT:    xxlnor 36, 35, 35
738; CHECK-NEXT:    vminud 2, 2, 4
739; CHECK-NEXT:    vaddudm 2, 2, 3
740; CHECK-NEXT:    blr
741  %noty = xor <2 x i64> %y, <i64 -1, i64 -1>
742  %c = icmp ult <2 x i64> %x, %noty
743  %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %noty
744  %r = add <2 x i64> %s, %y
745  ret <2 x i64> %r
746}
747
748define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i64> %y) {
749; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:
750; CHECK:       # %bb.0:
751; CHECK-NEXT:    vaddudm 3, 2, 3
752; CHECK-NEXT:    xxleqv 0, 0, 0
753; CHECK-NEXT:    vcmpgtud 2, 2, 3
754; CHECK-NEXT:    xxsel 34, 35, 0, 34
755; CHECK-NEXT:    blr
756  %a = add <2 x i64> %x, %y
757  %c = icmp ugt <2 x i64> %x, %a
758  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
759  ret <2 x i64> %r
760}
761
762define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2 x i64> %y) {
763; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval:
764; CHECK:       # %bb.0:
765; CHECK-NEXT:    xxlnor 36, 35, 35
766; CHECK-NEXT:    xxleqv 0, 0, 0
767; CHECK-NEXT:    vcmpgtud 4, 2, 4
768; CHECK-NEXT:    vaddudm 2, 2, 3
769; CHECK-NEXT:    xxsel 34, 34, 0, 36
770; CHECK-NEXT:    blr
771  %noty = xor <2 x i64> %y, <i64 -1, i64 -1>
772  %a = add <2 x i64> %x, %y
773  %c = icmp ugt <2 x i64> %x, %noty
774  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
775  ret <2 x i64> %r
776}
777
778