1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s
3
4; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not.
5; Test each of those patterns with i8/i16/i32/i64.
6; Test each of those with a constant operand and a variable operand.
7; Test each of those with a 128-bit vector type.
8
9define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
10; CHECK-LABEL: unsigned_sat_constant_i8_using_min:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    clrlwi 5, 3, 24
13; CHECK-NEXT:    li 4, -43
14; CHECK-NEXT:    cmplwi 5, 213
15; CHECK-NEXT:    isellt 3, 3, 4
16; CHECK-NEXT:    addi 3, 3, 42
17; CHECK-NEXT:    blr
18  %c = icmp ult i8 %x, -43
19  %s = select i1 %c, i8 %x, i8 -43
20  %r = add i8 %s, 42
21  ret i8 %r
22}
23
24define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
25; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    clrlwi 3, 3, 24
28; CHECK-NEXT:    addi 3, 3, 42
29; CHECK-NEXT:    andi. 4, 3, 256
30; CHECK-NEXT:    li 4, -1
31; CHECK-NEXT:    iseleq 3, 3, 4
32; CHECK-NEXT:    blr
33  %a = add i8 %x, 42
34  %c = icmp ugt i8 %x, %a
35  %r = select i1 %c, i8 -1, i8 %a
36  ret i8 %r
37}
38
39define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) {
40; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_notval:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    clrlwi 5, 3, 24
43; CHECK-NEXT:    li 4, -1
44; CHECK-NEXT:    addi 3, 3, 42
45; CHECK-NEXT:    cmplwi 5, 213
46; CHECK-NEXT:    iselgt 3, 4, 3
47; CHECK-NEXT:    blr
48  %a = add i8 %x, 42
49  %c = icmp ugt i8 %x, -43
50  %r = select i1 %c, i8 -1, i8 %a
51  ret i8 %r
52}
53
54define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
55; CHECK-LABEL: unsigned_sat_constant_i16_using_min:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    clrlwi 5, 3, 16
58; CHECK-NEXT:    li 4, -43
59; CHECK-NEXT:    cmplwi 5, 65493
60; CHECK-NEXT:    isellt 3, 3, 4
61; CHECK-NEXT:    addi 3, 3, 42
62; CHECK-NEXT:    blr
63  %c = icmp ult i16 %x, -43
64  %s = select i1 %c, i16 %x, i16 -43
65  %r = add i16 %s, 42
66  ret i16 %r
67}
68
69define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
70; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    clrlwi 3, 3, 16
73; CHECK-NEXT:    addi 3, 3, 42
74; CHECK-NEXT:    andis. 4, 3, 1
75; CHECK-NEXT:    li 4, -1
76; CHECK-NEXT:    iseleq 3, 3, 4
77; CHECK-NEXT:    blr
78  %a = add i16 %x, 42
79  %c = icmp ugt i16 %x, %a
80  %r = select i1 %c, i16 -1, i16 %a
81  ret i16 %r
82}
83
84define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) {
85; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval:
86; CHECK:       # %bb.0:
87; CHECK-NEXT:    clrlwi 5, 3, 16
88; CHECK-NEXT:    li 4, -1
89; CHECK-NEXT:    addi 3, 3, 42
90; CHECK-NEXT:    cmplwi 5, 65493
91; CHECK-NEXT:    iselgt 3, 4, 3
92; CHECK-NEXT:    blr
93  %a = add i16 %x, 42
94  %c = icmp ugt i16 %x, -43
95  %r = select i1 %c, i16 -1, i16 %a
96  ret i16 %r
97}
98
99define i32 @unsigned_sat_constant_i32_using_min(i32 %x) {
100; CHECK-LABEL: unsigned_sat_constant_i32_using_min:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    li 4, -43
103; CHECK-NEXT:    cmplw 3, 4
104; CHECK-NEXT:    isellt 3, 3, 4
105; CHECK-NEXT:    addi 3, 3, 42
106; CHECK-NEXT:    blr
107  %c = icmp ult i32 %x, -43
108  %s = select i1 %c, i32 %x, i32 -43
109  %r = add i32 %s, 42
110  ret i32 %r
111}
112
113define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {
114; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    addi 5, 3, 42
117; CHECK-NEXT:    li 4, -1
118; CHECK-NEXT:    cmplw 5, 3
119; CHECK-NEXT:    isellt 3, 4, 5
120; CHECK-NEXT:    blr
121  %a = add i32 %x, 42
122  %c = icmp ugt i32 %x, %a
123  %r = select i1 %c, i32 -1, i32 %a
124  ret i32 %r
125}
126
127define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {
128; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    li 4, -43
131; CHECK-NEXT:    addi 5, 3, 42
132; CHECK-NEXT:    cmplw 3, 4
133; CHECK-NEXT:    li 3, -1
134; CHECK-NEXT:    iselgt 3, 3, 5
135; CHECK-NEXT:    blr
136  %a = add i32 %x, 42
137  %c = icmp ugt i32 %x, -43
138  %r = select i1 %c, i32 -1, i32 %a
139  ret i32 %r
140}
141
142define i64 @unsigned_sat_constant_i64_using_min(i64 %x) {
143; CHECK-LABEL: unsigned_sat_constant_i64_using_min:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    li 4, -43
146; CHECK-NEXT:    cmpld 3, 4
147; CHECK-NEXT:    isellt 3, 3, 4
148; CHECK-NEXT:    addi 3, 3, 42
149; CHECK-NEXT:    blr
150  %c = icmp ult i64 %x, -43
151  %s = select i1 %c, i64 %x, i64 -43
152  %r = add i64 %s, 42
153  ret i64 %r
154}
155
156define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) {
157; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_sum:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    addi 5, 3, 42
160; CHECK-NEXT:    li 4, -1
161; CHECK-NEXT:    cmpld 5, 3
162; CHECK-NEXT:    isellt 3, 4, 5
163; CHECK-NEXT:    blr
164  %a = add i64 %x, 42
165  %c = icmp ugt i64 %x, %a
166  %r = select i1 %c, i64 -1, i64 %a
167  ret i64 %r
168}
169
170define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
171; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    li 4, -43
174; CHECK-NEXT:    addi 5, 3, 42
175; CHECK-NEXT:    cmpld 3, 4
176; CHECK-NEXT:    li 3, -1
177; CHECK-NEXT:    iselgt 3, 3, 5
178; CHECK-NEXT:    blr
179  %a = add i64 %x, 42
180  %c = icmp ugt i64 %x, -43
181  %r = select i1 %c, i64 -1, i64 %a
182  ret i64 %r
183}
184
185define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
186; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    not 5, 4
189; CHECK-NEXT:    clrlwi 6, 3, 24
190; CHECK-NEXT:    clrlwi 7, 5, 24
191; CHECK-NEXT:    cmplw 6, 7
192; CHECK-NEXT:    isellt 3, 3, 5
193; CHECK-NEXT:    add 3, 3, 4
194; CHECK-NEXT:    blr
195  %noty = xor i8 %y, -1
196  %c = icmp ult i8 %x, %noty
197  %s = select i1 %c, i8 %x, i8 %noty
198  %r = add i8 %s, %y
199  ret i8 %r
200}
201
202define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
203; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
204; CHECK:       # %bb.0:
205; CHECK-NEXT:    clrlwi 4, 4, 24
206; CHECK-NEXT:    clrlwi 3, 3, 24
207; CHECK-NEXT:    add 3, 3, 4
208; CHECK-NEXT:    andi. 4, 3, 256
209; CHECK-NEXT:    li 4, -1
210; CHECK-NEXT:    iseleq 3, 3, 4
211; CHECK-NEXT:    blr
212  %a = add i8 %x, %y
213  %c = icmp ugt i8 %x, %a
214  %r = select i1 %c, i8 -1, i8 %a
215  ret i8 %r
216}
217
218define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
219; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    not 6, 4
222; CHECK-NEXT:    clrlwi 7, 3, 24
223; CHECK-NEXT:    li 5, -1
224; CHECK-NEXT:    add 3, 3, 4
225; CHECK-NEXT:    clrlwi 6, 6, 24
226; CHECK-NEXT:    cmplw 7, 6
227; CHECK-NEXT:    iselgt 3, 5, 3
228; CHECK-NEXT:    blr
229  %noty = xor i8 %y, -1
230  %a = add i8 %x, %y
231  %c = icmp ugt i8 %x, %noty
232  %r = select i1 %c, i8 -1, i8 %a
233  ret i8 %r
234}
235
236define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
237; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    not 5, 4
240; CHECK-NEXT:    clrlwi 6, 3, 16
241; CHECK-NEXT:    clrlwi 7, 5, 16
242; CHECK-NEXT:    cmplw 6, 7
243; CHECK-NEXT:    isellt 3, 3, 5
244; CHECK-NEXT:    add 3, 3, 4
245; CHECK-NEXT:    blr
246  %noty = xor i16 %y, -1
247  %c = icmp ult i16 %x, %noty
248  %s = select i1 %c, i16 %x, i16 %noty
249  %r = add i16 %s, %y
250  ret i16 %r
251}
252
253define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
254; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    clrlwi 4, 4, 16
257; CHECK-NEXT:    clrlwi 3, 3, 16
258; CHECK-NEXT:    add 3, 3, 4
259; CHECK-NEXT:    andis. 4, 3, 1
260; CHECK-NEXT:    li 4, -1
261; CHECK-NEXT:    iseleq 3, 3, 4
262; CHECK-NEXT:    blr
263  %a = add i16 %x, %y
264  %c = icmp ugt i16 %x, %a
265  %r = select i1 %c, i16 -1, i16 %a
266  ret i16 %r
267}
268
269define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
270; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    not 6, 4
273; CHECK-NEXT:    clrlwi 7, 3, 16
274; CHECK-NEXT:    li 5, -1
275; CHECK-NEXT:    add 3, 3, 4
276; CHECK-NEXT:    clrlwi 6, 6, 16
277; CHECK-NEXT:    cmplw 7, 6
278; CHECK-NEXT:    iselgt 3, 5, 3
279; CHECK-NEXT:    blr
280  %noty = xor i16 %y, -1
281  %a = add i16 %x, %y
282  %c = icmp ugt i16 %x, %noty
283  %r = select i1 %c, i16 -1, i16 %a
284  ret i16 %r
285}
286
287define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) {
288; CHECK-LABEL: unsigned_sat_variable_i32_using_min:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    not 5, 4
291; CHECK-NEXT:    cmplw 3, 5
292; CHECK-NEXT:    isellt 3, 3, 5
293; CHECK-NEXT:    add 3, 3, 4
294; CHECK-NEXT:    blr
295  %noty = xor i32 %y, -1
296  %c = icmp ult i32 %x, %noty
297  %s = select i1 %c, i32 %x, i32 %noty
298  %r = add i32 %s, %y
299  ret i32 %r
300}
301
302define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
303; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_sum:
304; CHECK:       # %bb.0:
305; CHECK-NEXT:    add 4, 3, 4
306; CHECK-NEXT:    li 5, -1
307; CHECK-NEXT:    cmplw 4, 3
308; CHECK-NEXT:    isellt 3, 5, 4
309; CHECK-NEXT:    blr
310  %a = add i32 %x, %y
311  %c = icmp ugt i32 %x, %a
312  %r = select i1 %c, i32 -1, i32 %a
313  ret i32 %r
314}
315
316define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {
317; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:
318; CHECK:       # %bb.0:
319; CHECK-NEXT:    not 6, 4
320; CHECK-NEXT:    li 5, -1
321; CHECK-NEXT:    cmplw 3, 6
322; CHECK-NEXT:    add 3, 3, 4
323; CHECK-NEXT:    iselgt 3, 5, 3
324; CHECK-NEXT:    blr
325  %noty = xor i32 %y, -1
326  %a = add i32 %x, %y
327  %c = icmp ugt i32 %x, %noty
328  %r = select i1 %c, i32 -1, i32 %a
329  ret i32 %r
330}
331
332define i64 @unsigned_sat_variable_i64_using_min(i64 %x, i64 %y) {
333; CHECK-LABEL: unsigned_sat_variable_i64_using_min:
334; CHECK:       # %bb.0:
335; CHECK-NEXT:    not 5, 4
336; CHECK-NEXT:    cmpld 3, 5
337; CHECK-NEXT:    isellt 3, 3, 5
338; CHECK-NEXT:    add 3, 3, 4
339; CHECK-NEXT:    blr
340  %noty = xor i64 %y, -1
341  %c = icmp ult i64 %x, %noty
342  %s = select i1 %c, i64 %x, i64 %noty
343  %r = add i64 %s, %y
344  ret i64 %r
345}
346
347define i64 @unsigned_sat_variable_i64_using_cmp_sum(i64 %x, i64 %y) {
348; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_sum:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    add 4, 3, 4
351; CHECK-NEXT:    li 5, -1
352; CHECK-NEXT:    cmpld 4, 3
353; CHECK-NEXT:    isellt 3, 5, 4
354; CHECK-NEXT:    blr
355  %a = add i64 %x, %y
356  %c = icmp ugt i64 %x, %a
357  %r = select i1 %c, i64 -1, i64 %a
358  ret i64 %r
359}
360
361define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {
362; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_notval:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    not 6, 4
365; CHECK-NEXT:    li 5, -1
366; CHECK-NEXT:    cmpld 3, 6
367; CHECK-NEXT:    add 3, 3, 4
368; CHECK-NEXT:    iselgt 3, 5, 3
369; CHECK-NEXT:    blr
370  %noty = xor i64 %y, -1
371  %a = add i64 %x, %y
372  %c = icmp ugt i64 %x, %noty
373  %r = select i1 %c, i64 -1, i64 %a
374  ret i64 %r
375}
376
377define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
378; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min:
379; CHECK:       # %bb.0:
380; CHECK-NEXT:    addis 3, 2, .LCPI24_0@toc@ha
381; CHECK-NEXT:    addi 3, 3, .LCPI24_0@toc@l
382; CHECK-NEXT:    lxvd2x 0, 0, 3
383; CHECK-NEXT:    addis 3, 2, .LCPI24_1@toc@ha
384; CHECK-NEXT:    addi 3, 3, .LCPI24_1@toc@l
385; CHECK-NEXT:    xxswapd 35, 0
386; CHECK-NEXT:    lxvd2x 0, 0, 3
387; CHECK-NEXT:    vminub 2, 2, 3
388; CHECK-NEXT:    xxswapd 35, 0
389; CHECK-NEXT:    vaddubm 2, 2, 3
390; CHECK-NEXT:    blr
391  %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
392  %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
393  %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
394  ret <16 x i8> %r
395}
396
397define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
398; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
399; CHECK:       # %bb.0:
400; CHECK-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
401; CHECK-NEXT:    addi 3, 3, .LCPI25_0@toc@l
402; CHECK-NEXT:    lxvd2x 0, 0, 3
403; CHECK-NEXT:    xxswapd 35, 0
404; CHECK-NEXT:    vaddubs 2, 2, 3
405; CHECK-NEXT:    blr
406  %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
407  %c = icmp ugt <16 x i8> %x, %a
408  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
409  ret <16 x i8> %r
410}
411
412define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
413; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
416; CHECK-NEXT:    addi 3, 3, .LCPI26_0@toc@l
417; CHECK-NEXT:    lxvd2x 0, 0, 3
418; CHECK-NEXT:    xxswapd 35, 0
419; CHECK-NEXT:    vaddubs 2, 2, 3
420; CHECK-NEXT:    blr
421  %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
422  %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
423  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
424  ret <16 x i8> %r
425}
426
427define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
428; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min:
429; CHECK:       # %bb.0:
430; CHECK-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
431; CHECK-NEXT:    addi 3, 3, .LCPI27_0@toc@l
432; CHECK-NEXT:    lxvd2x 0, 0, 3
433; CHECK-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
434; CHECK-NEXT:    addi 3, 3, .LCPI27_1@toc@l
435; CHECK-NEXT:    xxswapd 35, 0
436; CHECK-NEXT:    lxvd2x 0, 0, 3
437; CHECK-NEXT:    vminuh 2, 2, 3
438; CHECK-NEXT:    xxswapd 35, 0
439; CHECK-NEXT:    vadduhm 2, 2, 3
440; CHECK-NEXT:    blr
441  %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
442  %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
443  %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
444  ret <8 x i16> %r
445}
446
447define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
448; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
449; CHECK:       # %bb.0:
450; CHECK-NEXT:    addis 3, 2, .LCPI28_0@toc@ha
451; CHECK-NEXT:    addi 3, 3, .LCPI28_0@toc@l
452; CHECK-NEXT:    lxvd2x 0, 0, 3
453; CHECK-NEXT:    xxswapd 35, 0
454; CHECK-NEXT:    vadduhs 2, 2, 3
455; CHECK-NEXT:    blr
456  %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
457  %c = icmp ugt <8 x i16> %x, %a
458  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
459  ret <8 x i16> %r
460}
461
462define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
463; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
466; CHECK-NEXT:    addi 3, 3, .LCPI29_0@toc@l
467; CHECK-NEXT:    lxvd2x 0, 0, 3
468; CHECK-NEXT:    xxswapd 35, 0
469; CHECK-NEXT:    vadduhs 2, 2, 3
470; CHECK-NEXT:    blr
471  %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
472  %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
473  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
474  ret <8 x i16> %r
475}
476
477define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
478; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    addis 3, 2, .LCPI30_0@toc@ha
481; CHECK-NEXT:    addi 3, 3, .LCPI30_0@toc@l
482; CHECK-NEXT:    lxvd2x 0, 0, 3
483; CHECK-NEXT:    addis 3, 2, .LCPI30_1@toc@ha
484; CHECK-NEXT:    addi 3, 3, .LCPI30_1@toc@l
485; CHECK-NEXT:    xxswapd 35, 0
486; CHECK-NEXT:    lxvd2x 0, 0, 3
487; CHECK-NEXT:    vminuw 2, 2, 3
488; CHECK-NEXT:    xxswapd 35, 0
489; CHECK-NEXT:    vadduwm 2, 2, 3
490; CHECK-NEXT:    blr
491  %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
492  %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43>
493  %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>
494  ret <4 x i32> %r
495}
496
497define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
498; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
501; CHECK-NEXT:    addi 3, 3, .LCPI31_0@toc@l
502; CHECK-NEXT:    lxvd2x 0, 0, 3
503; CHECK-NEXT:    xxswapd 35, 0
504; CHECK-NEXT:    vadduws 2, 2, 3
505; CHECK-NEXT:    blr
506  %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
507  %c = icmp ugt <4 x i32> %x, %a
508  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
509  ret <4 x i32> %r
510}
511
512define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
513; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
514; CHECK:       # %bb.0:
515; CHECK-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
516; CHECK-NEXT:    addi 3, 3, .LCPI32_0@toc@l
517; CHECK-NEXT:    lxvd2x 0, 0, 3
518; CHECK-NEXT:    xxswapd 35, 0
519; CHECK-NEXT:    vadduws 2, 2, 3
520; CHECK-NEXT:    blr
521  %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
522  %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
523  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
524  ret <4 x i32> %r
525}
526
527define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
528; CHECK-LABEL: unsigned_sat_constant_v2i64_using_min:
529; CHECK:       # %bb.0:
530; CHECK-NEXT:    addis 3, 2, .LCPI33_0@toc@ha
531; CHECK-NEXT:    addi 3, 3, .LCPI33_0@toc@l
532; CHECK-NEXT:    lxvd2x 0, 0, 3
533; CHECK-NEXT:    addis 3, 2, .LCPI33_1@toc@ha
534; CHECK-NEXT:    addi 3, 3, .LCPI33_1@toc@l
535; CHECK-NEXT:    xxswapd 35, 0
536; CHECK-NEXT:    lxvd2x 0, 0, 3
537; CHECK-NEXT:    vminud 2, 2, 3
538; CHECK-NEXT:    xxswapd 35, 0
539; CHECK-NEXT:    vaddudm 2, 2, 3
540; CHECK-NEXT:    blr
541  %c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>
542  %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>
543  %r = add <2 x i64> %s, <i64 42, i64 42>
544  ret <2 x i64> %r
545}
546
547define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
548; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
549; CHECK:       # %bb.0:
550; CHECK-NEXT:    addis 3, 2, .LCPI34_0@toc@ha
551; CHECK-NEXT:    addi 3, 3, .LCPI34_0@toc@l
552; CHECK-NEXT:    lxvd2x 0, 0, 3
553; CHECK-NEXT:    xxswapd 35, 0
554; CHECK-NEXT:    xxleqv 0, 0, 0
555; CHECK-NEXT:    vaddudm 3, 2, 3
556; CHECK-NEXT:    vcmpgtud 2, 2, 3
557; CHECK-NEXT:    xxsel 34, 35, 0, 34
558; CHECK-NEXT:    blr
559  %a = add <2 x i64> %x, <i64 42, i64 42>
560  %c = icmp ugt <2 x i64> %x, %a
561  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
562  ret <2 x i64> %r
563}
564
565define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
566; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
567; CHECK:       # %bb.0:
568; CHECK-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
569; CHECK-NEXT:    addi 3, 3, .LCPI35_1@toc@l
570; CHECK-NEXT:    lxvd2x 0, 0, 3
571; CHECK-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
572; CHECK-NEXT:    addi 3, 3, .LCPI35_0@toc@l
573; CHECK-NEXT:    lxvd2x 1, 0, 3
574; CHECK-NEXT:    xxswapd 35, 0
575; CHECK-NEXT:    xxleqv 0, 0, 0
576; CHECK-NEXT:    xxswapd 36, 1
577; CHECK-NEXT:    vcmpgtud 3, 2, 3
578; CHECK-NEXT:    vaddudm 2, 2, 4
579; CHECK-NEXT:    xxsel 34, 34, 0, 35
580; CHECK-NEXT:    blr
581  %a = add <2 x i64> %x, <i64 42, i64 42>
582  %c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
583  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
584  ret <2 x i64> %r
585}
586
587define <16 x i8> @unsigned_sat_variable_v16i8_using_min(<16 x i8> %x, <16 x i8> %y) {
588; CHECK-LABEL: unsigned_sat_variable_v16i8_using_min:
589; CHECK:       # %bb.0:
590; CHECK-NEXT:    xxlnor 36, 35, 35
591; CHECK-NEXT:    vminub 2, 2, 4
592; CHECK-NEXT:    vaddubm 2, 2, 3
593; CHECK-NEXT:    blr
594  %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
595  %c = icmp ult <16 x i8> %x, %noty
596  %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %noty
597  %r = add <16 x i8> %s, %y
598  ret <16 x i8> %r
599}
600
601define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x i8> %y) {
602; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum:
603; CHECK:       # %bb.0:
604; CHECK-NEXT:    vaddubs 2, 2, 3
605; CHECK-NEXT:    blr
606  %a = add <16 x i8> %x, %y
607  %c = icmp ugt <16 x i8> %x, %a
608  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
609  ret <16 x i8> %r
610}
611
612define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16 x i8> %y) {
613; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    xxlnor 36, 35, 35
616; CHECK-NEXT:    xxleqv 0, 0, 0
617; CHECK-NEXT:    vcmpgtub 4, 2, 4
618; CHECK-NEXT:    vaddubm 2, 2, 3
619; CHECK-NEXT:    xxsel 34, 34, 0, 36
620; CHECK-NEXT:    blr
621  %noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
622  %a = add <16 x i8> %x, %y
623  %c = icmp ugt <16 x i8> %x, %noty
624  %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
625  ret <16 x i8> %r
626}
627
628define <8 x i16> @unsigned_sat_variable_v8i16_using_min(<8 x i16> %x, <8 x i16> %y) {
629; CHECK-LABEL: unsigned_sat_variable_v8i16_using_min:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    xxlnor 36, 35, 35
632; CHECK-NEXT:    vminuh 2, 2, 4
633; CHECK-NEXT:    vadduhm 2, 2, 3
634; CHECK-NEXT:    blr
635  %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
636  %c = icmp ult <8 x i16> %x, %noty
637  %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %noty
638  %r = add <8 x i16> %s, %y
639  ret <8 x i16> %r
640}
641
642define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i16> %y) {
643; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum:
644; CHECK:       # %bb.0:
645; CHECK-NEXT:    vadduhs 2, 2, 3
646; CHECK-NEXT:    blr
647  %a = add <8 x i16> %x, %y
648  %c = icmp ugt <8 x i16> %x, %a
649  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
650  ret <8 x i16> %r
651}
652
653define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8 x i16> %y) {
654; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval:
655; CHECK:       # %bb.0:
656; CHECK-NEXT:    xxlnor 36, 35, 35
657; CHECK-NEXT:    xxleqv 0, 0, 0
658; CHECK-NEXT:    vcmpgtuh 4, 2, 4
659; CHECK-NEXT:    vadduhm 2, 2, 3
660; CHECK-NEXT:    xxsel 34, 34, 0, 36
661; CHECK-NEXT:    blr
662  %noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
663  %a = add <8 x i16> %x, %y
664  %c = icmp ugt <8 x i16> %x, %noty
665  %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
666  ret <8 x i16> %r
667}
668
669define <4 x i32> @unsigned_sat_variable_v4i32_using_min(<4 x i32> %x, <4 x i32> %y) {
670; CHECK-LABEL: unsigned_sat_variable_v4i32_using_min:
671; CHECK:       # %bb.0:
672; CHECK-NEXT:    xxlnor 36, 35, 35
673; CHECK-NEXT:    vminuw 2, 2, 4
674; CHECK-NEXT:    vadduwm 2, 2, 3
675; CHECK-NEXT:    blr
676  %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
677  %c = icmp ult <4 x i32> %x, %noty
678  %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %noty
679  %r = add <4 x i32> %s, %y
680  ret <4 x i32> %r
681}
682
683define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i32> %y) {
684; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum:
685; CHECK:       # %bb.0:
686; CHECK-NEXT:    vadduws 2, 2, 3
687; CHECK-NEXT:    blr
688  %a = add <4 x i32> %x, %y
689  %c = icmp ugt <4 x i32> %x, %a
690  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
691  ret <4 x i32> %r
692}
693
694define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4 x i32> %y) {
695; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval:
696; CHECK:       # %bb.0:
697; CHECK-NEXT:    xxlnor 36, 35, 35
698; CHECK-NEXT:    xxleqv 0, 0, 0
699; CHECK-NEXT:    vcmpgtuw 4, 2, 4
700; CHECK-NEXT:    vadduwm 2, 2, 3
701; CHECK-NEXT:    xxsel 34, 34, 0, 36
702; CHECK-NEXT:    blr
703  %noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
704  %a = add <4 x i32> %x, %y
705  %c = icmp ugt <4 x i32> %x, %noty
706  %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
707  ret <4 x i32> %r
708}
709
710define <2 x i64> @unsigned_sat_variable_v2i64_using_min(<2 x i64> %x, <2 x i64> %y) {
711; CHECK-LABEL: unsigned_sat_variable_v2i64_using_min:
712; CHECK:       # %bb.0:
713; CHECK-NEXT:    xxlnor 36, 35, 35
714; CHECK-NEXT:    vminud 2, 2, 4
715; CHECK-NEXT:    vaddudm 2, 2, 3
716; CHECK-NEXT:    blr
717  %noty = xor <2 x i64> %y, <i64 -1, i64 -1>
718  %c = icmp ult <2 x i64> %x, %noty
719  %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %noty
720  %r = add <2 x i64> %s, %y
721  ret <2 x i64> %r
722}
723
724define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i64> %y) {
725; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:
726; CHECK:       # %bb.0:
727; CHECK-NEXT:    vaddudm 3, 2, 3
728; CHECK-NEXT:    xxleqv 0, 0, 0
729; CHECK-NEXT:    vcmpgtud 2, 2, 3
730; CHECK-NEXT:    xxsel 34, 35, 0, 34
731; CHECK-NEXT:    blr
732  %a = add <2 x i64> %x, %y
733  %c = icmp ugt <2 x i64> %x, %a
734  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
735  ret <2 x i64> %r
736}
737
738define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2 x i64> %y) {
739; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval:
740; CHECK:       # %bb.0:
741; CHECK-NEXT:    xxlnor 36, 35, 35
742; CHECK-NEXT:    xxleqv 0, 0, 0
743; CHECK-NEXT:    vcmpgtud 4, 2, 4
744; CHECK-NEXT:    vaddudm 2, 2, 3
745; CHECK-NEXT:    xxsel 34, 34, 0, 36
746; CHECK-NEXT:    blr
747  %noty = xor <2 x i64> %y, <i64 -1, i64 -1>
748  %a = add <2 x i64> %x, %y
749  %c = icmp ugt <2 x i64> %x, %noty
750  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
751  ret <2 x i64> %r
752}
753
754declare <4 x i128> @llvm.sadd.sat.v4i128(<4 x i128> %a, <4 x i128> %b);
755
756define <4 x i128> @sadd(<4 x i128> %a, <4 x i128> %b) local_unnamed_addr {
757; CHECK-LABEL: sadd:
758; CHECK:       # %bb.0:
759; CHECK-NEXT:    vadduqm 0, 2, 6
760; CHECK-NEXT:    xxswapd 0, 34
761; CHECK-NEXT:    std 30, -16(1) # 8-byte Folded Spill
762; CHECK-NEXT:    addis 3, 2, .LCPI48_0@toc@ha
763; CHECK-NEXT:    vadduqm 1, 3, 7
764; CHECK-NEXT:    xxswapd 1, 35
765; CHECK-NEXT:    addi 3, 3, .LCPI48_0@toc@l
766; CHECK-NEXT:    xxswapd 3, 32
767; CHECK-NEXT:    mfvsrd 4, 34
768; CHECK-NEXT:    mfvsrd 8, 32
769; CHECK-NEXT:    xxswapd 2, 36
770; CHECK-NEXT:    mffprd 12, 0
771; CHECK-NEXT:    xxswapd 0, 33
772; CHECK-NEXT:    vadduqm 10, 4, 8
773; CHECK-NEXT:    cmpld 8, 4
774; CHECK-NEXT:    cmpd 1, 8, 4
775; CHECK-NEXT:    mffprd 4, 3
776; CHECK-NEXT:    lxvd2x 3, 0, 3
777; CHECK-NEXT:    sradi 3, 8, 63
778; CHECK-NEXT:    mffprd 0, 1
779; CHECK-NEXT:    xxswapd 1, 37
780; CHECK-NEXT:    mfvsrd 5, 35
781; CHECK-NEXT:    vadduqm 11, 5, 9
782; CHECK-NEXT:    xxswapd 34, 3
783; CHECK-NEXT:    mfvsrd 9, 33
784; CHECK-NEXT:    crandc 20, 4, 2
785; CHECK-NEXT:    cmpld 1, 4, 12
786; CHECK-NEXT:    mffprd 4, 0
787; CHECK-NEXT:    xxswapd 0, 42
788; CHECK-NEXT:    mfvsrd 6, 36
789; CHECK-NEXT:    mfvsrd 10, 42
790; CHECK-NEXT:    cmpld 6, 4, 0
791; CHECK-NEXT:    crand 21, 2, 4
792; CHECK-NEXT:    cmpld 9, 5
793; CHECK-NEXT:    cmpd 1, 9, 5
794; CHECK-NEXT:    mffprd 5, 1
795; CHECK-NEXT:    xxswapd 1, 43
796; CHECK-NEXT:    mffprd 30, 2
797; CHECK-NEXT:    mffprd 4, 0
798; CHECK-NEXT:    mfvsrd 7, 37
799; CHECK-NEXT:    mfvsrd 11, 43
800; CHECK-NEXT:    crandc 22, 4, 2
801; CHECK-NEXT:    cmpd 1, 10, 6
802; CHECK-NEXT:    crand 23, 2, 24
803; CHECK-NEXT:    cmpld 10, 6
804; CHECK-NEXT:    crandc 24, 4, 2
805; CHECK-NEXT:    cmpld 1, 4, 30
806; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
807; CHECK-NEXT:    mffprd 4, 1
808; CHECK-NEXT:    mfvsrd 6, 38
809; CHECK-NEXT:    crand 25, 2, 4
810; CHECK-NEXT:    cmpld 11, 7
811; CHECK-NEXT:    cmpd 1, 11, 7
812; CHECK-NEXT:    crandc 26, 4, 2
813; CHECK-NEXT:    cmpld 1, 4, 5
814; CHECK-NEXT:    sradi 4, 6, 63
815; CHECK-NEXT:    mtfprd 0, 4
816; CHECK-NEXT:    mfvsrd 4, 39
817; CHECK-NEXT:    mfvsrd 5, 40
818; CHECK-NEXT:    mfvsrd 6, 41
819; CHECK-NEXT:    sradi 4, 4, 63
820; CHECK-NEXT:    mtfprd 1, 4
821; CHECK-NEXT:    sradi 4, 5, 63
822; CHECK-NEXT:    mtfprd 2, 4
823; CHECK-NEXT:    sradi 4, 6, 63
824; CHECK-NEXT:    mtfprd 5, 3
825; CHECK-NEXT:    sradi 3, 10, 63
826; CHECK-NEXT:    mtfprd 4, 4
827; CHECK-NEXT:    sradi 4, 9, 63
828; CHECK-NEXT:    mtfprd 6, 4
829; CHECK-NEXT:    xxspltd 35, 5, 0
830; CHECK-NEXT:    sradi 4, 11, 63
831; CHECK-NEXT:    crnor 20, 21, 20
832; CHECK-NEXT:    xxspltd 38, 4, 0
833; CHECK-NEXT:    mtfprd 3, 3
834; CHECK-NEXT:    li 3, -1
835; CHECK-NEXT:    xxspltd 36, 6, 0
836; CHECK-NEXT:    mtfprd 5, 4
837; CHECK-NEXT:    crand 27, 2, 4
838; CHECK-NEXT:    xxspltd 37, 3, 0
839; CHECK-NEXT:    xxlxor 3, 35, 34
840; CHECK-NEXT:    xxspltd 35, 5, 0
841; CHECK-NEXT:    isel 4, 0, 3, 20
842; CHECK-NEXT:    mtfprd 8, 4
843; CHECK-NEXT:    crnor 20, 23, 22
844; CHECK-NEXT:    crnor 21, 25, 24
845; CHECK-NEXT:    crnor 22, 27, 26
846; CHECK-NEXT:    xxlxor 5, 36, 34
847; CHECK-NEXT:    xxspltd 36, 2, 0
848; CHECK-NEXT:    xxlxor 6, 37, 34
849; CHECK-NEXT:    xxlxor 7, 35, 34
850; CHECK-NEXT:    xxspltd 34, 0, 0
851; CHECK-NEXT:    xxspltd 35, 8, 0
852; CHECK-NEXT:    isel 4, 0, 3, 20
853; CHECK-NEXT:    isel 5, 0, 3, 21
854; CHECK-NEXT:    isel 3, 0, 3, 22
855; CHECK-NEXT:    xxlxor 0, 34, 35
856; CHECK-NEXT:    xxspltd 34, 1, 0
857; CHECK-NEXT:    mtfprd 8, 4
858; CHECK-NEXT:    mtfprd 1, 5
859; CHECK-NEXT:    mtfprd 9, 3
860; CHECK-NEXT:    xxspltd 35, 8, 0
861; CHECK-NEXT:    xxspltd 37, 1, 0
862; CHECK-NEXT:    xxspltd 39, 9, 0
863; CHECK-NEXT:    xxlxor 1, 34, 35
864; CHECK-NEXT:    xxsel 34, 32, 3, 0
865; CHECK-NEXT:    xxlxor 2, 36, 37
866; CHECK-NEXT:    xxlxor 4, 38, 39
867; CHECK-NEXT:    xxsel 35, 33, 5, 1
868; CHECK-NEXT:    xxsel 36, 42, 6, 2
869; CHECK-NEXT:    xxsel 37, 43, 7, 4
870; CHECK-NEXT:    blr
871  %c = call <4 x i128> @llvm.sadd.sat.v4i128(<4 x i128> %a, <4 x i128> %b)
872  ret <4 x i128> %c
873}
874
875define i64 @unsigned_sat_constant_i64_with_single_use(i64 %x) {
876; CHECK-LABEL: unsigned_sat_constant_i64_with_single_use:
877; CHECK:       # %bb.0:
878; CHECK-NEXT:    addi 4, 3, -4
879; CHECK-NEXT:    cmpld 4, 3
880; CHECK-NEXT:    iselgt 3, 0, 4
881; CHECK-NEXT:    blr
882  %umin = call i64 @llvm.umin.i64(i64 %x, i64 4)
883  %sub = sub i64 %x, %umin
884  ret i64 %sub
885}
886
887define i64 @unsigned_sat_constant_i64_with_multiple_use(i64 %x, i64 %y) {
888; CHECK-LABEL: unsigned_sat_constant_i64_with_multiple_use:
889; CHECK:       # %bb.0:
890; CHECK-NEXT:    li 5, 4
891; CHECK-NEXT:    cmpldi 3, 4
892; CHECK-NEXT:    isellt 5, 3, 5
893; CHECK-NEXT:    sub 3, 3, 5
894; CHECK-NEXT:    add 4, 4, 5
895; CHECK-NEXT:    mulld 3, 3, 4
896; CHECK-NEXT:    blr
897  %umin = call i64 @llvm.umin.i64(i64 %x, i64 4)
898  %sub = sub i64 %x, %umin
899  %add = add i64 %y, %umin
900  %res = mul i64 %sub, %add
901  ret i64 %res
902}
903
904declare i64 @llvm.umin.i64(i64, i64)
905