1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
4
5define <8 x i16> @pr25080(<8 x i32> %a) {
6; LE-LABEL: pr25080:
7; LE:       # %bb.0: # %entry
8; LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
9; LE-NEXT:    xxlxor 37, 37, 37
10; LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
11; LE-NEXT:    lvx 4, 0, 3
12; LE-NEXT:    xxland 34, 34, 36
13; LE-NEXT:    xxland 35, 35, 36
14; LE-NEXT:    vcmpequw 2, 2, 5
15; LE-NEXT:    vcmpequw 3, 3, 5
16; LE-NEXT:    xxswapd 0, 34
17; LE-NEXT:    mfvsrwz 3, 34
18; LE-NEXT:    xxsldwi 1, 34, 34, 1
19; LE-NEXT:    mfvsrwz 4, 35
20; LE-NEXT:    xxsldwi 4, 34, 34, 3
21; LE-NEXT:    mtvsrd 2, 3
22; LE-NEXT:    mfvsrwz 3, 0
23; LE-NEXT:    xxswapd 0, 35
24; LE-NEXT:    mtvsrd 3, 4
25; LE-NEXT:    xxsldwi 5, 35, 35, 1
26; LE-NEXT:    mfvsrwz 4, 1
27; LE-NEXT:    xxsldwi 7, 35, 35, 3
28; LE-NEXT:    mtvsrd 1, 3
29; LE-NEXT:    xxswapd 33, 3
30; LE-NEXT:    mfvsrwz 3, 4
31; LE-NEXT:    mtvsrd 4, 4
32; LE-NEXT:    xxswapd 34, 1
33; LE-NEXT:    mfvsrwz 4, 0
34; LE-NEXT:    mtvsrd 0, 3
35; LE-NEXT:    xxswapd 35, 4
36; LE-NEXT:    mfvsrwz 3, 5
37; LE-NEXT:    mtvsrd 6, 4
38; LE-NEXT:    xxswapd 36, 0
39; LE-NEXT:    mtvsrd 1, 3
40; LE-NEXT:    mfvsrwz 3, 7
41; LE-NEXT:    xxswapd 37, 6
42; LE-NEXT:    vmrglh 2, 3, 2
43; LE-NEXT:    xxswapd 35, 2
44; LE-NEXT:    mtvsrd 2, 3
45; LE-NEXT:    xxswapd 32, 1
46; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
47; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
48; LE-NEXT:    xxswapd 38, 2
49; LE-NEXT:    vmrglh 3, 4, 3
50; LE-NEXT:    vmrglh 4, 0, 5
51; LE-NEXT:    vmrglh 5, 6, 1
52; LE-NEXT:    vmrglw 2, 3, 2
53; LE-NEXT:    vmrglw 3, 5, 4
54; LE-NEXT:    vspltish 4, 15
55; LE-NEXT:    xxmrgld 34, 35, 34
56; LE-NEXT:    lvx 3, 0, 3
57; LE-NEXT:    xxlor 34, 34, 35
58; LE-NEXT:    vslh 2, 2, 4
59; LE-NEXT:    vsrah 2, 2, 4
60; LE-NEXT:    blr
61;
62; BE-LABEL: pr25080:
63; BE:       # %bb.0: # %entry
64; BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
65; BE-NEXT:    xxlxor 36, 36, 36
66; BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
67; BE-NEXT:    lxvw4x 0, 0, 3
68; BE-NEXT:    xxland 35, 35, 0
69; BE-NEXT:    xxland 34, 34, 0
70; BE-NEXT:    vcmpequw 3, 3, 4
71; BE-NEXT:    vcmpequw 2, 2, 4
72; BE-NEXT:    xxswapd 0, 35
73; BE-NEXT:    mfvsrwz 3, 35
74; BE-NEXT:    xxsldwi 1, 35, 35, 1
75; BE-NEXT:    sldi 3, 3, 48
76; BE-NEXT:    mfvsrwz 4, 0
77; BE-NEXT:    xxsldwi 0, 35, 35, 3
78; BE-NEXT:    mtvsrd 36, 3
79; BE-NEXT:    mfvsrwz 3, 1
80; BE-NEXT:    sldi 4, 4, 48
81; BE-NEXT:    xxswapd 1, 34
82; BE-NEXT:    mtvsrd 35, 4
83; BE-NEXT:    mfvsrwz 4, 34
84; BE-NEXT:    sldi 3, 3, 48
85; BE-NEXT:    mtvsrd 37, 3
86; BE-NEXT:    mfvsrwz 3, 0
87; BE-NEXT:    sldi 4, 4, 48
88; BE-NEXT:    xxsldwi 0, 34, 34, 1
89; BE-NEXT:    vmrghh 3, 5, 3
90; BE-NEXT:    mtvsrd 37, 4
91; BE-NEXT:    sldi 3, 3, 48
92; BE-NEXT:    mfvsrwz 4, 1
93; BE-NEXT:    xxsldwi 1, 34, 34, 3
94; BE-NEXT:    mtvsrd 34, 3
95; BE-NEXT:    mfvsrwz 3, 0
96; BE-NEXT:    sldi 4, 4, 48
97; BE-NEXT:    mtvsrd 32, 4
98; BE-NEXT:    mfvsrwz 4, 1
99; BE-NEXT:    sldi 3, 3, 48
100; BE-NEXT:    mtvsrd 33, 3
101; BE-NEXT:    sldi 3, 4, 48
102; BE-NEXT:    vmrghh 2, 2, 4
103; BE-NEXT:    mtvsrd 36, 3
104; BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
105; BE-NEXT:    vmrghh 0, 1, 0
106; BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
107; BE-NEXT:    vmrghh 4, 4, 5
108; BE-NEXT:    lxvw4x 0, 0, 3
109; BE-NEXT:    vmrghw 2, 2, 3
110; BE-NEXT:    vmrghw 3, 4, 0
111; BE-NEXT:    xxmrghd 34, 35, 34
112; BE-NEXT:    vspltish 3, 15
113; BE-NEXT:    xxlor 34, 34, 0
114; BE-NEXT:    vslh 2, 2, 3
115; BE-NEXT:    vsrah 2, 2, 3
116; BE-NEXT:    blr
117entry:
118  %0 = trunc <8 x i32> %a to <8 x i23>
119  %1 = icmp eq <8 x i23> %0, zeroinitializer
120  %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
121  %3 = sext <8 x i1> %2 to <8 x i16>
122  ret <8 x i16> %3
123}
124