1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
4
5define <8 x i16> @pr25080(<8 x i32> %a) {
6; LE-LABEL: pr25080:
7; LE:       # %bb.0: # %entry
8; LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
9; LE-NEXT:    xxlxor 37, 37, 37
10; LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
11; LE-NEXT:    lxvd2x 0, 0, 3
12; LE-NEXT:    xxswapd 36, 0
13; LE-NEXT:    xxland 34, 34, 36
14; LE-NEXT:    xxland 35, 35, 36
15; LE-NEXT:    vcmpequw 2, 2, 5
16; LE-NEXT:    vcmpequw 3, 3, 5
17; LE-NEXT:    xxswapd 0, 34
18; LE-NEXT:    mfvsrwz 3, 34
19; LE-NEXT:    xxsldwi 1, 34, 34, 1
20; LE-NEXT:    mfvsrwz 4, 35
21; LE-NEXT:    xxsldwi 2, 34, 34, 3
22; LE-NEXT:    mtvsrd 36, 3
23; LE-NEXT:    mffprwz 3, 0
24; LE-NEXT:    xxswapd 0, 35
25; LE-NEXT:    mtvsrd 37, 4
26; LE-NEXT:    mffprwz 4, 1
27; LE-NEXT:    xxsldwi 1, 35, 35, 1
28; LE-NEXT:    mtvsrd 34, 3
29; LE-NEXT:    mffprwz 3, 2
30; LE-NEXT:    mtvsrd 32, 4
31; LE-NEXT:    mffprwz 4, 0
32; LE-NEXT:    xxsldwi 0, 35, 35, 3
33; LE-NEXT:    mtvsrd 33, 3
34; LE-NEXT:    mffprwz 3, 1
35; LE-NEXT:    mtvsrd 38, 4
36; LE-NEXT:    mtvsrd 35, 3
37; LE-NEXT:    mffprwz 3, 0
38; LE-NEXT:    vmrghh 2, 0, 2
39; LE-NEXT:    mtvsrd 32, 3
40; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
41; LE-NEXT:    vmrghh 4, 1, 4
42; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
43; LE-NEXT:    vmrghh 3, 3, 6
44; LE-NEXT:    lxvd2x 2, 0, 3
45; LE-NEXT:    vmrghh 5, 0, 5
46; LE-NEXT:    xxmrglw 0, 36, 34
47; LE-NEXT:    xxmrglw 1, 37, 35
48; LE-NEXT:    xxswapd 35, 2
49; LE-NEXT:    xxmrgld 34, 1, 0
50; LE-NEXT:    xxlor 34, 34, 35
51; LE-NEXT:    blr
52;
53; BE-LABEL: pr25080:
54; BE:       # %bb.0: # %entry
55; BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
56; BE-NEXT:    xxlxor 36, 36, 36
57; BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
58; BE-NEXT:    lxvw4x 0, 0, 3
59; BE-NEXT:    xxland 35, 35, 0
60; BE-NEXT:    xxland 34, 34, 0
61; BE-NEXT:    vcmpequw 3, 3, 4
62; BE-NEXT:    vcmpequw 2, 2, 4
63; BE-NEXT:    xxswapd 0, 35
64; BE-NEXT:    mfvsrwz 3, 35
65; BE-NEXT:    xxsldwi 1, 35, 35, 1
66; BE-NEXT:    mfvsrwz 4, 34
67; BE-NEXT:    mtvsrwz 36, 3
68; BE-NEXT:    xxsldwi 2, 35, 35, 3
69; BE-NEXT:    mffprwz 3, 0
70; BE-NEXT:    xxswapd 0, 34
71; BE-NEXT:    mtvsrwz 35, 4
72; BE-NEXT:    mffprwz 4, 1
73; BE-NEXT:    xxsldwi 1, 34, 34, 1
74; BE-NEXT:    mtvsrwz 37, 3
75; BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
76; BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
77; BE-NEXT:    mtvsrwz 32, 4
78; BE-NEXT:    mffprwz 4, 0
79; BE-NEXT:    lxvw4x 33, 0, 3
80; BE-NEXT:    xxsldwi 0, 34, 34, 3
81; BE-NEXT:    mffprwz 3, 1
82; BE-NEXT:    mffprwz 5, 2
83; BE-NEXT:    vperm 2, 0, 5, 1
84; BE-NEXT:    mtvsrwz 37, 3
85; BE-NEXT:    mffprwz 3, 0
86; BE-NEXT:    mtvsrwz 38, 5
87; BE-NEXT:    mtvsrwz 39, 4
88; BE-NEXT:    mtvsrwz 32, 3
89; BE-NEXT:    addis 3, 2, .LCPI0_2@toc@ha
90; BE-NEXT:    vperm 4, 6, 4, 1
91; BE-NEXT:    addi 3, 3, .LCPI0_2@toc@l
92; BE-NEXT:    vperm 5, 5, 7, 1
93; BE-NEXT:    vperm 3, 0, 3, 1
94; BE-NEXT:    xxmrghw 0, 36, 34
95; BE-NEXT:    xxmrghw 1, 35, 37
96; BE-NEXT:    xxmrghd 34, 1, 0
97; BE-NEXT:    lxvw4x 0, 0, 3
98; BE-NEXT:    xxlor 34, 34, 0
99; BE-NEXT:    blr
100entry:
101  %0 = trunc <8 x i32> %a to <8 x i23>
102  %1 = icmp eq <8 x i23> %0, zeroinitializer
103  %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
104  %3 = sext <8 x i1> %2 to <8 x i16>
105  ret <8 x i16> %3
106}
107