1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
4
5define <8 x i16> @pr25080(<8 x i32> %a) {
6; LE-LABEL: pr25080:
7; LE:       # %bb.0: # %entry
8; LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
9; LE-NEXT:    xxlxor 37, 37, 37
10; LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
11; LE-NEXT:    lvx 4, 0, 3
12; LE-NEXT:    xxland 34, 34, 36
13; LE-NEXT:    xxland 35, 35, 36
14; LE-NEXT:    vcmpequw 2, 2, 5
15; LE-NEXT:    vcmpequw 3, 3, 5
16; LE-NEXT:    xxswapd 0, 34
17; LE-NEXT:    mfvsrwz 3, 34
18; LE-NEXT:    xxsldwi 1, 34, 34, 1
19; LE-NEXT:    mfvsrwz 4, 35
20; LE-NEXT:    xxsldwi 2, 34, 34, 3
21; LE-NEXT:    mtvsrd 36, 3
22; LE-NEXT:    mffprwz 3, 0
23; LE-NEXT:    xxswapd 0, 35
24; LE-NEXT:    mtvsrd 37, 4
25; LE-NEXT:    mffprwz 4, 1
26; LE-NEXT:    xxsldwi 1, 35, 35, 1
27; LE-NEXT:    mtvsrd 34, 3
28; LE-NEXT:    mffprwz 3, 2
29; LE-NEXT:    mtvsrd 32, 4
30; LE-NEXT:    mffprwz 4, 0
31; LE-NEXT:    xxsldwi 0, 35, 35, 3
32; LE-NEXT:    mtvsrd 33, 3
33; LE-NEXT:    mffprwz 3, 1
34; LE-NEXT:    mtvsrd 38, 4
35; LE-NEXT:    mtvsrd 35, 3
36; LE-NEXT:    mffprwz 3, 0
37; LE-NEXT:    vmrghh 2, 0, 2
38; LE-NEXT:    mtvsrd 32, 3
39; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
40; LE-NEXT:    vmrghh 4, 1, 4
41; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
42; LE-NEXT:    vmrghh 3, 3, 6
43; LE-NEXT:    vmrghh 5, 0, 5
44; LE-NEXT:    vmrglw 2, 4, 2
45; LE-NEXT:    vspltish 4, 15
46; LE-NEXT:    vmrglw 3, 5, 3
47; LE-NEXT:    xxmrgld 34, 35, 34
48; LE-NEXT:    lvx 3, 0, 3
49; LE-NEXT:    xxlor 34, 34, 35
50; LE-NEXT:    vslh 2, 2, 4
51; LE-NEXT:    vsrah 2, 2, 4
52; LE-NEXT:    blr
53;
54; BE-LABEL: pr25080:
55; BE:       # %bb.0: # %entry
56; BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
57; BE-NEXT:    xxlxor 36, 36, 36
58; BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
59; BE-NEXT:    lxvw4x 0, 0, 3
60; BE-NEXT:    xxland 35, 35, 0
61; BE-NEXT:    xxland 34, 34, 0
62; BE-NEXT:    vcmpequw 3, 3, 4
63; BE-NEXT:    vcmpequw 2, 2, 4
64; BE-NEXT:    xxswapd 0, 35
65; BE-NEXT:    mfvsrwz 3, 35
66; BE-NEXT:    xxsldwi 1, 35, 35, 1
67; BE-NEXT:    sldi 3, 3, 48
68; BE-NEXT:    mffprwz 4, 0
69; BE-NEXT:    xxsldwi 0, 35, 35, 3
70; BE-NEXT:    mtvsrd 36, 3
71; BE-NEXT:    mffprwz 3, 1
72; BE-NEXT:    sldi 4, 4, 48
73; BE-NEXT:    xxswapd 1, 34
74; BE-NEXT:    mtvsrd 35, 4
75; BE-NEXT:    mfvsrwz 4, 34
76; BE-NEXT:    sldi 3, 3, 48
77; BE-NEXT:    mtvsrd 37, 3
78; BE-NEXT:    mffprwz 3, 0
79; BE-NEXT:    sldi 4, 4, 48
80; BE-NEXT:    xxsldwi 0, 34, 34, 1
81; BE-NEXT:    vmrghh 3, 5, 3
82; BE-NEXT:    mtvsrd 37, 4
83; BE-NEXT:    sldi 3, 3, 48
84; BE-NEXT:    mffprwz 4, 1
85; BE-NEXT:    xxsldwi 1, 34, 34, 3
86; BE-NEXT:    mtvsrd 34, 3
87; BE-NEXT:    mffprwz 3, 0
88; BE-NEXT:    sldi 4, 4, 48
89; BE-NEXT:    mtvsrd 32, 4
90; BE-NEXT:    mffprwz 4, 1
91; BE-NEXT:    sldi 3, 3, 48
92; BE-NEXT:    mtvsrd 33, 3
93; BE-NEXT:    sldi 3, 4, 48
94; BE-NEXT:    vmrghh 2, 2, 4
95; BE-NEXT:    mtvsrd 36, 3
96; BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
97; BE-NEXT:    vmrghh 0, 1, 0
98; BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
99; BE-NEXT:    vmrghh 4, 4, 5
100; BE-NEXT:    lxvw4x 0, 0, 3
101; BE-NEXT:    vmrghw 2, 2, 3
102; BE-NEXT:    vmrghw 3, 4, 0
103; BE-NEXT:    xxmrghd 34, 35, 34
104; BE-NEXT:    vspltish 3, 15
105; BE-NEXT:    xxlor 34, 34, 0
106; BE-NEXT:    vslh 2, 2, 3
107; BE-NEXT:    vsrah 2, 2, 3
108; BE-NEXT:    blr
109entry:
110  %0 = trunc <8 x i32> %a to <8 x i23>
111  %1 = icmp eq <8 x i23> %0, zeroinitializer
112  %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
113  %3 = sext <8 x i1> %2 to <8 x i16>
114  ret <8 x i16> %3
115}
116