1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
3; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
4; RUN:    | FileCheck %s
5
6define void @copy_novsrp() local_unnamed_addr {
7; CHECK-LABEL: copy_novsrp:
8; CHECK:       # %bb.0: # %dmblvi_entry
9; CHECK-NEXT:    xxlxor v2, v2, v2
10; CHECK-NEXT:    xxlxor vs0, vs0, vs0
11; CHECK-NEXT:    xxlor vs3, v2, v2
12; CHECK-NEXT:    stxv vs1, 0(0)
13dmblvi_entry:
14  %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
15  %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
16  %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
17  store <16 x i8> %2, <16 x i8>* null, align 1
18  unreachable
19}
20
21declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
22declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
23