1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2target datalayout = "e-m:e-i64:64-n32:64" 3target triple = "powerpc64le-unknown-linux-gnu" 4; This file mainly tests the case that the two input registers of the ISEL instruction are the same register. 5; The foldable ISEL in this test case is introduced at simple register coalescing stage. 6 7; Before that stage we have: 8; %vreg18<def> = ISEL8 %vreg5, %vreg2, %vreg15<undef>; 9 10; At simple register coalescing stage, the register coalescer figures out it could remove the copy 11; from %vreg2 to %vreg5, put the original value %X3 into %vreg5 directly 12; erased: 336r %vreg5<def> = COPY %vreg2 13; updated: 288B %vreg5<def> = COPY %X3; 14 15; After that we have: 16; updated: 416B %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>; 17 18; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE 19; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel 20%"struct.pov::ot_block_struct" = type { %"struct.pov::ot_block_struct"*, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 } 21%"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", %"struct.pov::ot_block_struct"*, [8 x %"struct.pov::ot_node_struct"*] } 22%"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 } 23 24define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(%"struct.pov::ot_block_struct"* %new_block) { 25; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE: 26; CHECK-GEN-ISEL-TRUE: # %bb.0: # %entry 27; CHECK-GEN-ISEL-TRUE-NEXT: mflr r0 28; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_def_cfa_offset 64 29; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset lr, 16 30; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r29, -24 31; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r30, -16 32; CHECK-GEN-ISEL-TRUE-NEXT: std r29, -24(r1) # 8-byte Folded Spill 33; CHECK-GEN-ISEL-TRUE-NEXT: std r30, -16(r1) # 8-byte Folded Spill 34; CHECK-GEN-ISEL-TRUE-NEXT: std r0, 16(r1) 35; CHECK-GEN-ISEL-TRUE-NEXT: stdu r1, -64(r1) 36; CHECK-GEN-ISEL-TRUE-NEXT: mr r30, r3 37; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x3 38; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $r29 39; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 4 40; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %while.cond11 41; CHECK-GEN-ISEL-TRUE-NEXT: # 42; CHECK-GEN-ISEL-TRUE-NEXT: lwz r4, 0(r3) 43; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r4, 0 44; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_3 45; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.2: # %while.body21 46; CHECK-GEN-ISEL-TRUE-NEXT: # 47; CHECK-GEN-ISEL-TRUE-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov 48; CHECK-GEN-ISEL-TRUE-NEXT: nop 49; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r29, 1 50; CHECK-GEN-ISEL-TRUE-NEXT: srwi r5, r29, 1 51; CHECK-GEN-ISEL-TRUE-NEXT: srawi r4, r4, 1 52; CHECK-GEN-ISEL-TRUE-NEXT: std r3, 0(r3) 53; CHECK-GEN-ISEL-TRUE-NEXT: addze r4, r4 54; CHECK-GEN-ISEL-TRUE-NEXT: isel r29, r4, r5, 4*cr5+lt 55; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_1 56; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_3: # %lor.rhs 57; CHECK-GEN-ISEL-TRUE-NEXT: std r30, 16(r3) 58; CHECK-GEN-ISEL-TRUE-NEXT: addi r1, r1, 64 59; CHECK-GEN-ISEL-TRUE-NEXT: ld r0, 16(r1) 60; CHECK-GEN-ISEL-TRUE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload 61; CHECK-GEN-ISEL-TRUE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload 62; CHECK-GEN-ISEL-TRUE-NEXT: mtlr r0 63; CHECK-GEN-ISEL-TRUE-NEXT: blr 64; 65; CHECK-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE: 66; CHECK: # %bb.0: # %entry 67; CHECK-NEXT: mflr r0 68; CHECK-NEXT: .cfi_def_cfa_offset 64 69; CHECK-NEXT: .cfi_offset lr, 16 70; CHECK-NEXT: .cfi_offset r29, -24 71; CHECK-NEXT: .cfi_offset r30, -16 72; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill 73; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill 74; CHECK-NEXT: std r0, 16(r1) 75; CHECK-NEXT: stdu r1, -64(r1) 76; CHECK-NEXT: mr r30, r3 77; CHECK-NEXT: # implicit-def: $x3 78; CHECK-NEXT: # implicit-def: $r29 79; CHECK-NEXT: .p2align 4 80; CHECK-NEXT: .LBB0_1: # %while.cond11 81; CHECK-NEXT: # 82; CHECK-NEXT: lwz r4, 0(r3) 83; CHECK-NEXT: cmplwi r4, 0 84; CHECK-NEXT: beq cr0, .LBB0_6 85; CHECK-NEXT: # %bb.2: # %while.body21 86; CHECK-NEXT: # 87; CHECK-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov 88; CHECK-NEXT: nop 89; CHECK-NEXT: addi r4, r29, 1 90; CHECK-NEXT: srwi r5, r29, 1 91; CHECK-NEXT: srawi r4, r4, 1 92; CHECK-NEXT: std r3, 0(r3) 93; CHECK-NEXT: addze r4, r4 94; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_4 95; CHECK-NEXT: # %bb.3: # %while.body21 96; CHECK-NEXT: # 97; CHECK-NEXT: ori r29, r5, 0 98; CHECK-NEXT: b .LBB0_5 99; CHECK-NEXT: .LBB0_4: # %while.body21 100; CHECK-NEXT: # 101; CHECK-NEXT: addi r29, r4, 0 102; CHECK-NEXT: .LBB0_5: # %while.body21 103; CHECK-NEXT: # 104; CHECK-NEXT: b .LBB0_1 105; CHECK-NEXT: .LBB0_6: # %lor.rhs 106; CHECK-NEXT: std r30, 16(r3) 107; CHECK-NEXT: addi r1, r1, 64 108; CHECK-NEXT: ld r0, 16(r1) 109; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload 110; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload 111; CHECK-NEXT: mtlr r0 112; CHECK-NEXT: blr 113entry: 114 br label %while.cond11 115 116while.cond11: 117 %this_node.0250 = phi %"struct.pov::ot_node_struct"* [ undef, %entry ], [ %1, %cond.false21.i156 ], [ %1, %cond.true18.i153 ] 118 %temp_id.sroa.21.1 = phi i32 [ undef, %entry ], [ %shr2039.i152, %cond.true18.i153 ], [ %div24.i155, %cond.false21.i156 ] 119 %0 = load i32, i32* undef, align 4 120 %cmp17 = icmp eq i32 0, %0 121 br i1 %cmp17, label %lor.rhs, label %while.body21 122 123lor.rhs: 124 %Values = getelementptr inbounds %"struct.pov::ot_node_struct", %"struct.pov::ot_node_struct"* %this_node.0250, i64 0, i32 1 125 store %"struct.pov::ot_block_struct"* %new_block, %"struct.pov::ot_block_struct"** %Values, align 8 126 ret void 127 128while.body21: 129 %call.i84 = tail call i8* @ZN3pov10pov_callocEmmPKciS1_pov() 130 store i8* %call.i84, i8** undef, align 8 131 %1 = bitcast i8* %call.i84 to %"struct.pov::ot_node_struct"* 132 br i1 undef, label %cond.true18.i153, label %cond.false21.i156 133 134cond.true18.i153: 135 %shr2039.i152 = lshr i32 %temp_id.sroa.21.1, 1 136 br label %while.cond11 137 138cond.false21.i156: 139 %add23.i154 = add nsw i32 %temp_id.sroa.21.1, 1 140 %div24.i155 = sdiv i32 %add23.i154, 2 141 br label %while.cond11 142} 143 144declare i8* @ZN3pov10pov_callocEmmPKciS1_pov() 145