1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32--     -mcpu=ppc32 | FileCheck %s --check-prefixes=X32
3; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32--     -mcpu=pwr7  | FileCheck %s --check-prefixes=X32,PWR7_32
4; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=ppc64 | FileCheck %s --check-prefixes=X64
5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=pwr7  | FileCheck %s --check-prefixes=PWR7_64
6
7
8define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
9; X32-LABEL: STWBRX:
10; X32:       # %bb.0:
11; X32-NEXT:    stwbrx r3, r4, r5
12; X32-NEXT:    blr
13;
14; X64-LABEL: STWBRX:
15; X64:       # %bb.0:
16; X64-NEXT:    extsw r5, r5
17; X64-NEXT:    stwbrx r3, r4, r5
18; X64-NEXT:    blr
19;
20; PWR7_64-LABEL: STWBRX:
21; PWR7_64:       # %bb.0:
22; PWR7_64-NEXT:    extsw r5, r5
23; PWR7_64-NEXT:    stwbrx r3, r4, r5
24; PWR7_64-NEXT:    blr
25  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
26  %tmp1.upgrd.1 = bitcast i8* %tmp1 to i32*
27  %tmp13 = tail call i32 @llvm.bswap.i32( i32 %i )
28  store i32 %tmp13, i32* %tmp1.upgrd.1
29  ret void
30}
31
32define i32 @LWBRX(i8* %ptr, i32 %off) {
33; X32-LABEL: LWBRX:
34; X32:       # %bb.0:
35; X32-NEXT:    lwbrx r3, r3, r4
36; X32-NEXT:    blr
37;
38; X64-LABEL: LWBRX:
39; X64:       # %bb.0:
40; X64-NEXT:    extsw r4, r4
41; X64-NEXT:    lwbrx r3, r3, r4
42; X64-NEXT:    blr
43;
44; PWR7_64-LABEL: LWBRX:
45; PWR7_64:       # %bb.0:
46; PWR7_64-NEXT:    extsw r4, r4
47; PWR7_64-NEXT:    lwbrx r3, r3, r4
48; PWR7_64-NEXT:    blr
49  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
50  %tmp1.upgrd.2 = bitcast i8* %tmp1 to i32*
51  %tmp = load i32, i32* %tmp1.upgrd.2
52  %tmp14 = tail call i32 @llvm.bswap.i32( i32 %tmp )
53  ret i32 %tmp14
54}
55
56define void @STHBRX(i16 %s, i8* %ptr, i32 %off) {
57; X32-LABEL: STHBRX:
58; X32:       # %bb.0:
59; X32-NEXT:    sthbrx r3, r4, r5
60; X32-NEXT:    blr
61;
62; X64-LABEL: STHBRX:
63; X64:       # %bb.0:
64; X64-NEXT:    extsw r5, r5
65; X64-NEXT:    sthbrx r3, r4, r5
66; X64-NEXT:    blr
67;
68; PWR7_64-LABEL: STHBRX:
69; PWR7_64:       # %bb.0:
70; PWR7_64-NEXT:    extsw r5, r5
71; PWR7_64-NEXT:    sthbrx r3, r4, r5
72; PWR7_64-NEXT:    blr
73  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
74  %tmp1.upgrd.3 = bitcast i8* %tmp1 to i16*
75  %tmp5 = call i16 @llvm.bswap.i16( i16 %s )
76  store i16 %tmp5, i16* %tmp1.upgrd.3
77  ret void
78}
79
80define i16 @LHBRX(i8* %ptr, i32 %off) {
81; X32-LABEL: LHBRX:
82; X32:       # %bb.0:
83; X32-NEXT:    lhbrx r3, r3, r4
84; X32-NEXT:    blr
85;
86; X64-LABEL: LHBRX:
87; X64:       # %bb.0:
88; X64-NEXT:    extsw r4, r4
89; X64-NEXT:    lhbrx r3, r3, r4
90; X64-NEXT:    blr
91;
92; PWR7_64-LABEL: LHBRX:
93; PWR7_64:       # %bb.0:
94; PWR7_64-NEXT:    extsw r4, r4
95; PWR7_64-NEXT:    lhbrx r3, r3, r4
96; PWR7_64-NEXT:    blr
97  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
98  %tmp1.upgrd.4 = bitcast i8* %tmp1 to i16*
99  %tmp = load i16, i16* %tmp1.upgrd.4
100  %tmp6 = call i16 @llvm.bswap.i16( i16 %tmp )
101  ret i16 %tmp6
102}
103
104; TODO: combine the bswap feeding a store on subtargets
105; that do not have an STDBRX.
106define void @STDBRX(i64 %i, i8* %ptr, i64 %off) {
107; PWR7_32-LABEL: STDBRX:
108; PWR7_32:       # %bb.0:
109; PWR7_32-NEXT:    li r6, 4
110; PWR7_32-NEXT:    add r7, r5, r8
111; PWR7_32-NEXT:    stwbrx r4, r5, r8
112; PWR7_32-NEXT:    stwbrx r3, r7, r6
113; PWR7_32-NEXT:    blr
114;
115; X64-LABEL: STDBRX:
116; X64:       # %bb.0:
117; X64-NEXT:    rotldi r6, r3, 16
118; X64-NEXT:    rotldi r7, r3, 8
119; X64-NEXT:    rldimi r7, r6, 8, 48
120; X64-NEXT:    rotldi r6, r3, 24
121; X64-NEXT:    rldimi r7, r6, 16, 40
122; X64-NEXT:    rotldi r6, r3, 32
123; X64-NEXT:    rldimi r7, r6, 24, 32
124; X64-NEXT:    rotldi r6, r3, 48
125; X64-NEXT:    rldimi r7, r6, 40, 16
126; X64-NEXT:    rotldi r6, r3, 56
127; X64-NEXT:    rldimi r7, r6, 48, 8
128; X64-NEXT:    rldimi r7, r3, 56, 0
129; X64-NEXT:    stdx r7, r4, r5
130; X64-NEXT:    blr
131;
132; PWR7_64-LABEL: STDBRX:
133; PWR7_64:       # %bb.0:
134; PWR7_64-NEXT:    stdbrx r3, r4, r5
135; PWR7_64-NEXT:    blr
136  %tmp1 = getelementptr i8, i8* %ptr, i64 %off
137  %tmp1.upgrd.1 = bitcast i8* %tmp1 to i64*
138  %tmp13 = tail call i64 @llvm.bswap.i64( i64 %i )
139  store i64 %tmp13, i64* %tmp1.upgrd.1
140  ret void
141}
142
143define i64 @LDBRX(i8* %ptr, i64 %off) {
144; PWR7_32-LABEL: LDBRX:
145; PWR7_32:       # %bb.0:
146; PWR7_32-NEXT:    li r5, 4
147; PWR7_32-NEXT:    add r7, r3, r6
148; PWR7_32-NEXT:    lwbrx r4, r3, r6
149; PWR7_32-NEXT:    lwbrx r3, r7, r5
150; PWR7_32-NEXT:    blr
151;
152; X64-LABEL: LDBRX:
153; X64:       # %bb.0:
154; X64-NEXT:    li r6, 4
155; X64-NEXT:    lwbrx r5, r3, r4
156; X64-NEXT:    add r3, r3, r4
157; X64-NEXT:    lwbrx r3, r3, r6
158; X64-NEXT:    rldimi r5, r3, 32, 0
159; X64-NEXT:    mr r3, r5
160; X64-NEXT:    blr
161;
162; PWR7_64-LABEL: LDBRX:
163; PWR7_64:       # %bb.0:
164; PWR7_64-NEXT:    ldbrx r3, r3, r4
165; PWR7_64-NEXT:    blr
166  %tmp1 = getelementptr i8, i8* %ptr, i64 %off
167  %tmp1.upgrd.2 = bitcast i8* %tmp1 to i64*
168  %tmp = load i64, i64* %tmp1.upgrd.2
169  %tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp )
170  ret i64 %tmp14
171}
172
173declare i16 @llvm.bswap.i16(i16)
174declare i32 @llvm.bswap.i32(i32)
175declare i64 @llvm.bswap.i64(i64)
176