1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32--     -mcpu=ppc32 | FileCheck %s --check-prefixes=X32
3; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32--     -mcpu=pwr7  | FileCheck %s --check-prefixes=X32,PWR7_32
4; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=ppc64 | FileCheck %s --check-prefixes=X64
5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=pwr7  | FileCheck %s --check-prefixes=PWR7_64
6; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=a2    | FileCheck %s --check-prefixes=A2_64
7
8
9define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
10; X32-LABEL: STWBRX:
11; X32:       # %bb.0:
12; X32-NEXT:    stwbrx r3, r4, r5
13; X32-NEXT:    blr
14;
15; X64-LABEL: STWBRX:
16; X64:       # %bb.0:
17; X64-NEXT:    extsw r5, r5
18; X64-NEXT:    stwbrx r3, r4, r5
19; X64-NEXT:    blr
20;
21; PWR7_64-LABEL: STWBRX:
22; PWR7_64:       # %bb.0:
23; PWR7_64-NEXT:    extsw r5, r5
24; PWR7_64-NEXT:    stwbrx r3, r4, r5
25; PWR7_64-NEXT:    blr
26;
27; A2_64-LABEL: STWBRX:
28; A2_64:       # %bb.0:
29; A2_64-NEXT:    extsw r5, r5
30; A2_64-NEXT:    stwbrx r3, r4, r5
31; A2_64-NEXT:    blr
32  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
33  %tmp1.upgrd.1 = bitcast i8* %tmp1 to i32*
34  %tmp13 = tail call i32 @llvm.bswap.i32( i32 %i )
35  store i32 %tmp13, i32* %tmp1.upgrd.1
36  ret void
37}
38
39define i32 @LWBRX(i8* %ptr, i32 %off) {
40; X32-LABEL: LWBRX:
41; X32:       # %bb.0:
42; X32-NEXT:    lwbrx r3, r3, r4
43; X32-NEXT:    blr
44;
45; X64-LABEL: LWBRX:
46; X64:       # %bb.0:
47; X64-NEXT:    extsw r4, r4
48; X64-NEXT:    lwbrx r3, r3, r4
49; X64-NEXT:    blr
50;
51; PWR7_64-LABEL: LWBRX:
52; PWR7_64:       # %bb.0:
53; PWR7_64-NEXT:    extsw r4, r4
54; PWR7_64-NEXT:    lwbrx r3, r3, r4
55; PWR7_64-NEXT:    blr
56;
57; A2_64-LABEL: LWBRX:
58; A2_64:       # %bb.0:
59; A2_64-NEXT:    extsw r4, r4
60; A2_64-NEXT:    lwbrx r3, r3, r4
61; A2_64-NEXT:    blr
62  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
63  %tmp1.upgrd.2 = bitcast i8* %tmp1 to i32*
64  %tmp = load i32, i32* %tmp1.upgrd.2
65  %tmp14 = tail call i32 @llvm.bswap.i32( i32 %tmp )
66  ret i32 %tmp14
67}
68
69define void @STHBRX(i16 %s, i8* %ptr, i32 %off) {
70; X32-LABEL: STHBRX:
71; X32:       # %bb.0:
72; X32-NEXT:    sthbrx r3, r4, r5
73; X32-NEXT:    blr
74;
75; X64-LABEL: STHBRX:
76; X64:       # %bb.0:
77; X64-NEXT:    extsw r5, r5
78; X64-NEXT:    sthbrx r3, r4, r5
79; X64-NEXT:    blr
80;
81; PWR7_64-LABEL: STHBRX:
82; PWR7_64:       # %bb.0:
83; PWR7_64-NEXT:    extsw r5, r5
84; PWR7_64-NEXT:    sthbrx r3, r4, r5
85; PWR7_64-NEXT:    blr
86;
87; A2_64-LABEL: STHBRX:
88; A2_64:       # %bb.0:
89; A2_64-NEXT:    extsw r5, r5
90; A2_64-NEXT:    sthbrx r3, r4, r5
91; A2_64-NEXT:    blr
92  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
93  %tmp1.upgrd.3 = bitcast i8* %tmp1 to i16*
94  %tmp5 = call i16 @llvm.bswap.i16( i16 %s )
95  store i16 %tmp5, i16* %tmp1.upgrd.3
96  ret void
97}
98
99define i16 @LHBRX(i8* %ptr, i32 %off) {
100; X32-LABEL: LHBRX:
101; X32:       # %bb.0:
102; X32-NEXT:    lhbrx r3, r3, r4
103; X32-NEXT:    blr
104;
105; X64-LABEL: LHBRX:
106; X64:       # %bb.0:
107; X64-NEXT:    extsw r4, r4
108; X64-NEXT:    lhbrx r3, r3, r4
109; X64-NEXT:    blr
110;
111; PWR7_64-LABEL: LHBRX:
112; PWR7_64:       # %bb.0:
113; PWR7_64-NEXT:    extsw r4, r4
114; PWR7_64-NEXT:    lhbrx r3, r3, r4
115; PWR7_64-NEXT:    blr
116;
117; A2_64-LABEL: LHBRX:
118; A2_64:       # %bb.0:
119; A2_64-NEXT:    extsw r4, r4
120; A2_64-NEXT:    lhbrx r3, r3, r4
121; A2_64-NEXT:    blr
122  %tmp1 = getelementptr i8, i8* %ptr, i32 %off
123  %tmp1.upgrd.4 = bitcast i8* %tmp1 to i16*
124  %tmp = load i16, i16* %tmp1.upgrd.4
125  %tmp6 = call i16 @llvm.bswap.i16( i16 %tmp )
126  ret i16 %tmp6
127}
128
129; TODO: combine the bswap feeding a store on subtargets
130; that do not have an STDBRX.
131define void @STDBRX(i64 %i, i8* %ptr, i64 %off) {
132; PWR7_32-LABEL: STDBRX:
133; PWR7_32:       # %bb.0:
134; PWR7_32-NEXT:    li r6, 4
135; PWR7_32-NEXT:    add r7, r5, r8
136; PWR7_32-NEXT:    stwbrx r4, r5, r8
137; PWR7_32-NEXT:    stwbrx r3, r7, r6
138; PWR7_32-NEXT:    blr
139;
140; X64-LABEL: STDBRX:
141; X64:       # %bb.0:
142; X64-NEXT:    rotldi r6, r3, 16
143; X64-NEXT:    rotldi r7, r3, 8
144; X64-NEXT:    rldimi r7, r6, 8, 48
145; X64-NEXT:    rotldi r6, r3, 24
146; X64-NEXT:    rldimi r7, r6, 16, 40
147; X64-NEXT:    rotldi r6, r3, 32
148; X64-NEXT:    rldimi r7, r6, 24, 32
149; X64-NEXT:    rotldi r6, r3, 48
150; X64-NEXT:    rldimi r7, r6, 40, 16
151; X64-NEXT:    rotldi r6, r3, 56
152; X64-NEXT:    rldimi r7, r6, 48, 8
153; X64-NEXT:    rldimi r7, r3, 56, 0
154; X64-NEXT:    stdx r7, r4, r5
155; X64-NEXT:    blr
156;
157; PWR7_64-LABEL: STDBRX:
158; PWR7_64:       # %bb.0:
159; PWR7_64-NEXT:    stdbrx r3, r4, r5
160; PWR7_64-NEXT:    blr
161;
162; A2_64-LABEL: STDBRX:
163; A2_64:       # %bb.0:
164; A2_64-NEXT:    stdbrx r3, r4, r5
165; A2_64-NEXT:    blr
166  %tmp1 = getelementptr i8, i8* %ptr, i64 %off
167  %tmp1.upgrd.1 = bitcast i8* %tmp1 to i64*
168  %tmp13 = tail call i64 @llvm.bswap.i64( i64 %i )
169  store i64 %tmp13, i64* %tmp1.upgrd.1
170  ret void
171}
172
173define i64 @LDBRX(i8* %ptr, i64 %off) {
174; PWR7_32-LABEL: LDBRX:
175; PWR7_32:       # %bb.0:
176; PWR7_32-NEXT:    li r5, 4
177; PWR7_32-NEXT:    add r7, r3, r6
178; PWR7_32-NEXT:    lwbrx r4, r3, r6
179; PWR7_32-NEXT:    lwbrx r3, r7, r5
180; PWR7_32-NEXT:    blr
181;
182; X64-LABEL: LDBRX:
183; X64:       # %bb.0:
184; X64-NEXT:    li r6, 4
185; X64-NEXT:    lwbrx r5, r3, r4
186; X64-NEXT:    add r3, r3, r4
187; X64-NEXT:    lwbrx r3, r3, r6
188; X64-NEXT:    rldimi r5, r3, 32, 0
189; X64-NEXT:    mr r3, r5
190; X64-NEXT:    blr
191;
192; PWR7_64-LABEL: LDBRX:
193; PWR7_64:       # %bb.0:
194; PWR7_64-NEXT:    ldbrx r3, r3, r4
195; PWR7_64-NEXT:    blr
196;
197; A2_64-LABEL: LDBRX:
198; A2_64:       # %bb.0:
199; A2_64-NEXT:    ldbrx r3, r3, r4
200; A2_64-NEXT:    blr
201  %tmp1 = getelementptr i8, i8* %ptr, i64 %off
202  %tmp1.upgrd.2 = bitcast i8* %tmp1 to i64*
203  %tmp = load i64, i64* %tmp1.upgrd.2
204  %tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp )
205  ret i64 %tmp14
206}
207
208declare i16 @llvm.bswap.i16(i16)
209declare i32 @llvm.bswap.i32(i32)
210declare i64 @llvm.bswap.i64(i64)
211