1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
3; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10
5; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10
6
7; Byte indexed
8
9define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) {
10; CHECK-64-LABEL: testByte:
11; CHECK-64:       # %bb.0: # %entry
12; CHECK-64-NEXT:    addi 5, 1, -16
13; CHECK-64-NEXT:    clrldi 4, 4, 60
14; CHECK-64-NEXT:    stxv 34, -16(1)
15; CHECK-64-NEXT:    stbx 3, 5, 4
16; CHECK-64-NEXT:    lxv 34, -16(1)
17; CHECK-64-NEXT:    blr
18;
19; CHECK-32-LABEL: testByte:
20; CHECK-32:       # %bb.0: # %entry
21; CHECK-32-NEXT:    addi 5, 1, -16
22; CHECK-32-NEXT:    clrlwi 3, 6, 28
23; CHECK-32-NEXT:    stxv 34, -16(1)
24; CHECK-32-NEXT:    stbx 4, 5, 3
25; CHECK-32-NEXT:    lxv 34, -16(1)
26; CHECK-32-NEXT:    blr
27;
28; CHECK-64-P10-LABEL: testByte:
29; CHECK-64-P10:       # %bb.0: # %entry
30; CHECK-64-P10-NEXT:    vinsblx 2, 4, 3
31; CHECK-64-P10-NEXT:    blr
32;
33; CHECK-32-P10-LABEL: testByte:
34; CHECK-32-P10:       # %bb.0: # %entry
35; CHECK-32-P10-NEXT:    vinsblx 2, 6, 4
36; CHECK-32-P10-NEXT:    blr
37entry:
38  %conv = trunc i64 %b to i8
39  %vecins = insertelement <16 x i8> %a, i8 %conv, i64 %idx
40  ret <16 x i8> %vecins
41}
42
43; Halfword indexed
44
45define <8 x i16> @testHalf(<8 x i16> %a, i64 %b, i64 %idx) {
46; CHECK-64-LABEL: testHalf:
47; CHECK-64:       # %bb.0: # %entry
48; CHECK-64-NEXT:    addi 5, 1, -16
49; CHECK-64-NEXT:    rlwinm 4, 4, 1, 28, 30
50; CHECK-64-NEXT:    stxv 34, -16(1)
51; CHECK-64-NEXT:    sthx 3, 5, 4
52; CHECK-64-NEXT:    lxv 34, -16(1)
53; CHECK-64-NEXT:    blr
54;
55; CHECK-32-LABEL: testHalf:
56; CHECK-32:       # %bb.0: # %entry
57; CHECK-32-NEXT:    addi 5, 1, -16
58; CHECK-32-NEXT:    rlwinm 3, 6, 1, 28, 30
59; CHECK-32-NEXT:    stxv 34, -16(1)
60; CHECK-32-NEXT:    sthx 4, 5, 3
61; CHECK-32-NEXT:    lxv 34, -16(1)
62; CHECK-32-NEXT:    blr
63;
64; CHECK-64-P10-LABEL: testHalf:
65; CHECK-64-P10:       # %bb.0: # %entry
66; CHECK-64-P10-NEXT:    slwi 4, 4, 1
67; CHECK-64-P10-NEXT:    vinshlx 2, 4, 3
68; CHECK-64-P10-NEXT:    blr
69;
70; CHECK-32-P10-LABEL: testHalf:
71; CHECK-32-P10:       # %bb.0: # %entry
72; CHECK-32-P10-NEXT:    vinshlx 2, 6, 4
73; CHECK-32-P10-NEXT:    blr
74entry:
75  %conv = trunc i64 %b to i16
76  %vecins = insertelement <8 x i16> %a, i16 %conv, i64 %idx
77  ret <8 x i16> %vecins
78}
79
80; Word indexed
81
82define <4 x i32> @testWord(<4 x i32> %a, i64 %b, i64 %idx) {
83; CHECK-64-LABEL: testWord:
84; CHECK-64:       # %bb.0: # %entry
85; CHECK-64-NEXT:    addi 5, 1, -16
86; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
87; CHECK-64-NEXT:    stxv 34, -16(1)
88; CHECK-64-NEXT:    stwx 3, 5, 4
89; CHECK-64-NEXT:    lxv 34, -16(1)
90; CHECK-64-NEXT:    blr
91;
92; CHECK-32-LABEL: testWord:
93; CHECK-32:       # %bb.0: # %entry
94; CHECK-32-NEXT:    addi 5, 1, -16
95; CHECK-32-NEXT:    rlwinm 3, 6, 2, 28, 29
96; CHECK-32-NEXT:    stxv 34, -16(1)
97; CHECK-32-NEXT:    stwx 4, 5, 3
98; CHECK-32-NEXT:    lxv 34, -16(1)
99; CHECK-32-NEXT:    blr
100;
101; CHECK-64-P10-LABEL: testWord:
102; CHECK-64-P10:       # %bb.0: # %entry
103; CHECK-64-P10-NEXT:    slwi 4, 4, 2
104; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
105; CHECK-64-P10-NEXT:    blr
106;
107; CHECK-32-P10-LABEL: testWord:
108; CHECK-32-P10:       # %bb.0: # %entry
109; CHECK-32-P10-NEXT:    vinswlx 2, 6, 4
110; CHECK-32-P10-NEXT:    blr
111entry:
112  %conv = trunc i64 %b to i32
113  %vecins = insertelement <4 x i32> %a, i32 %conv, i64 %idx
114  ret <4 x i32> %vecins
115}
116
117; Word immediate
118
119define <4 x i32> @testWordImm(<4 x i32> %a, i64 %b) {
120; CHECK-64-LABEL: testWordImm:
121; CHECK-64:       # %bb.0: # %entry
122; CHECK-64-NEXT:    mtfprwz 0, 3
123; CHECK-64-NEXT:    xxinsertw 34, 0, 4
124; CHECK-64-NEXT:    xxinsertw 34, 0, 12
125; CHECK-64-NEXT:    blr
126;
127; CHECK-32-LABEL: testWordImm:
128; CHECK-32:       # %bb.0: # %entry
129; CHECK-32-NEXT:    mtfprwz 0, 4
130; CHECK-32-NEXT:    xxinsertw 34, 0, 4
131; CHECK-32-NEXT:    xxinsertw 34, 0, 12
132; CHECK-32-NEXT:    blr
133;
134; CHECK-64-P10-LABEL: testWordImm:
135; CHECK-64-P10:       # %bb.0: # %entry
136; CHECK-64-P10-NEXT:    vinsw 2, 3, 4
137; CHECK-64-P10-NEXT:    vinsw 2, 3, 12
138; CHECK-64-P10-NEXT:    blr
139;
140; CHECK-32-P10-LABEL: testWordImm:
141; CHECK-32-P10:       # %bb.0: # %entry
142; CHECK-32-P10-NEXT:    vinsw 2, 4, 4
143; CHECK-32-P10-NEXT:    vinsw 2, 4, 12
144; CHECK-32-P10-NEXT:    blr
145entry:
146  %conv = trunc i64 %b to i32
147  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 1
148  %vecins2 = insertelement <4 x i32> %vecins, i32 %conv, i32 3
149  ret <4 x i32> %vecins2
150}
151
152; Doubleword indexed
153
154define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
155; CHECK-64-LABEL: testDoubleword:
156; CHECK-64:       # %bb.0: # %entry
157; CHECK-64-NEXT:    addi 5, 1, -16
158; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
159; CHECK-64-NEXT:    stxv 34, -16(1)
160; CHECK-64-NEXT:    stdx 3, 5, 4
161; CHECK-64-NEXT:    lxv 34, -16(1)
162; CHECK-64-NEXT:    blr
163;
164; CHECK-32-LABEL: testDoubleword:
165; CHECK-32:       # %bb.0: # %entry
166; CHECK-32-NEXT:    add 5, 6, 6
167; CHECK-32-NEXT:    addi 7, 1, -32
168; CHECK-32-NEXT:    stxv 34, -32(1)
169; CHECK-32-NEXT:    rlwinm 6, 5, 2, 28, 29
170; CHECK-32-NEXT:    stwx 3, 7, 6
171; CHECK-32-NEXT:    addi 3, 5, 1
172; CHECK-32-NEXT:    addi 5, 1, -16
173; CHECK-32-NEXT:    lxv 0, -32(1)
174; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
175; CHECK-32-NEXT:    stxv 0, -16(1)
176; CHECK-32-NEXT:    stwx 4, 5, 3
177; CHECK-32-NEXT:    lxv 34, -16(1)
178; CHECK-32-NEXT:    blr
179;
180; CHECK-64-P10-LABEL: testDoubleword:
181; CHECK-64-P10:       # %bb.0: # %entry
182; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
183; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
184; CHECK-64-P10-NEXT:    blr
185;
186; CHECK-32-P10-LABEL: testDoubleword:
187; CHECK-32-P10:       # %bb.0: # %entry
188; CHECK-32-P10-NEXT:    add 5, 6, 6
189; CHECK-32-P10-NEXT:    vinswlx 2, 5, 3
190; CHECK-32-P10-NEXT:    addi 3, 5, 1
191; CHECK-32-P10-NEXT:    vinswlx 2, 3, 4
192; CHECK-32-P10-NEXT:    blr
193entry:
194  %vecins = insertelement <2 x i64> %a, i64 %b, i64 %idx
195  ret <2 x i64> %vecins
196}
197
198; Doubleword immediate
199
200define <2 x i64> @testDoublewordImm(<2 x i64> %a, i64 %b) {
201; CHECK-64-LABEL: testDoublewordImm:
202; CHECK-64:       # %bb.0: # %entry
203; CHECK-64-NEXT:    mtfprd 0, 3
204; CHECK-64-NEXT:    xxmrghd 34, 34, 0
205; CHECK-64-NEXT:    blr
206;
207; CHECK-32-LABEL: testDoublewordImm:
208; CHECK-32:       # %bb.0: # %entry
209; CHECK-32-NEXT:    mtfprwz 0, 3
210; CHECK-32-NEXT:    xxinsertw 34, 0, 8
211; CHECK-32-NEXT:    mtfprwz 0, 4
212; CHECK-32-NEXT:    xxinsertw 34, 0, 12
213; CHECK-32-NEXT:    blr
214;
215; CHECK-64-P10-LABEL: testDoublewordImm:
216; CHECK-64-P10:       # %bb.0: # %entry
217; CHECK-64-P10-NEXT:    vinsd 2, 3, 8
218; CHECK-64-P10-NEXT:    blr
219;
220; CHECK-32-P10-LABEL: testDoublewordImm:
221; CHECK-32-P10:       # %bb.0: # %entry
222; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
223; CHECK-32-P10-NEXT:    vinsw 2, 4, 12
224; CHECK-32-P10-NEXT:    blr
225entry:
226  %vecins = insertelement <2 x i64> %a, i64 %b, i32 1
227  ret <2 x i64> %vecins
228}
229
230define <2 x i64> @testDoublewordImm2(<2 x i64> %a, i64 %b) {
231; CHECK-64-LABEL: testDoublewordImm2:
232; CHECK-64:       # %bb.0: # %entry
233; CHECK-64-NEXT:    mtfprd 0, 3
234; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
235; CHECK-64-NEXT:    blr
236;
237; CHECK-32-LABEL: testDoublewordImm2:
238; CHECK-32:       # %bb.0: # %entry
239; CHECK-32-NEXT:    mtfprwz 0, 3
240; CHECK-32-NEXT:    xxinsertw 34, 0, 0
241; CHECK-32-NEXT:    mtfprwz 0, 4
242; CHECK-32-NEXT:    xxinsertw 34, 0, 4
243; CHECK-32-NEXT:    blr
244;
245; CHECK-64-P10-LABEL: testDoublewordImm2:
246; CHECK-64-P10:       # %bb.0: # %entry
247; CHECK-64-P10-NEXT:    vinsd 2, 3, 0
248; CHECK-64-P10-NEXT:    blr
249;
250; CHECK-32-P10-LABEL: testDoublewordImm2:
251; CHECK-32-P10:       # %bb.0: # %entry
252; CHECK-32-P10-NEXT:    vinsw 2, 3, 0
253; CHECK-32-P10-NEXT:    vinsw 2, 4, 4
254; CHECK-32-P10-NEXT:    blr
255entry:
256  %vecins = insertelement <2 x i64> %a, i64 %b, i32 0
257  ret <2 x i64> %vecins
258}
259
260; Float indexed
261
262define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
263; CHECK-64-LABEL: testFloat1:
264; CHECK-64:       # %bb.0: # %entry
265; CHECK-64-DAG:     rlwinm 3, 4, 2, 28, 29
266; CHECK-64-DAG:     addi 4, 1, -16
267; CHECK-64-NEXT:    stxv 34, -16(1)
268; CHECK-64-NEXT:    stfsx 1, 4, 3
269; CHECK-64-NEXT:    lxv 34, -16(1)
270; CHECK-64-NEXT:    blr
271;
272; CHECK-32-LABEL: testFloat1:
273; CHECK-32:       # %bb.0: # %entry
274; CHECK-32-NEXT:    rlwinm 3, 4, 2, 28, 29
275; CHECK-32-NEXT:    addi 4, 1, -16
276; CHECK-32-NEXT:    stxv 34, -16(1)
277; CHECK-32-NEXT:    stfsx 1, 4, 3
278; CHECK-32-NEXT:    lxv 34, -16(1)
279; CHECK-32-NEXT:    blr
280;
281; CHECK-64-P10-LABEL: testFloat1:
282; CHECK-64-P10:       # %bb.0: # %entry
283; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
284; CHECK-64-P10-NEXT:    extsw 4, 4
285; CHECK-64-P10-NEXT:    slwi 4, 4, 2
286; CHECK-64-P10-NEXT:    mffprwz 3, 0
287; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
288; CHECK-64-P10-NEXT:    blr
289;
290; CHECK-32-P10-LABEL: testFloat1:
291; CHECK-32-P10:       # %bb.0: # %entry
292; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
293; CHECK-32-P10-NEXT:    mffprwz 3, 0
294; CHECK-32-P10-NEXT:    vinswlx 2, 4, 3
295; CHECK-32-P10-NEXT:    blr
296entry:
297  %vecins = insertelement <4 x float> %a, float %b, i32 %idx1
298  ret <4 x float> %vecins
299}
300
301define <4 x float> @testFloat2(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
302; CHECK-64-LABEL: testFloat2:
303; CHECK-64:       # %bb.0: # %entry
304; CHECK-64-NEXT:    lwz 6, 0(3)
305; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
306; CHECK-64-DAG:     addi 7, 1, -32
307; CHECK-64-NEXT:    stxv 34, -32(1)
308; CHECK-64-NEXT:    stwx 6, 7, 4
309; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
310; CHECK-64-NEXT:    addi 5, 1, -16
311; CHECK-64-NEXT:    lxv 0, -32(1)
312; CHECK-64-NEXT:    lwz 3, 1(3)
313; CHECK-64-NEXT:    stxv 0, -16(1)
314; CHECK-64-NEXT:    stwx 3, 5, 4
315; CHECK-64-NEXT:    lxv 34, -16(1)
316; CHECK-64-NEXT:    blr
317;
318; CHECK-32-LABEL: testFloat2:
319; CHECK-32:       # %bb.0: # %entry
320; CHECK-32-NEXT:    lwz 6, 0(3)
321; CHECK-32-NEXT:    addi 7, 1, -32
322; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
323; CHECK-32-NEXT:    stxv 34, -32(1)
324; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
325; CHECK-32-NEXT:    stwx 6, 7, 4
326; CHECK-32-NEXT:    addi 4, 1, -16
327; CHECK-32-NEXT:    lxv 0, -32(1)
328; CHECK-32-NEXT:    lwz 3, 1(3)
329; CHECK-32-NEXT:    stxv 0, -16(1)
330; CHECK-32-NEXT:    stwx 3, 4, 5
331; CHECK-32-NEXT:    lxv 34, -16(1)
332; CHECK-32-NEXT:    blr
333;
334; CHECK-64-P10-LABEL: testFloat2:
335; CHECK-64-P10:       # %bb.0: # %entry
336; CHECK-64-P10-NEXT:    lwz 6, 0(3)
337; CHECK-64-P10-NEXT:    extsw 4, 4
338; CHECK-64-P10-NEXT:    lwz 3, 1(3)
339; CHECK-64-P10-NEXT:    slwi 4, 4, 2
340; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
341; CHECK-64-P10-NEXT:    extsw 4, 5
342; CHECK-64-P10-NEXT:    slwi 4, 4, 2
343; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
344; CHECK-64-P10-NEXT:    blr
345;
346; CHECK-32-P10-LABEL: testFloat2:
347; CHECK-32-P10:       # %bb.0: # %entry
348; CHECK-32-P10-NEXT:    lwz 6, 0(3)
349; CHECK-32-P10-NEXT:    lwz 3, 1(3)
350; CHECK-32-P10-NEXT:    vinswlx 2, 4, 6
351; CHECK-32-P10-NEXT:    vinswlx 2, 5, 3
352; CHECK-32-P10-NEXT:    blr
353entry:
354  %0 = bitcast i8* %b to float*
355  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
356  %1 = bitcast i8* %add.ptr1 to float*
357  %2 = load float, float* %0, align 4
358  %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
359  %3 = load float, float* %1, align 4
360  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
361  ret <4 x float> %vecins2
362}
363
364define <4 x float> @testFloat3(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
365; CHECK-64-LABEL: testFloat3:
366; CHECK-64:       # %bb.0: # %entry
367; CHECK-64-NEXT:    lis 6, 1
368; CHECK-64-DAG:         rlwinm 4, 4, 2, 28, 29
369; CHECK-64-DAG:    addi 7, 1, -32
370; CHECK-64-NEXT:    lwzx 6, 3, 6
371; CHECK-64-NEXT:    stxv 34, -32(1)
372; CHECK-64-NEXT:    stwx 6, 7, 4
373; CHECK-64-NEXT:    li 4, 1
374; CHECK-64-NEXT:    lxv 0, -32(1)
375; CHECK-64-NEXT:    rldic 4, 4, 36, 27
376; CHECK-64-NEXT:    lwzx 3, 3, 4
377; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
378; CHECK-64-NEXT:    addi 5, 1, -16
379; CHECK-64-NEXT:    stxv 0, -16(1)
380; CHECK-64-NEXT:    stwx 3, 5, 4
381; CHECK-64-NEXT:    lxv 34, -16(1)
382; CHECK-64-NEXT:    blr
383;
384; CHECK-32-LABEL: testFloat3:
385; CHECK-32:       # %bb.0: # %entry
386; CHECK-32-NEXT:    lis 6, 1
387; CHECK-32-NEXT:    addi 7, 1, -32
388; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
389; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
390; CHECK-32-NEXT:    lwzx 6, 3, 6
391; CHECK-32-NEXT:    stxv 34, -32(1)
392; CHECK-32-NEXT:    stwx 6, 7, 4
393; CHECK-32-NEXT:    addi 4, 1, -16
394; CHECK-32-NEXT:    lxv 0, -32(1)
395; CHECK-32-NEXT:    lwz 3, 0(3)
396; CHECK-32-NEXT:    stxv 0, -16(1)
397; CHECK-32-NEXT:    stwx 3, 4, 5
398; CHECK-32-NEXT:    lxv 34, -16(1)
399; CHECK-32-NEXT:    blr
400;
401; CHECK-64-P10-LABEL: testFloat3:
402; CHECK-64-P10:       # %bb.0: # %entry
403; CHECK-64-P10-NEXT:    plwz 6, 65536(3), 0
404; CHECK-64-P10-NEXT:    extsw 4, 4
405; CHECK-64-P10-NEXT:    slwi 4, 4, 2
406; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
407; CHECK-64-P10-NEXT:    li 4, 1
408; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
409; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
410; CHECK-64-P10-NEXT:    extsw 4, 5
411; CHECK-64-P10-NEXT:    slwi 4, 4, 2
412; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
413; CHECK-64-P10-NEXT:    blr
414;
415; CHECK-32-P10-LABEL: testFloat3:
416; CHECK-32-P10:       # %bb.0: # %entry
417; CHECK-32-P10-NEXT:    lis 6, 1
418; CHECK-32-P10-NEXT:    lwzx 6, 3, 6
419; CHECK-32-P10-NEXT:    lwz 3, 0(3)
420; CHECK-32-P10-NEXT:    vinswlx 2, 4, 6
421; CHECK-32-P10-NEXT:    vinswlx 2, 5, 3
422; CHECK-32-P10-NEXT:    blr
423entry:
424  %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
425  %0 = bitcast i8* %add.ptr to float*
426  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
427  %1 = bitcast i8* %add.ptr1 to float*
428  %2 = load float, float* %0, align 4
429  %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
430  %3 = load float, float* %1, align 4
431  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
432  ret <4 x float> %vecins2
433}
434
435; Float immediate
436
437define <4 x float> @testFloatImm1(<4 x float> %a, float %b) {
438; CHECK-64-LABEL: testFloatImm1:
439; CHECK-64:       # %bb.0: # %entry
440; CHECK-64-NEXT:    xscvdpspn 0, 1
441; CHECK-64-NEXT:    xxinsertw 34, 0, 0
442; CHECK-64-NEXT:    xxinsertw 34, 0, 8
443; CHECK-64-NEXT:    blr
444;
445; CHECK-32-LABEL: testFloatImm1:
446; CHECK-32:       # %bb.0: # %entry
447; CHECK-32-NEXT:    xscvdpspn 0, 1
448; CHECK-32-NEXT:    xxinsertw 34, 0, 0
449; CHECK-32-NEXT:    xxinsertw 34, 0, 8
450; CHECK-32-NEXT:    blr
451;
452; CHECK-64-P10-LABEL: testFloatImm1:
453; CHECK-64-P10:       # %bb.0: # %entry
454; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
455; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 0
456; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 8
457; CHECK-64-P10-NEXT:    blr
458;
459; CHECK-32-P10-LABEL: testFloatImm1:
460; CHECK-32-P10:       # %bb.0: # %entry
461; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
462; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
463; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
464; CHECK-32-P10-NEXT:    blr
465entry:
466  %vecins = insertelement <4 x float> %a, float %b, i32 0
467  %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2
468  ret <4 x float> %vecins1
469}
470
471define <4 x float> @testFloatImm2(<4 x float> %a, i32* %b) {
472; CHECK-64-LABEL: testFloatImm2:
473; CHECK-64:       # %bb.0: # %entry
474; CHECK-64-NEXT:    lfs 0, 0(3)
475; CHECK-64-NEXT:    xscvdpspn 0, 0
476; CHECK-64-NEXT:    xxinsertw 34, 0, 0
477; CHECK-64-NEXT:    lfs 0, 4(3)
478; CHECK-64-NEXT:    xscvdpspn 0, 0
479; CHECK-64-NEXT:    xxinsertw 34, 0, 8
480; CHECK-64-NEXT:    blr
481;
482; CHECK-32-LABEL: testFloatImm2:
483; CHECK-32:       # %bb.0: # %entry
484; CHECK-32-NEXT:    lfs 0, 0(3)
485; CHECK-32-NEXT:    xscvdpspn 0, 0
486; CHECK-32-NEXT:    xxinsertw 34, 0, 0
487; CHECK-32-NEXT:    lfs 0, 4(3)
488; CHECK-32-NEXT:    xscvdpspn 0, 0
489; CHECK-32-NEXT:    xxinsertw 34, 0, 8
490; CHECK-32-NEXT:    blr
491;
492; CHECK-64-P10-LABEL: testFloatImm2:
493; CHECK-64-P10:       # %bb.0: # %entry
494; CHECK-64-P10-NEXT:    lwz 4, 0(3)
495; CHECK-64-P10-NEXT:    lwz 3, 4(3)
496; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
497; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
498; CHECK-64-P10-NEXT:    blr
499;
500; CHECK-32-P10-LABEL: testFloatImm2:
501; CHECK-32-P10:       # %bb.0: # %entry
502; CHECK-32-P10-NEXT:    lwz 4, 0(3)
503; CHECK-32-P10-NEXT:    lwz 3, 4(3)
504; CHECK-32-P10-NEXT:    vinsw 2, 4, 0
505; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
506; CHECK-32-P10-NEXT:    blr
507entry:
508  %0 = bitcast i32* %b to float*
509  %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 1
510  %1 = bitcast i32* %add.ptr1 to float*
511  %2 = load float, float* %0, align 4
512  %vecins = insertelement <4 x float> %a, float %2, i32 0
513  %3 = load float, float* %1, align 4
514  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2
515  ret <4 x float> %vecins2
516}
517
518define <4 x float> @testFloatImm3(<4 x float> %a, i32* %b) {
519; CHECK-64-LABEL: testFloatImm3:
520; CHECK-64:       # %bb.0: # %entry
521; CHECK-64-NEXT:    lis 4, 4
522; CHECK-64-NEXT:    lfsx 0, 3, 4
523; CHECK-64-NEXT:    li 4, 1
524; CHECK-64-NEXT:    rldic 4, 4, 38, 25
525; CHECK-64-NEXT:    xscvdpspn 0, 0
526; CHECK-64-NEXT:    xxinsertw 34, 0, 0
527; CHECK-64-NEXT:    lfsx 0, 3, 4
528; CHECK-64-NEXT:    xscvdpspn 0, 0
529; CHECK-64-NEXT:    xxinsertw 34, 0, 8
530; CHECK-64-NEXT:    blr
531;
532; CHECK-32-LABEL: testFloatImm3:
533; CHECK-32:       # %bb.0: # %entry
534; CHECK-32-NEXT:    lis 4, 4
535; CHECK-32-NEXT:    lfsx 0, 3, 4
536; CHECK-32-NEXT:    xscvdpspn 0, 0
537; CHECK-32-NEXT:    xxinsertw 34, 0, 0
538; CHECK-32-NEXT:    lfs 0, 0(3)
539; CHECK-32-NEXT:    xscvdpspn 0, 0
540; CHECK-32-NEXT:    xxinsertw 34, 0, 8
541; CHECK-32-NEXT:    blr
542;
543; CHECK-64-P10-LABEL: testFloatImm3:
544; CHECK-64-P10:       # %bb.0: # %entry
545; CHECK-64-P10-NEXT:    plwz 4, 262144(3), 0
546; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
547; CHECK-64-P10-NEXT:    li 4, 1
548; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
549; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
550; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
551; CHECK-64-P10-NEXT:    blr
552;
553; CHECK-32-P10-LABEL: testFloatImm3:
554; CHECK-32-P10:       # %bb.0: # %entry
555; CHECK-32-P10-NEXT:    lis 4, 4
556; CHECK-32-P10-NEXT:    lwzx 4, 3, 4
557; CHECK-32-P10-NEXT:    lwz 3, 0(3)
558; CHECK-32-P10-NEXT:    vinsw 2, 4, 0
559; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
560; CHECK-32-P10-NEXT:    blr
561entry:
562  %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
563  %0 = bitcast i32* %add.ptr to float*
564  %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736
565  %1 = bitcast i32* %add.ptr1 to float*
566  %2 = load float, float* %0, align 4
567  %vecins = insertelement <4 x float> %a, float %2, i32 0
568  %3 = load float, float* %1, align 4
569  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2
570  ret <4 x float> %vecins2
571}
572
573; Double indexed
574
575define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) {
576; CHECK-64-LABEL: testDouble1:
577; CHECK-64:       # %bb.0: # %entry
578; CHECK-64:         rlwinm 3, 4, 3, 28, 28
579; CHECK-64-NEXT:    addi 4, 1, -16
580; CHECK-64-NEXT:    stxv 34, -16(1)
581; CHECK-64-NEXT:    stfdx 1, 4, 3
582; CHECK-64-NEXT:    lxv 34, -16(1)
583; CHECK-64-NEXT:    blr
584;
585; CHECK-32-LABEL: testDouble1:
586; CHECK-32:       # %bb.0: # %entry
587; CHECK-32-NEXT:    addi 4, 1, -16
588; CHECK-32-NEXT:    rlwinm 3, 5, 3, 28, 28
589; CHECK-32-NEXT:    stxv 34, -16(1)
590; CHECK-32-NEXT:    stfdx 1, 4, 3
591; CHECK-32-NEXT:    lxv 34, -16(1)
592; CHECK-32-NEXT:    blr
593;
594; CHECK-64-P10-LABEL: testDouble1:
595; CHECK-64-P10:       # %bb.0: # %entry
596; CHECK-64-P10-NEXT:    extsw 4, 4
597; CHECK-64-P10-NEXT:    mffprd 3, 1
598; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
599; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
600; CHECK-64-P10-NEXT:    blr
601;
602; CHECK-32-P10-LABEL: testDouble1:
603; CHECK-32-P10:       # %bb.0: # %entry
604; CHECK-32-P10-DAG:     addi 4, 1, -16
605; CHECK-32-P10-DAG:     rlwinm 3, 5, 3, 28, 28
606; CHECK-32-P10-NEXT:    stxv 34, -16(1)
607; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
608; CHECK-32-P10-NEXT:    lxv 34, -16(1)
609; CHECK-32-P10-NEXT:    blr
610entry:
611  %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
612  ret <2 x double> %vecins
613}
614
615define <2 x double> @testDouble2(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
616; CHECK-64-LABEL: testDouble2:
617; CHECK-64:       # %bb.0: # %entry
618; CHECK-64-NEXT:    ld 6, 0(3)
619; CHECK-64-DAG:         rlwinm 4, 4, 3, 28, 28
620; CHECK-64-DAG:    addi 7, 1, -32
621; CHECK-64-NEXT:    stxv 34, -32(1)
622; CHECK-64-NEXT:    stdx 6, 7, 4
623; CHECK-64-NEXT:    li 4, 1
624; CHECK-64-NEXT:    lxv 0, -32(1)
625; CHECK-64-NEXT:    ldx 3, 3, 4
626; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
627; CHECK-64-NEXT:    addi 5, 1, -16
628; CHECK-64-NEXT:    stxv 0, -16(1)
629; CHECK-64-NEXT:    stdx 3, 5, 4
630; CHECK-64-NEXT:    lxv 34, -16(1)
631; CHECK-64-NEXT:    blr
632;
633; CHECK-32-LABEL: testDouble2:
634; CHECK-32:       # %bb.0: # %entry
635; CHECK-32-NEXT:    lfd 0, 0(3)
636; CHECK-32-NEXT:    addi 6, 1, -32
637; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
638; CHECK-32-NEXT:    stxv 34, -32(1)
639; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
640; CHECK-32-NEXT:    stfdx 0, 6, 4
641; CHECK-32-NEXT:    lxv 0, -32(1)
642; CHECK-32-NEXT:    lfd 1, 1(3)
643; CHECK-32-NEXT:    addi 3, 1, -16
644; CHECK-32-NEXT:    stxv 0, -16(1)
645; CHECK-32-NEXT:    stfdx 1, 3, 5
646; CHECK-32-NEXT:    lxv 34, -16(1)
647; CHECK-32-NEXT:    blr
648;
649; CHECK-64-P10-LABEL: testDouble2:
650; CHECK-64-P10:       # %bb.0: # %entry
651; CHECK-64-P10-NEXT:    ld 6, 0(3)
652; CHECK-64-P10-NEXT:    extsw 4, 4
653; CHECK-64-P10-NEXT:    pld 3, 1(3), 0
654; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
655; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
656; CHECK-64-P10-NEXT:    extsw 4, 5
657; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
658; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
659; CHECK-64-P10-NEXT:    blr
660;
661; CHECK-32-P10-LABEL: testDouble2:
662; CHECK-32-P10:       # %bb.0: # %entry
663; CHECK-32-P10-NEXT:    lfd 0, 0(3)
664; CHECK-32-P10-DAG:     addi 6, 1, -32
665; CHECK-32-P10-DAG:     rlwinm 4, 4, 3, 28, 28
666; CHECK-32-P10-NEXT:    stxv 34, -32(1)
667; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
668; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
669; CHECK-32-P10-NEXT:    lxv 0, -32(1)
670; CHECK-32-P10-NEXT:    plfd 1, 1(3), 0
671; CHECK-32-P10-NEXT:    addi 3, 1, -16
672; CHECK-32-P10-NEXT:    stxv 0, -16(1)
673; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
674; CHECK-32-P10-NEXT:    lxv 34, -16(1)
675; CHECK-32-P10-NEXT:    blr
676entry:
677  %0 = bitcast i8* %b to double*
678  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
679  %1 = bitcast i8* %add.ptr1 to double*
680  %2 = load double, double* %0, align 8
681  %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
682  %3 = load double, double* %1, align 8
683  %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
684  ret <2 x double> %vecins2
685}
686
687define <2 x double> @testDouble3(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
688; CHECK-64-LABEL: testDouble3:
689; CHECK-64:       # %bb.0: # %entry
690; CHECK-64-NEXT:    lis 6, 1
691; CHECK-64-DAG:     rlwinm 4, 4, 3, 28, 28
692; CHECK-64-DAG:     addi 7, 1, -32
693; CHECK-64-NEXT:    ldx 6, 3, 6
694; CHECK-64-NEXT:    stxv 34, -32(1)
695; CHECK-64-NEXT:    stdx 6, 7, 4
696; CHECK-64-NEXT:    li 4, 1
697; CHECK-64-NEXT:    lxv 0, -32(1)
698; CHECK-64-NEXT:    rldic 4, 4, 36, 27
699; CHECK-64-NEXT:    ldx 3, 3, 4
700; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
701; CHECK-64-NEXT:    addi 5, 1, -16
702; CHECK-64-NEXT:    stxv 0, -16(1)
703; CHECK-64-NEXT:    stdx 3, 5, 4
704; CHECK-64-NEXT:    lxv 34, -16(1)
705; CHECK-64-NEXT:    blr
706;
707; CHECK-32-LABEL: testDouble3:
708; CHECK-32:       # %bb.0: # %entry
709; CHECK-32-NEXT:    lis 6, 1
710; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
711; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
712; CHECK-32-NEXT:    lfdx 0, 3, 6
713; CHECK-32-NEXT:    addi 6, 1, -32
714; CHECK-32-NEXT:    stxv 34, -32(1)
715; CHECK-32-NEXT:    stfdx 0, 6, 4
716; CHECK-32-NEXT:    lxv 0, -32(1)
717; CHECK-32-NEXT:    lfd 1, 0(3)
718; CHECK-32-NEXT:    addi 3, 1, -16
719; CHECK-32-NEXT:    stxv 0, -16(1)
720; CHECK-32-NEXT:    stfdx 1, 3, 5
721; CHECK-32-NEXT:    lxv 34, -16(1)
722; CHECK-32-NEXT:    blr
723;
724; CHECK-64-P10-LABEL: testDouble3:
725; CHECK-64-P10:       # %bb.0: # %entry
726; CHECK-64-P10-NEXT:    pld 6, 65536(3), 0
727; CHECK-64-P10-NEXT:    extsw 4, 4
728; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
729; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
730; CHECK-64-P10-NEXT:    li 4, 1
731; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
732; CHECK-64-P10-NEXT:    ldx 3, 3, 4
733; CHECK-64-P10-NEXT:    extsw 4, 5
734; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
735; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
736; CHECK-64-P10-NEXT:    blr
737;
738; CHECK-32-P10-LABEL: testDouble3:
739; CHECK-32-P10:       # %bb.0: # %entry
740; CHECK-32-P10-NEXT:    plfd 0, 65536(3), 0
741; CHECK-32-P10-DAG:     addi 6, 1, -32
742; CHECK-32-P10-DAG:     rlwinm 4, 4, 3, 28, 28
743; CHECK-32-P10-NEXT:    stxv 34, -32(1)
744; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
745; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
746; CHECK-32-P10-NEXT:    lxv 0, -32(1)
747; CHECK-32-P10-NEXT:    lfd 1, 0(3)
748; CHECK-32-P10-NEXT:    addi 3, 1, -16
749; CHECK-32-P10-NEXT:    stxv 0, -16(1)
750; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
751; CHECK-32-P10-NEXT:    lxv 34, -16(1)
752; CHECK-32-P10-NEXT:    blr
753entry:
754  %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
755  %0 = bitcast i8* %add.ptr to double*
756  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
757  %1 = bitcast i8* %add.ptr1 to double*
758  %2 = load double, double* %0, align 8
759  %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
760  %3 = load double, double* %1, align 8
761  %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
762  ret <2 x double> %vecins2
763}
764
765; Double immediate
766
767define <2 x double> @testDoubleImm1(<2 x double> %a, double %b) {
768; CHECK-64-LABEL: testDoubleImm1:
769; CHECK-64:       # %bb.0: # %entry
770; CHECK-64-NEXT:    # kill: def $f1 killed $f1 def $vsl1
771; CHECK-64-NEXT:    xxpermdi 34, 1, 34, 1
772; CHECK-64-NEXT:    blr
773;
774; CHECK-32-LABEL: testDoubleImm1:
775; CHECK-32:       # %bb.0: # %entry
776; CHECK-32-NEXT:    # kill: def $f1 killed $f1 def $vsl1
777; CHECK-32-NEXT:    xxpermdi 34, 1, 34, 1
778; CHECK-32-NEXT:    blr
779;
780; CHECK-64-P10-LABEL: testDoubleImm1:
781; CHECK-64-P10:       # %bb.0: # %entry
782; CHECK-64-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
783; CHECK-64-P10-NEXT:    xxpermdi 34, 1, 34, 1
784; CHECK-64-P10-NEXT:    blr
785;
786; CHECK-32-P10-LABEL: testDoubleImm1:
787; CHECK-32-P10:       # %bb.0: # %entry
788; CHECK-32-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
789; CHECK-32-P10-NEXT:    xxpermdi 34, 1, 34, 1
790; CHECK-32-P10-NEXT:    blr
791entry:
792  %vecins = insertelement <2 x double> %a, double %b, i32 0
793  ret <2 x double> %vecins
794}
795
796define <2 x double> @testDoubleImm2(<2 x double> %a, i32* %b) {
797; CHECK-64-LABEL: testDoubleImm2:
798; CHECK-64:       # %bb.0: # %entry
799; CHECK-64-NEXT:    lfd 0, 0(3)
800; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
801; CHECK-64-NEXT:    blr
802;
803; CHECK-32-LABEL: testDoubleImm2:
804; CHECK-32:       # %bb.0: # %entry
805; CHECK-32-NEXT:    lfd 0, 0(3)
806; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
807; CHECK-32-NEXT:    blr
808;
809; CHECK-64-P10-LABEL: testDoubleImm2:
810; CHECK-64-P10:       # %bb.0: # %entry
811; CHECK-64-P10-NEXT:    lfd 0, 0(3)
812; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
813; CHECK-64-P10-NEXT:    blr
814;
815; CHECK-32-P10-LABEL: testDoubleImm2:
816; CHECK-32-P10:       # %bb.0: # %entry
817; CHECK-32-P10-NEXT:    lfd 0, 0(3)
818; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
819; CHECK-32-P10-NEXT:    blr
820entry:
821  %0 = bitcast i32* %b to double*
822  %1 = load double, double* %0, align 8
823  %vecins = insertelement <2 x double> %a, double %1, i32 0
824  ret <2 x double> %vecins
825}
826
827define <2 x double> @testDoubleImm3(<2 x double> %a, i32* %b) {
828; CHECK-64-LABEL: testDoubleImm3:
829; CHECK-64:       # %bb.0: # %entry
830; CHECK-64-NEXT:    lfd 0, 4(3)
831; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
832; CHECK-64-NEXT:    blr
833;
834; CHECK-32-LABEL: testDoubleImm3:
835; CHECK-32:       # %bb.0: # %entry
836; CHECK-32-NEXT:    lfd 0, 4(3)
837; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
838; CHECK-32-NEXT:    blr
839;
840; CHECK-64-P10-LABEL: testDoubleImm3:
841; CHECK-64-P10:       # %bb.0: # %entry
842; CHECK-64-P10-NEXT:    lfd 0, 4(3)
843; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
844; CHECK-64-P10-NEXT:    blr
845;
846; CHECK-32-P10-LABEL: testDoubleImm3:
847; CHECK-32-P10:       # %bb.0: # %entry
848; CHECK-32-P10-NEXT:    lfd 0, 4(3)
849; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
850; CHECK-32-P10-NEXT:    blr
851entry:
852  %add.ptr = getelementptr inbounds i32, i32* %b, i64 1
853  %0 = bitcast i32* %add.ptr to double*
854  %1 = load double, double* %0, align 8
855  %vecins = insertelement <2 x double> %a, double %1, i32 0
856  ret <2 x double> %vecins
857}
858
859define <2 x double> @testDoubleImm4(<2 x double> %a, i32* %b) {
860; CHECK-64-LABEL: testDoubleImm4:
861; CHECK-64:       # %bb.0: # %entry
862; CHECK-64-NEXT:    lis 4, 4
863; CHECK-64-NEXT:    lfdx 0, 3, 4
864; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
865; CHECK-64-NEXT:    blr
866;
867; CHECK-32-LABEL: testDoubleImm4:
868; CHECK-32:       # %bb.0: # %entry
869; CHECK-32-NEXT:    lis 4, 4
870; CHECK-32-NEXT:    lfdx 0, 3, 4
871; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
872; CHECK-32-NEXT:    blr
873;
874; CHECK-64-P10-LABEL: testDoubleImm4:
875; CHECK-64-P10:       # %bb.0: # %entry
876; CHECK-64-P10-NEXT:    plfd 0, 262144(3), 0
877; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
878; CHECK-64-P10-NEXT:    blr
879;
880; CHECK-32-P10-LABEL: testDoubleImm4:
881; CHECK-32-P10:       # %bb.0: # %entry
882; CHECK-32-P10-NEXT:    plfd 0, 262144(3), 0
883; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
884; CHECK-32-P10-NEXT:    blr
885entry:
886  %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
887  %0 = bitcast i32* %add.ptr to double*
888  %1 = load double, double* %0, align 8
889  %vecins = insertelement <2 x double> %a, double %1, i32 0
890  ret <2 x double> %vecins
891}
892
893define <2 x double> @testDoubleImm5(<2 x double> %a, i32* %b) {
894; CHECK-64-LABEL: testDoubleImm5:
895; CHECK-64:       # %bb.0: # %entry
896; CHECK-64-NEXT:    li 4, 1
897; CHECK-64-NEXT:    rldic 4, 4, 38, 25
898; CHECK-64-NEXT:    lfdx 0, 3, 4
899; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
900; CHECK-64-NEXT:    blr
901;
902; CHECK-32-LABEL: testDoubleImm5:
903; CHECK-32:       # %bb.0: # %entry
904; CHECK-32-NEXT:    lfd 0, 0(3)
905; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
906; CHECK-32-NEXT:    blr
907;
908; CHECK-64-P10-LABEL: testDoubleImm5:
909; CHECK-64-P10:       # %bb.0: # %entry
910; CHECK-64-P10-NEXT:    li 4, 1
911; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
912; CHECK-64-P10-NEXT:    lfdx 0, 3, 4
913; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
914; CHECK-64-P10-NEXT:    blr
915;
916; CHECK-32-P10-LABEL: testDoubleImm5:
917; CHECK-32-P10:       # %bb.0: # %entry
918; CHECK-32-P10-NEXT:    lfd 0, 0(3)
919; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
920; CHECK-32-P10-NEXT:    blr
921entry:
922  %add.ptr = getelementptr inbounds i32, i32* %b, i64 68719476736
923  %0 = bitcast i32* %add.ptr to double*
924  %1 = load double, double* %0, align 8
925  %vecins = insertelement <2 x double> %a, double %1, i32 0
926  ret <2 x double> %vecins
927}
928
929