1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
3; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10
5; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10
6
7; Byte indexed
8
9define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) {
10; CHECK-64-LABEL: testByte:
11; CHECK-64:       # %bb.0: # %entry
12; CHECK-64-NEXT:    addi 5, 1, -16
13; CHECK-64-NEXT:    clrldi 4, 4, 60
14; CHECK-64-NEXT:    stxv 34, -16(1)
15; CHECK-64-NEXT:    stbx 3, 5, 4
16; CHECK-64-NEXT:    lxv 34, -16(1)
17; CHECK-64-NEXT:    blr
18;
19; CHECK-32-LABEL: testByte:
20; CHECK-32:       # %bb.0: # %entry
21; CHECK-32-NEXT:    addi 5, 1, -16
22; CHECK-32-NEXT:    clrlwi 3, 6, 28
23; CHECK-32-NEXT:    stxv 34, -16(1)
24; CHECK-32-NEXT:    stbx 4, 5, 3
25; CHECK-32-NEXT:    lxv 34, -16(1)
26; CHECK-32-NEXT:    blr
27;
28; CHECK-64-P10-LABEL: testByte:
29; CHECK-64-P10:       # %bb.0: # %entry
30; CHECK-64-P10-NEXT:    vinsblx 2, 4, 3
31; CHECK-64-P10-NEXT:    blr
32;
33; CHECK-32-P10-LABEL: testByte:
34; CHECK-32-P10:       # %bb.0: # %entry
35; CHECK-32-P10-NEXT:    vinsblx 2, 6, 4
36; CHECK-32-P10-NEXT:    blr
37entry:
38  %conv = trunc i64 %b to i8
39  %vecins = insertelement <16 x i8> %a, i8 %conv, i64 %idx
40  ret <16 x i8> %vecins
41}
42
43; Halfword indexed
44
45define <8 x i16> @testHalf(<8 x i16> %a, i64 %b, i64 %idx) {
46; CHECK-64-LABEL: testHalf:
47; CHECK-64:       # %bb.0: # %entry
48; CHECK-64-NEXT:    addi 5, 1, -16
49; CHECK-64-NEXT:    rlwinm 4, 4, 1, 28, 30
50; CHECK-64-NEXT:    stxv 34, -16(1)
51; CHECK-64-NEXT:    sthx 3, 5, 4
52; CHECK-64-NEXT:    lxv 34, -16(1)
53; CHECK-64-NEXT:    blr
54;
55; CHECK-32-LABEL: testHalf:
56; CHECK-32:       # %bb.0: # %entry
57; CHECK-32-NEXT:    addi 5, 1, -16
58; CHECK-32-NEXT:    rlwinm 3, 6, 1, 28, 30
59; CHECK-32-NEXT:    stxv 34, -16(1)
60; CHECK-32-NEXT:    sthx 4, 5, 3
61; CHECK-32-NEXT:    lxv 34, -16(1)
62; CHECK-32-NEXT:    blr
63;
64; CHECK-64-P10-LABEL: testHalf:
65; CHECK-64-P10:       # %bb.0: # %entry
66; CHECK-64-P10-NEXT:    slwi 4, 4, 1
67; CHECK-64-P10-NEXT:    vinshlx 2, 4, 3
68; CHECK-64-P10-NEXT:    blr
69;
70; CHECK-32-P10-LABEL: testHalf:
71; CHECK-32-P10:       # %bb.0: # %entry
72; CHECK-32-P10-NEXT:    slwi 3, 6, 1
73; CHECK-32-P10-NEXT:    vinshlx 2, 3, 4
74; CHECK-32-P10-NEXT:    blr
75entry:
76  %conv = trunc i64 %b to i16
77  %vecins = insertelement <8 x i16> %a, i16 %conv, i64 %idx
78  ret <8 x i16> %vecins
79}
80
81; Word indexed
82
83define <4 x i32> @testWord(<4 x i32> %a, i64 %b, i64 %idx) {
84; CHECK-64-LABEL: testWord:
85; CHECK-64:       # %bb.0: # %entry
86; CHECK-64-NEXT:    addi 5, 1, -16
87; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
88; CHECK-64-NEXT:    stxv 34, -16(1)
89; CHECK-64-NEXT:    stwx 3, 5, 4
90; CHECK-64-NEXT:    lxv 34, -16(1)
91; CHECK-64-NEXT:    blr
92;
93; CHECK-32-LABEL: testWord:
94; CHECK-32:       # %bb.0: # %entry
95; CHECK-32-NEXT:    addi 5, 1, -16
96; CHECK-32-NEXT:    rlwinm 3, 6, 2, 28, 29
97; CHECK-32-NEXT:    stxv 34, -16(1)
98; CHECK-32-NEXT:    stwx 4, 5, 3
99; CHECK-32-NEXT:    lxv 34, -16(1)
100; CHECK-32-NEXT:    blr
101;
102; CHECK-64-P10-LABEL: testWord:
103; CHECK-64-P10:       # %bb.0: # %entry
104; CHECK-64-P10-NEXT:    slwi 4, 4, 2
105; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
106; CHECK-64-P10-NEXT:    blr
107;
108; CHECK-32-P10-LABEL: testWord:
109; CHECK-32-P10:       # %bb.0: # %entry
110; CHECK-32-P10-NEXT:    slwi 3, 6, 2
111; CHECK-32-P10-NEXT:    vinswlx 2, 3, 4
112; CHECK-32-P10-NEXT:    blr
113entry:
114  %conv = trunc i64 %b to i32
115  %vecins = insertelement <4 x i32> %a, i32 %conv, i64 %idx
116  ret <4 x i32> %vecins
117}
118
119; Word immediate
120
121define <4 x i32> @testWordImm(<4 x i32> %a, i64 %b) {
122; CHECK-64-LABEL: testWordImm:
123; CHECK-64:       # %bb.0: # %entry
124; CHECK-64-NEXT:    mtfprwz 0, 3
125; CHECK-64-NEXT:    xxinsertw 34, 0, 4
126; CHECK-64-NEXT:    xxinsertw 34, 0, 12
127; CHECK-64-NEXT:    blr
128;
129; CHECK-32-LABEL: testWordImm:
130; CHECK-32:       # %bb.0: # %entry
131; CHECK-32-NEXT:    mtfprwz 0, 4
132; CHECK-32-NEXT:    xxinsertw 34, 0, 4
133; CHECK-32-NEXT:    xxinsertw 34, 0, 12
134; CHECK-32-NEXT:    blr
135;
136; CHECK-64-P10-LABEL: testWordImm:
137; CHECK-64-P10:       # %bb.0: # %entry
138; CHECK-64-P10-NEXT:    vinsw 2, 3, 4
139; CHECK-64-P10-NEXT:    vinsw 2, 3, 12
140; CHECK-64-P10-NEXT:    blr
141;
142; CHECK-32-P10-LABEL: testWordImm:
143; CHECK-32-P10:       # %bb.0: # %entry
144; CHECK-32-P10-NEXT:    vinsw 2, 4, 4
145; CHECK-32-P10-NEXT:    vinsw 2, 4, 12
146; CHECK-32-P10-NEXT:    blr
147entry:
148  %conv = trunc i64 %b to i32
149  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 1
150  %vecins2 = insertelement <4 x i32> %vecins, i32 %conv, i32 3
151  ret <4 x i32> %vecins2
152}
153
154; Doubleword indexed
155
156define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
157; CHECK-64-LABEL: testDoubleword:
158; CHECK-64:       # %bb.0: # %entry
159; CHECK-64-NEXT:    addi 5, 1, -16
160; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
161; CHECK-64-NEXT:    stxv 34, -16(1)
162; CHECK-64-NEXT:    stdx 3, 5, 4
163; CHECK-64-NEXT:    lxv 34, -16(1)
164; CHECK-64-NEXT:    blr
165;
166; CHECK-32-LABEL: testDoubleword:
167; CHECK-32:       # %bb.0: # %entry
168; CHECK-32-NEXT:    add 5, 6, 6
169; CHECK-32-NEXT:    addi 7, 1, -32
170; CHECK-32-NEXT:    stxv 34, -32(1)
171; CHECK-32-NEXT:    rlwinm 6, 5, 2, 28, 29
172; CHECK-32-NEXT:    stwx 3, 7, 6
173; CHECK-32-NEXT:    addi 3, 5, 1
174; CHECK-32-NEXT:    addi 5, 1, -16
175; CHECK-32-NEXT:    lxv 0, -32(1)
176; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
177; CHECK-32-NEXT:    stxv 0, -16(1)
178; CHECK-32-NEXT:    stwx 4, 5, 3
179; CHECK-32-NEXT:    lxv 34, -16(1)
180; CHECK-32-NEXT:    blr
181;
182; CHECK-64-P10-LABEL: testDoubleword:
183; CHECK-64-P10:       # %bb.0: # %entry
184; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
185; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
186; CHECK-64-P10-NEXT:    blr
187;
188; CHECK-32-P10-LABEL: testDoubleword:
189; CHECK-32-P10:       # %bb.0: # %entry
190; CHECK-32-P10-NEXT:    add 5, 6, 6
191; CHECK-32-P10-NEXT:    slwi 6, 5, 2
192; CHECK-32-P10-NEXT:    vinswlx 2, 6, 3
193; CHECK-32-P10-NEXT:    addi 3, 5, 1
194; CHECK-32-P10-NEXT:    slwi 3, 3, 2
195; CHECK-32-P10-NEXT:    vinswlx 2, 3, 4
196; CHECK-32-P10-NEXT:    blr
197entry:
198  %vecins = insertelement <2 x i64> %a, i64 %b, i64 %idx
199  ret <2 x i64> %vecins
200}
201
202; Doubleword immediate
203
204define <2 x i64> @testDoublewordImm(<2 x i64> %a, i64 %b) {
205; CHECK-64-LABEL: testDoublewordImm:
206; CHECK-64:       # %bb.0: # %entry
207; CHECK-64-NEXT:    mtfprd 0, 3
208; CHECK-64-NEXT:    xxmrghd 34, 34, 0
209; CHECK-64-NEXT:    blr
210;
211; CHECK-32-LABEL: testDoublewordImm:
212; CHECK-32:       # %bb.0: # %entry
213; CHECK-32-NEXT:    mtfprwz 0, 3
214; CHECK-32-NEXT:    xxinsertw 34, 0, 8
215; CHECK-32-NEXT:    mtfprwz 0, 4
216; CHECK-32-NEXT:    xxinsertw 34, 0, 12
217; CHECK-32-NEXT:    blr
218;
219; CHECK-64-P10-LABEL: testDoublewordImm:
220; CHECK-64-P10:       # %bb.0: # %entry
221; CHECK-64-P10-NEXT:    vinsd 2, 3, 8
222; CHECK-64-P10-NEXT:    blr
223;
224; CHECK-32-P10-LABEL: testDoublewordImm:
225; CHECK-32-P10:       # %bb.0: # %entry
226; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
227; CHECK-32-P10-NEXT:    vinsw 2, 4, 12
228; CHECK-32-P10-NEXT:    blr
229entry:
230  %vecins = insertelement <2 x i64> %a, i64 %b, i32 1
231  ret <2 x i64> %vecins
232}
233
234define <2 x i64> @testDoublewordImm2(<2 x i64> %a, i64 %b) {
235; CHECK-64-LABEL: testDoublewordImm2:
236; CHECK-64:       # %bb.0: # %entry
237; CHECK-64-NEXT:    mtfprd 0, 3
238; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
239; CHECK-64-NEXT:    blr
240;
241; CHECK-32-LABEL: testDoublewordImm2:
242; CHECK-32:       # %bb.0: # %entry
243; CHECK-32-NEXT:    mtfprwz 0, 3
244; CHECK-32-NEXT:    xxinsertw 34, 0, 0
245; CHECK-32-NEXT:    mtfprwz 0, 4
246; CHECK-32-NEXT:    xxinsertw 34, 0, 4
247; CHECK-32-NEXT:    blr
248;
249; CHECK-64-P10-LABEL: testDoublewordImm2:
250; CHECK-64-P10:       # %bb.0: # %entry
251; CHECK-64-P10-NEXT:    vinsd 2, 3, 0
252; CHECK-64-P10-NEXT:    blr
253;
254; CHECK-32-P10-LABEL: testDoublewordImm2:
255; CHECK-32-P10:       # %bb.0: # %entry
256; CHECK-32-P10-NEXT:    vinsw 2, 3, 0
257; CHECK-32-P10-NEXT:    vinsw 2, 4, 4
258; CHECK-32-P10-NEXT:    blr
259entry:
260  %vecins = insertelement <2 x i64> %a, i64 %b, i32 0
261  ret <2 x i64> %vecins
262}
263
264; Float indexed
265
266define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
267; CHECK-64-LABEL: testFloat1:
268; CHECK-64:       # %bb.0: # %entry
269; CHECK-64-DAG:     rlwinm 3, 4, 2, 28, 29
270; CHECK-64-DAG:     addi 4, 1, -16
271; CHECK-64-NEXT:    stxv 34, -16(1)
272; CHECK-64-NEXT:    stfsx 1, 4, 3
273; CHECK-64-NEXT:    lxv 34, -16(1)
274; CHECK-64-NEXT:    blr
275;
276; CHECK-32-LABEL: testFloat1:
277; CHECK-32:       # %bb.0: # %entry
278; CHECK-32-NEXT:    rlwinm 3, 4, 2, 28, 29
279; CHECK-32-NEXT:    addi 4, 1, -16
280; CHECK-32-NEXT:    stxv 34, -16(1)
281; CHECK-32-NEXT:    stfsx 1, 4, 3
282; CHECK-32-NEXT:    lxv 34, -16(1)
283; CHECK-32-NEXT:    blr
284;
285; CHECK-64-P10-LABEL: testFloat1:
286; CHECK-64-P10:       # %bb.0: # %entry
287; CHECK-64-P10-NEXT:    xscvdpspn 35, 1
288; CHECK-64-P10-NEXT:    extsw 3, 4
289; CHECK-64-P10-NEXT:    slwi 3, 3, 2
290; CHECK-64-P10-NEXT:    vinswvlx 2, 3, 3
291; CHECK-64-P10-NEXT:    blr
292;
293; CHECK-32-P10-LABEL: testFloat1:
294; CHECK-32-P10:       # %bb.0: # %entry
295; CHECK-32-P10-NEXT:    xscvdpspn 35, 1
296; CHECK-32-P10-NEXT:    slwi 3, 4, 2
297; CHECK-32-P10-NEXT:    vinswvlx 2, 3, 3
298; CHECK-32-P10-NEXT:    blr
299entry:
300  %vecins = insertelement <4 x float> %a, float %b, i32 %idx1
301  ret <4 x float> %vecins
302}
303
304define <4 x float> @testFloat2(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
305; CHECK-64-LABEL: testFloat2:
306; CHECK-64:       # %bb.0: # %entry
307; CHECK-64-NEXT:    lwz 6, 0(3)
308; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
309; CHECK-64-DAG:     addi 7, 1, -16
310; CHECK-64-NEXT:    stxv 34, -16(1)
311; CHECK-64-NEXT:    stwx 6, 7, 4
312; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
313; CHECK-64-NEXT:    addi 5, 1, -32
314; CHECK-64-NEXT:    lxv 0, -16(1)
315; CHECK-64-NEXT:    lwz 3, 1(3)
316; CHECK-64-NEXT:    stxv 0, -32(1)
317; CHECK-64-NEXT:    stwx 3, 5, 4
318; CHECK-64-NEXT:    lxv 34, -32(1)
319; CHECK-64-NEXT:    blr
320;
321; CHECK-32-LABEL: testFloat2:
322; CHECK-32:       # %bb.0: # %entry
323; CHECK-32-NEXT:    lwz 6, 0(3)
324; CHECK-32-NEXT:    addi 7, 1, -16
325; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
326; CHECK-32-NEXT:    stxv 34, -16(1)
327; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
328; CHECK-32-NEXT:    stwx 6, 7, 4
329; CHECK-32-NEXT:    addi 4, 1, -48
330; CHECK-32-NEXT:    lxv 0, -16(1)
331; CHECK-32-NEXT:    lwz 3, 1(3)
332; CHECK-32-NEXT:    stxv 0, -48(1)
333; CHECK-32-NEXT:    stwx 3, 4, 5
334; CHECK-32-NEXT:    lxv 34, -48(1)
335; CHECK-32-NEXT:    blr
336;
337; CHECK-64-P10-LABEL: testFloat2:
338; CHECK-64-P10:       # %bb.0: # %entry
339; CHECK-64-P10-NEXT:    lwz 6, 0(3)
340; CHECK-64-P10-NEXT:    extsw 4, 4
341; CHECK-64-P10-NEXT:    lwz 3, 1(3)
342; CHECK-64-P10-NEXT:    slwi 4, 4, 2
343; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
344; CHECK-64-P10-NEXT:    extsw 4, 5
345; CHECK-64-P10-NEXT:    slwi 4, 4, 2
346; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
347; CHECK-64-P10-NEXT:    blr
348;
349; CHECK-32-P10-LABEL: testFloat2:
350; CHECK-32-P10:       # %bb.0: # %entry
351; CHECK-32-P10-NEXT:    lwz 6, 0(3)
352; CHECK-32-P10-NEXT:    lwz 3, 1(3)
353; CHECK-32-P10-NEXT:    slwi 4, 4, 2
354; CHECK-32-P10-NEXT:    vinswlx 2, 4, 6
355; CHECK-32-P10-NEXT:    slwi 4, 5, 2
356; CHECK-32-P10-NEXT:    vinswlx 2, 4, 3
357; CHECK-32-P10-NEXT:    blr
358entry:
359  %0 = bitcast i8* %b to float*
360  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
361  %1 = bitcast i8* %add.ptr1 to float*
362  %2 = load float, float* %0, align 4
363  %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
364  %3 = load float, float* %1, align 4
365  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
366  ret <4 x float> %vecins2
367}
368
369define <4 x float> @testFloat3(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
370; CHECK-64-LABEL: testFloat3:
371; CHECK-64:       # %bb.0: # %entry
372; CHECK-64-NEXT:    lis 6, 1
373; CHECK-64-DAG:         rlwinm 4, 4, 2, 28, 29
374; CHECK-64-DAG:    addi 7, 1, -16
375; CHECK-64-NEXT:    lwzx 6, 3, 6
376; CHECK-64-NEXT:    stxv 34, -16(1)
377; CHECK-64-NEXT:    stwx 6, 7, 4
378; CHECK-64-NEXT:    li 4, 1
379; CHECK-64-NEXT:    lxv 0, -16(1)
380; CHECK-64-NEXT:    rldic 4, 4, 36, 27
381; CHECK-64-NEXT:    lwzx 3, 3, 4
382; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
383; CHECK-64-NEXT:    addi 5, 1, -32
384; CHECK-64-NEXT:    stxv 0, -32(1)
385; CHECK-64-NEXT:    stwx 3, 5, 4
386; CHECK-64-NEXT:    lxv 34, -32(1)
387; CHECK-64-NEXT:    blr
388;
389; CHECK-32-LABEL: testFloat3:
390; CHECK-32:       # %bb.0: # %entry
391; CHECK-32-NEXT:    lis 6, 1
392; CHECK-32-NEXT:    addi 7, 1, -16
393; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
394; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
395; CHECK-32-NEXT:    lwzx 6, 3, 6
396; CHECK-32-NEXT:    stxv 34, -16(1)
397; CHECK-32-NEXT:    stwx 6, 7, 4
398; CHECK-32-NEXT:    addi 4, 1, -48
399; CHECK-32-NEXT:    lxv 0, -16(1)
400; CHECK-32-NEXT:    lwz 3, 0(3)
401; CHECK-32-NEXT:    stxv 0, -48(1)
402; CHECK-32-NEXT:    stwx 3, 4, 5
403; CHECK-32-NEXT:    lxv 34, -48(1)
404; CHECK-32-NEXT:    blr
405;
406; CHECK-64-P10-LABEL: testFloat3:
407; CHECK-64-P10:       # %bb.0: # %entry
408; CHECK-64-P10-NEXT:    plwz 6, 65536(3), 0
409; CHECK-64-P10-NEXT:    extsw 4, 4
410; CHECK-64-P10-NEXT:    slwi 4, 4, 2
411; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
412; CHECK-64-P10-NEXT:    li 4, 1
413; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
414; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
415; CHECK-64-P10-NEXT:    extsw 4, 5
416; CHECK-64-P10-NEXT:    slwi 4, 4, 2
417; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
418; CHECK-64-P10-NEXT:    blr
419;
420; CHECK-32-P10-LABEL: testFloat3:
421; CHECK-32-P10:       # %bb.0: # %entry
422; CHECK-32-P10-NEXT:    plwz 6, 65536(3), 0
423; CHECK-32-P10-NEXT:    lwz 3, 0(3)
424; CHECK-32-P10-NEXT:    slwi 4, 4, 2
425; CHECK-32-P10-NEXT:    vinswlx 2, 4, 6
426; CHECK-32-P10-NEXT:    slwi 4, 5, 2
427; CHECK-32-P10-NEXT:    vinswlx 2, 4, 3
428; CHECK-32-P10-NEXT:    blr
429entry:
430  %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
431  %0 = bitcast i8* %add.ptr to float*
432  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
433  %1 = bitcast i8* %add.ptr1 to float*
434  %2 = load float, float* %0, align 4
435  %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
436  %3 = load float, float* %1, align 4
437  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
438  ret <4 x float> %vecins2
439}
440
441; Float immediate
442
443define <4 x float> @testFloatImm1(<4 x float> %a, float %b) {
444; CHECK-64-LABEL: testFloatImm1:
445; CHECK-64:       # %bb.0: # %entry
446; CHECK-64-NEXT:    xscvdpspn 0, 1
447; CHECK-64-NEXT:    xxinsertw 34, 0, 0
448; CHECK-64-NEXT:    xxinsertw 34, 0, 8
449; CHECK-64-NEXT:    blr
450;
451; CHECK-32-LABEL: testFloatImm1:
452; CHECK-32:       # %bb.0: # %entry
453; CHECK-32-NEXT:    xscvdpspn 0, 1
454; CHECK-32-NEXT:    xxinsertw 34, 0, 0
455; CHECK-32-NEXT:    xxinsertw 34, 0, 8
456; CHECK-32-NEXT:    blr
457;
458; CHECK-64-P10-LABEL: testFloatImm1:
459; CHECK-64-P10:       # %bb.0: # %entry
460; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
461; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 0
462; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 8
463; CHECK-64-P10-NEXT:    blr
464;
465; CHECK-32-P10-LABEL: testFloatImm1:
466; CHECK-32-P10:       # %bb.0: # %entry
467; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
468; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
469; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
470; CHECK-32-P10-NEXT:    blr
471entry:
472  %vecins = insertelement <4 x float> %a, float %b, i32 0
473  %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2
474  ret <4 x float> %vecins1
475}
476
477define <4 x float> @testFloatImm2(<4 x float> %a, i32* %b) {
478; CHECK-64-LABEL: testFloatImm2:
479; CHECK-64:       # %bb.0: # %entry
480; CHECK-64-NEXT:    lwz 4, 0(3)
481; CHECK-64-NEXT:    lwz 3, 4(3)
482; CHECK-64-NEXT:    mtfprwz 0, 4
483; CHECK-64-NEXT:    xxinsertw 34, 0, 0
484; CHECK-64-NEXT:    mtfprwz 0, 3
485; CHECK-64-NEXT:    xxinsertw 34, 0, 8
486; CHECK-64-NEXT:    blr
487;
488; CHECK-32-LABEL: testFloatImm2:
489; CHECK-32:       # %bb.0: # %entry
490; CHECK-32-NEXT:    lwz 4, 0(3)
491; CHECK-32-NEXT:    lwz 3, 4(3)
492; CHECK-32-NEXT:    mtfprwz 0, 4
493; CHECK-32-NEXT:    xxinsertw 34, 0, 0
494; CHECK-32-NEXT:    mtfprwz 0, 3
495; CHECK-32-NEXT:    xxinsertw 34, 0, 8
496; CHECK-32-NEXT:    blr
497;
498; CHECK-64-P10-LABEL: testFloatImm2:
499; CHECK-64-P10:       # %bb.0: # %entry
500; CHECK-64-P10-NEXT:    lwz 4, 0(3)
501; CHECK-64-P10-NEXT:    lwz 3, 4(3)
502; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
503; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
504; CHECK-64-P10-NEXT:    blr
505;
506; CHECK-32-P10-LABEL: testFloatImm2:
507; CHECK-32-P10:       # %bb.0: # %entry
508; CHECK-32-P10-NEXT:    lwz 4, 0(3)
509; CHECK-32-P10-NEXT:    lwz 3, 4(3)
510; CHECK-32-P10-NEXT:    vinsw 2, 4, 0
511; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
512; CHECK-32-P10-NEXT:    blr
513entry:
514  %0 = bitcast i32* %b to float*
515  %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 1
516  %1 = bitcast i32* %add.ptr1 to float*
517  %2 = load float, float* %0, align 4
518  %vecins = insertelement <4 x float> %a, float %2, i32 0
519  %3 = load float, float* %1, align 4
520  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2
521  ret <4 x float> %vecins2
522}
523
524define <4 x float> @testFloatImm3(<4 x float> %a, i32* %b) {
525; CHECK-64-LABEL: testFloatImm3:
526; CHECK-64:       # %bb.0: # %entry
527; CHECK-64-NEXT:    lis 4, 4
528; CHECK-64-NEXT:    lwzx 4, 3, 4
529; CHECK-64-NEXT:    mtfprwz 0, 4
530; CHECK-64-NEXT:    li 4, 1
531; CHECK-64-NEXT:    rldic 4, 4, 38, 25
532; CHECK-64-NEXT:    xxinsertw 34, 0, 0
533; CHECK-64-NEXT:    lwzx 3, 3, 4
534; CHECK-64-NEXT:    mtfprwz 0, 3
535; CHECK-64-NEXT:    xxinsertw 34, 0, 8
536; CHECK-64-NEXT:    blr
537;
538; CHECK-32-LABEL: testFloatImm3:
539; CHECK-32:       # %bb.0: # %entry
540; CHECK-32-NEXT:    lis 4, 4
541; CHECK-32-NEXT:    lwzx 4, 3, 4
542; CHECK-32-NEXT:    lwz 3, 0(3)
543; CHECK-32-NEXT:    mtfprwz 0, 4
544; CHECK-32-NEXT:    xxinsertw 34, 0, 0
545; CHECK-32-NEXT:    mtfprwz 0, 3
546; CHECK-32-NEXT:    xxinsertw 34, 0, 8
547; CHECK-32-NEXT:    blr
548;
549; CHECK-64-P10-LABEL: testFloatImm3:
550; CHECK-64-P10:       # %bb.0: # %entry
551; CHECK-64-P10-NEXT:    plwz 4, 262144(3), 0
552; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
553; CHECK-64-P10-NEXT:    li 4, 1
554; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
555; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
556; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
557; CHECK-64-P10-NEXT:    blr
558;
559; CHECK-32-P10-LABEL: testFloatImm3:
560; CHECK-32-P10:       # %bb.0: # %entry
561; CHECK-32-P10-NEXT:    plwz 4, 262144(3), 0
562; CHECK-32-P10-NEXT:    lwz 3, 0(3)
563; CHECK-32-P10-NEXT:    vinsw 2, 4, 0
564; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
565; CHECK-32-P10-NEXT:    blr
566entry:
567  %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
568  %0 = bitcast i32* %add.ptr to float*
569  %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736
570  %1 = bitcast i32* %add.ptr1 to float*
571  %2 = load float, float* %0, align 4
572  %vecins = insertelement <4 x float> %a, float %2, i32 0
573  %3 = load float, float* %1, align 4
574  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2
575  ret <4 x float> %vecins2
576}
577
578; Double indexed
579
580define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) {
581; CHECK-64-LABEL: testDouble1:
582; CHECK-64:       # %bb.0: # %entry
583; CHECK-64:         rlwinm 3, 4, 3, 28, 28
584; CHECK-64-NEXT:    addi 4, 1, -16
585; CHECK-64-NEXT:    stxv 34, -16(1)
586; CHECK-64-NEXT:    stfdx 1, 4, 3
587; CHECK-64-NEXT:    lxv 34, -16(1)
588; CHECK-64-NEXT:    blr
589;
590; CHECK-32-LABEL: testDouble1:
591; CHECK-32:       # %bb.0: # %entry
592; CHECK-32-NEXT:    addi 4, 1, -16
593; CHECK-32-NEXT:    rlwinm 3, 5, 3, 28, 28
594; CHECK-32-NEXT:    stxv 34, -16(1)
595; CHECK-32-NEXT:    stfdx 1, 4, 3
596; CHECK-32-NEXT:    lxv 34, -16(1)
597; CHECK-32-NEXT:    blr
598;
599; CHECK-64-P10-LABEL: testDouble1:
600; CHECK-64-P10:       # %bb.0: # %entry
601; CHECK-64-P10-NEXT:    extsw 4, 4
602; CHECK-64-P10-NEXT:    mffprd 3, 1
603; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
604; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
605; CHECK-64-P10-NEXT:    blr
606;
607; CHECK-32-P10-LABEL: testDouble1:
608; CHECK-32-P10:       # %bb.0: # %entry
609; CHECK-32-P10-DAG:     addi 4, 1, -16
610; CHECK-32-P10-DAG:     rlwinm 3, 5, 3, 28, 28
611; CHECK-32-P10-NEXT:    stxv 34, -16(1)
612; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
613; CHECK-32-P10-NEXT:    lxv 34, -16(1)
614; CHECK-32-P10-NEXT:    blr
615entry:
616  %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
617  ret <2 x double> %vecins
618}
619
620define <2 x double> @testDouble2(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
621; CHECK-64-LABEL: testDouble2:
622; CHECK-64:       # %bb.0: # %entry
623; CHECK-64-NEXT:    ld 6, 0(3)
624; CHECK-64-DAG:         rlwinm 4, 4, 3, 28, 28
625; CHECK-64-DAG:    addi 7, 1, -32
626; CHECK-64-NEXT:    stxv 34, -32(1)
627; CHECK-64-NEXT:    stdx 6, 7, 4
628; CHECK-64-NEXT:    li 4, 1
629; CHECK-64-NEXT:    lxv 0, -32(1)
630; CHECK-64-NEXT:    ldx 3, 3, 4
631; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
632; CHECK-64-NEXT:    addi 5, 1, -16
633; CHECK-64-NEXT:    stxv 0, -16(1)
634; CHECK-64-NEXT:    stdx 3, 5, 4
635; CHECK-64-NEXT:    lxv 34, -16(1)
636; CHECK-64-NEXT:    blr
637;
638; CHECK-32-LABEL: testDouble2:
639; CHECK-32:       # %bb.0: # %entry
640; CHECK-32-NEXT:    lfd 0, 0(3)
641; CHECK-32-NEXT:    addi 6, 1, -32
642; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
643; CHECK-32-NEXT:    stxv 34, -32(1)
644; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
645; CHECK-32-NEXT:    stfdx 0, 6, 4
646; CHECK-32-NEXT:    lxv 0, -32(1)
647; CHECK-32-NEXT:    lfd 1, 1(3)
648; CHECK-32-NEXT:    addi 3, 1, -16
649; CHECK-32-NEXT:    stxv 0, -16(1)
650; CHECK-32-NEXT:    stfdx 1, 3, 5
651; CHECK-32-NEXT:    lxv 34, -16(1)
652; CHECK-32-NEXT:    blr
653;
654; CHECK-64-P10-LABEL: testDouble2:
655; CHECK-64-P10:       # %bb.0: # %entry
656; CHECK-64-P10-NEXT:    ld 6, 0(3)
657; CHECK-64-P10-NEXT:    extsw 4, 4
658; CHECK-64-P10-NEXT:    pld 3, 1(3), 0
659; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
660; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
661; CHECK-64-P10-NEXT:    extsw 4, 5
662; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
663; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
664; CHECK-64-P10-NEXT:    blr
665;
666; CHECK-32-P10-LABEL: testDouble2:
667; CHECK-32-P10:       # %bb.0: # %entry
668; CHECK-32-P10-NEXT:    lfd 0, 0(3)
669; CHECK-32-P10-DAG:     addi 6, 1, -32
670; CHECK-32-P10-DAG:     rlwinm 4, 4, 3, 28, 28
671; CHECK-32-P10-NEXT:    stxv 34, -32(1)
672; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
673; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
674; CHECK-32-P10-NEXT:    lxv 0, -32(1)
675; CHECK-32-P10-NEXT:    plfd 1, 1(3), 0
676; CHECK-32-P10-NEXT:    addi 3, 1, -16
677; CHECK-32-P10-NEXT:    stxv 0, -16(1)
678; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
679; CHECK-32-P10-NEXT:    lxv 34, -16(1)
680; CHECK-32-P10-NEXT:    blr
681entry:
682  %0 = bitcast i8* %b to double*
683  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
684  %1 = bitcast i8* %add.ptr1 to double*
685  %2 = load double, double* %0, align 8
686  %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
687  %3 = load double, double* %1, align 8
688  %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
689  ret <2 x double> %vecins2
690}
691
692define <2 x double> @testDouble3(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
693; CHECK-64-LABEL: testDouble3:
694; CHECK-64:       # %bb.0: # %entry
695; CHECK-64-NEXT:    lis 6, 1
696; CHECK-64-DAG:     rlwinm 4, 4, 3, 28, 28
697; CHECK-64-DAG:     addi 7, 1, -32
698; CHECK-64-NEXT:    ldx 6, 3, 6
699; CHECK-64-NEXT:    stxv 34, -32(1)
700; CHECK-64-NEXT:    stdx 6, 7, 4
701; CHECK-64-NEXT:    li 4, 1
702; CHECK-64-NEXT:    lxv 0, -32(1)
703; CHECK-64-NEXT:    rldic 4, 4, 36, 27
704; CHECK-64-NEXT:    ldx 3, 3, 4
705; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
706; CHECK-64-NEXT:    addi 5, 1, -16
707; CHECK-64-NEXT:    stxv 0, -16(1)
708; CHECK-64-NEXT:    stdx 3, 5, 4
709; CHECK-64-NEXT:    lxv 34, -16(1)
710; CHECK-64-NEXT:    blr
711;
712; CHECK-32-LABEL: testDouble3:
713; CHECK-32:       # %bb.0: # %entry
714; CHECK-32-NEXT:    lis 6, 1
715; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
716; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
717; CHECK-32-NEXT:    lfdx 0, 3, 6
718; CHECK-32-NEXT:    addi 6, 1, -32
719; CHECK-32-NEXT:    stxv 34, -32(1)
720; CHECK-32-NEXT:    stfdx 0, 6, 4
721; CHECK-32-NEXT:    lxv 0, -32(1)
722; CHECK-32-NEXT:    lfd 1, 0(3)
723; CHECK-32-NEXT:    addi 3, 1, -16
724; CHECK-32-NEXT:    stxv 0, -16(1)
725; CHECK-32-NEXT:    stfdx 1, 3, 5
726; CHECK-32-NEXT:    lxv 34, -16(1)
727; CHECK-32-NEXT:    blr
728;
729; CHECK-64-P10-LABEL: testDouble3:
730; CHECK-64-P10:       # %bb.0: # %entry
731; CHECK-64-P10-NEXT:    pld 6, 65536(3), 0
732; CHECK-64-P10-NEXT:    extsw 4, 4
733; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
734; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
735; CHECK-64-P10-NEXT:    li 4, 1
736; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
737; CHECK-64-P10-NEXT:    ldx 3, 3, 4
738; CHECK-64-P10-NEXT:    extsw 4, 5
739; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
740; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
741; CHECK-64-P10-NEXT:    blr
742;
743; CHECK-32-P10-LABEL: testDouble3:
744; CHECK-32-P10:       # %bb.0: # %entry
745; CHECK-32-P10-NEXT:    plfd 0, 65536(3), 0
746; CHECK-32-P10-DAG:     addi 6, 1, -32
747; CHECK-32-P10-DAG:     rlwinm 4, 4, 3, 28, 28
748; CHECK-32-P10-NEXT:    stxv 34, -32(1)
749; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
750; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
751; CHECK-32-P10-NEXT:    lxv 0, -32(1)
752; CHECK-32-P10-NEXT:    lfd 1, 0(3)
753; CHECK-32-P10-NEXT:    addi 3, 1, -16
754; CHECK-32-P10-NEXT:    stxv 0, -16(1)
755; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
756; CHECK-32-P10-NEXT:    lxv 34, -16(1)
757; CHECK-32-P10-NEXT:    blr
758entry:
759  %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
760  %0 = bitcast i8* %add.ptr to double*
761  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
762  %1 = bitcast i8* %add.ptr1 to double*
763  %2 = load double, double* %0, align 8
764  %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
765  %3 = load double, double* %1, align 8
766  %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
767  ret <2 x double> %vecins2
768}
769
770; Double immediate
771
772define <2 x double> @testDoubleImm1(<2 x double> %a, double %b) {
773; CHECK-64-LABEL: testDoubleImm1:
774; CHECK-64:       # %bb.0: # %entry
775; CHECK-64-NEXT:    # kill: def $f1 killed $f1 def $vsl1
776; CHECK-64-NEXT:    xxpermdi 34, 1, 34, 1
777; CHECK-64-NEXT:    blr
778;
779; CHECK-32-LABEL: testDoubleImm1:
780; CHECK-32:       # %bb.0: # %entry
781; CHECK-32-NEXT:    # kill: def $f1 killed $f1 def $vsl1
782; CHECK-32-NEXT:    xxpermdi 34, 1, 34, 1
783; CHECK-32-NEXT:    blr
784;
785; CHECK-64-P10-LABEL: testDoubleImm1:
786; CHECK-64-P10:       # %bb.0: # %entry
787; CHECK-64-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
788; CHECK-64-P10-NEXT:    xxpermdi 34, 1, 34, 1
789; CHECK-64-P10-NEXT:    blr
790;
791; CHECK-32-P10-LABEL: testDoubleImm1:
792; CHECK-32-P10:       # %bb.0: # %entry
793; CHECK-32-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
794; CHECK-32-P10-NEXT:    xxpermdi 34, 1, 34, 1
795; CHECK-32-P10-NEXT:    blr
796entry:
797  %vecins = insertelement <2 x double> %a, double %b, i32 0
798  ret <2 x double> %vecins
799}
800
801define <2 x double> @testDoubleImm2(<2 x double> %a, i32* %b) {
802; CHECK-64-LABEL: testDoubleImm2:
803; CHECK-64:       # %bb.0: # %entry
804; CHECK-64-NEXT:    lfd 0, 0(3)
805; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
806; CHECK-64-NEXT:    blr
807;
808; CHECK-32-LABEL: testDoubleImm2:
809; CHECK-32:       # %bb.0: # %entry
810; CHECK-32-NEXT:    lfd 0, 0(3)
811; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
812; CHECK-32-NEXT:    blr
813;
814; CHECK-64-P10-LABEL: testDoubleImm2:
815; CHECK-64-P10:       # %bb.0: # %entry
816; CHECK-64-P10-NEXT:    lfd 0, 0(3)
817; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
818; CHECK-64-P10-NEXT:    blr
819;
820; CHECK-32-P10-LABEL: testDoubleImm2:
821; CHECK-32-P10:       # %bb.0: # %entry
822; CHECK-32-P10-NEXT:    lfd 0, 0(3)
823; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
824; CHECK-32-P10-NEXT:    blr
825entry:
826  %0 = bitcast i32* %b to double*
827  %1 = load double, double* %0, align 8
828  %vecins = insertelement <2 x double> %a, double %1, i32 0
829  ret <2 x double> %vecins
830}
831
832define <2 x double> @testDoubleImm3(<2 x double> %a, i32* %b) {
833; CHECK-64-LABEL: testDoubleImm3:
834; CHECK-64:       # %bb.0: # %entry
835; CHECK-64-NEXT:    lfd 0, 4(3)
836; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
837; CHECK-64-NEXT:    blr
838;
839; CHECK-32-LABEL: testDoubleImm3:
840; CHECK-32:       # %bb.0: # %entry
841; CHECK-32-NEXT:    lfd 0, 4(3)
842; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
843; CHECK-32-NEXT:    blr
844;
845; CHECK-64-P10-LABEL: testDoubleImm3:
846; CHECK-64-P10:       # %bb.0: # %entry
847; CHECK-64-P10-NEXT:    lfd 0, 4(3)
848; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
849; CHECK-64-P10-NEXT:    blr
850;
851; CHECK-32-P10-LABEL: testDoubleImm3:
852; CHECK-32-P10:       # %bb.0: # %entry
853; CHECK-32-P10-NEXT:    lfd 0, 4(3)
854; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
855; CHECK-32-P10-NEXT:    blr
856entry:
857  %add.ptr = getelementptr inbounds i32, i32* %b, i64 1
858  %0 = bitcast i32* %add.ptr to double*
859  %1 = load double, double* %0, align 8
860  %vecins = insertelement <2 x double> %a, double %1, i32 0
861  ret <2 x double> %vecins
862}
863
864define <2 x double> @testDoubleImm4(<2 x double> %a, i32* %b) {
865; CHECK-64-LABEL: testDoubleImm4:
866; CHECK-64:       # %bb.0: # %entry
867; CHECK-64-NEXT:    lis 4, 4
868; CHECK-64-NEXT:    lfdx 0, 3, 4
869; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
870; CHECK-64-NEXT:    blr
871;
872; CHECK-32-LABEL: testDoubleImm4:
873; CHECK-32:       # %bb.0: # %entry
874; CHECK-32-NEXT:    lis 4, 4
875; CHECK-32-NEXT:    lfdx 0, 3, 4
876; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
877; CHECK-32-NEXT:    blr
878;
879; CHECK-64-P10-LABEL: testDoubleImm4:
880; CHECK-64-P10:       # %bb.0: # %entry
881; CHECK-64-P10-NEXT:    plfd 0, 262144(3), 0
882; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
883; CHECK-64-P10-NEXT:    blr
884;
885; CHECK-32-P10-LABEL: testDoubleImm4:
886; CHECK-32-P10:       # %bb.0: # %entry
887; CHECK-32-P10-NEXT:    plfd 0, 262144(3), 0
888; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
889; CHECK-32-P10-NEXT:    blr
890entry:
891  %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
892  %0 = bitcast i32* %add.ptr to double*
893  %1 = load double, double* %0, align 8
894  %vecins = insertelement <2 x double> %a, double %1, i32 0
895  ret <2 x double> %vecins
896}
897
898define <2 x double> @testDoubleImm5(<2 x double> %a, i32* %b) {
899; CHECK-64-LABEL: testDoubleImm5:
900; CHECK-64:       # %bb.0: # %entry
901; CHECK-64-NEXT:    li 4, 1
902; CHECK-64-NEXT:    rldic 4, 4, 38, 25
903; CHECK-64-NEXT:    lfdx 0, 3, 4
904; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
905; CHECK-64-NEXT:    blr
906;
907; CHECK-32-LABEL: testDoubleImm5:
908; CHECK-32:       # %bb.0: # %entry
909; CHECK-32-NEXT:    lfd 0, 0(3)
910; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
911; CHECK-32-NEXT:    blr
912;
913; CHECK-64-P10-LABEL: testDoubleImm5:
914; CHECK-64-P10:       # %bb.0: # %entry
915; CHECK-64-P10-NEXT:    li 4, 1
916; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
917; CHECK-64-P10-NEXT:    lfdx 0, 3, 4
918; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
919; CHECK-64-P10-NEXT:    blr
920;
921; CHECK-32-P10-LABEL: testDoubleImm5:
922; CHECK-32-P10:       # %bb.0: # %entry
923; CHECK-32-P10-NEXT:    lfd 0, 0(3)
924; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
925; CHECK-32-P10-NEXT:    blr
926entry:
927  %add.ptr = getelementptr inbounds i32, i32* %b, i64 68719476736
928  %0 = bitcast i32* %add.ptr to double*
929  %1 = load double, double* %0, align 8
930  %vecins = insertelement <2 x double> %a, double %1, i32 0
931  ret <2 x double> %vecins
932}
933
934