1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
3; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10
5; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10
6
7; Byte indexed
8
9define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) {
10; CHECK-64-LABEL: testByte:
11; CHECK-64:       # %bb.0: # %entry
12; CHECK-64-NEXT:    addi 5, 1, -16
13; CHECK-64-NEXT:    clrldi 4, 4, 60
14; CHECK-64-NEXT:    stxv 34, -16(1)
15; CHECK-64-NEXT:    stbx 3, 5, 4
16; CHECK-64-NEXT:    lxv 34, -16(1)
17; CHECK-64-NEXT:    blr
18;
19; CHECK-32-LABEL: testByte:
20; CHECK-32:       # %bb.0: # %entry
21; CHECK-32-NEXT:    addi 5, 1, -16
22; CHECK-32-NEXT:    clrlwi 3, 6, 28
23; CHECK-32-NEXT:    stxv 34, -16(1)
24; CHECK-32-NEXT:    stbx 4, 5, 3
25; CHECK-32-NEXT:    lxv 34, -16(1)
26; CHECK-32-NEXT:    blr
27;
28; CHECK-64-P10-LABEL: testByte:
29; CHECK-64-P10:       # %bb.0: # %entry
30; CHECK-64-P10-NEXT:    vinsblx 2, 4, 3
31; CHECK-64-P10-NEXT:    blr
32;
33; CHECK-32-P10-LABEL: testByte:
34; CHECK-32-P10:       # %bb.0: # %entry
35; CHECK-32-P10-NEXT:    vinsblx 2, 6, 4
36; CHECK-32-P10-NEXT:    blr
37entry:
38  %conv = trunc i64 %b to i8
39  %vecins = insertelement <16 x i8> %a, i8 %conv, i64 %idx
40  ret <16 x i8> %vecins
41}
42
43; Halfword indexed
44
45define <8 x i16> @testHalf(<8 x i16> %a, i64 %b, i64 %idx) {
46; CHECK-64-LABEL: testHalf:
47; CHECK-64:       # %bb.0: # %entry
48; CHECK-64-NEXT:    addi 5, 1, -16
49; CHECK-64-NEXT:    rlwinm 4, 4, 1, 28, 30
50; CHECK-64-NEXT:    stxv 34, -16(1)
51; CHECK-64-NEXT:    sthx 3, 5, 4
52; CHECK-64-NEXT:    lxv 34, -16(1)
53; CHECK-64-NEXT:    blr
54;
55; CHECK-32-LABEL: testHalf:
56; CHECK-32:       # %bb.0: # %entry
57; CHECK-32-NEXT:    addi 5, 1, -16
58; CHECK-32-NEXT:    rlwinm 3, 6, 1, 28, 30
59; CHECK-32-NEXT:    stxv 34, -16(1)
60; CHECK-32-NEXT:    sthx 4, 5, 3
61; CHECK-32-NEXT:    lxv 34, -16(1)
62; CHECK-32-NEXT:    blr
63;
64; CHECK-64-P10-LABEL: testHalf:
65; CHECK-64-P10:       # %bb.0: # %entry
66; CHECK-64-P10-NEXT:    slwi 4, 4, 1
67; CHECK-64-P10-NEXT:    vinshlx 2, 4, 3
68; CHECK-64-P10-NEXT:    blr
69;
70; CHECK-32-P10-LABEL: testHalf:
71; CHECK-32-P10:       # %bb.0: # %entry
72; CHECK-32-P10-NEXT:    vinshlx 2, 6, 4
73; CHECK-32-P10-NEXT:    blr
74entry:
75  %conv = trunc i64 %b to i16
76  %vecins = insertelement <8 x i16> %a, i16 %conv, i64 %idx
77  ret <8 x i16> %vecins
78}
79
80; Word indexed
81
82define <4 x i32> @testWord(<4 x i32> %a, i64 %b, i64 %idx) {
83; CHECK-64-LABEL: testWord:
84; CHECK-64:       # %bb.0: # %entry
85; CHECK-64-NEXT:    addi 5, 1, -16
86; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
87; CHECK-64-NEXT:    stxv 34, -16(1)
88; CHECK-64-NEXT:    stwx 3, 5, 4
89; CHECK-64-NEXT:    lxv 34, -16(1)
90; CHECK-64-NEXT:    blr
91;
92; CHECK-32-LABEL: testWord:
93; CHECK-32:       # %bb.0: # %entry
94; CHECK-32-NEXT:    addi 5, 1, -16
95; CHECK-32-NEXT:    rlwinm 3, 6, 2, 28, 29
96; CHECK-32-NEXT:    stxv 34, -16(1)
97; CHECK-32-NEXT:    stwx 4, 5, 3
98; CHECK-32-NEXT:    lxv 34, -16(1)
99; CHECK-32-NEXT:    blr
100;
101; CHECK-64-P10-LABEL: testWord:
102; CHECK-64-P10:       # %bb.0: # %entry
103; CHECK-64-P10-NEXT:    slwi 4, 4, 2
104; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
105; CHECK-64-P10-NEXT:    blr
106;
107; CHECK-32-P10-LABEL: testWord:
108; CHECK-32-P10:       # %bb.0: # %entry
109; CHECK-32-P10-NEXT:    vinswlx 2, 6, 4
110; CHECK-32-P10-NEXT:    blr
111entry:
112  %conv = trunc i64 %b to i32
113  %vecins = insertelement <4 x i32> %a, i32 %conv, i64 %idx
114  ret <4 x i32> %vecins
115}
116
117; Word immediate
118
119define <4 x i32> @testWordImm(<4 x i32> %a, i64 %b) {
120; CHECK-64-LABEL: testWordImm:
121; CHECK-64:       # %bb.0: # %entry
122; CHECK-64-NEXT:    mtfprwz 0, 3
123; CHECK-64-NEXT:    xxinsertw 34, 0, 4
124; CHECK-64-NEXT:    xxinsertw 34, 0, 12
125; CHECK-64-NEXT:    blr
126;
127; CHECK-32-LABEL: testWordImm:
128; CHECK-32:       # %bb.0: # %entry
129; CHECK-32-NEXT:    mtfprwz 0, 4
130; CHECK-32-NEXT:    xxinsertw 34, 0, 4
131; CHECK-32-NEXT:    xxinsertw 34, 0, 12
132; CHECK-32-NEXT:    blr
133;
134; CHECK-64-P10-LABEL: testWordImm:
135; CHECK-64-P10:       # %bb.0: # %entry
136; CHECK-64-P10-NEXT:    vinsw 2, 3, 4
137; CHECK-64-P10-NEXT:    vinsw 2, 3, 12
138; CHECK-64-P10-NEXT:    blr
139;
140; CHECK-32-P10-LABEL: testWordImm:
141; CHECK-32-P10:       # %bb.0: # %entry
142; CHECK-32-P10-NEXT:    vinsw 2, 4, 4
143; CHECK-32-P10-NEXT:    vinsw 2, 4, 12
144; CHECK-32-P10-NEXT:    blr
145entry:
146  %conv = trunc i64 %b to i32
147  %vecins = insertelement <4 x i32> %a, i32 %conv, i32 1
148  %vecins2 = insertelement <4 x i32> %vecins, i32 %conv, i32 3
149  ret <4 x i32> %vecins2
150}
151
152; Doubleword indexed
153
154define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
155; CHECK-64-LABEL: testDoubleword:
156; CHECK-64:       # %bb.0: # %entry
157; CHECK-64-NEXT:    addi 5, 1, -16
158; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
159; CHECK-64-NEXT:    stxv 34, -16(1)
160; CHECK-64-NEXT:    stdx 3, 5, 4
161; CHECK-64-NEXT:    lxv 34, -16(1)
162; CHECK-64-NEXT:    blr
163;
164; CHECK-32-LABEL: testDoubleword:
165; CHECK-32:       # %bb.0: # %entry
166; CHECK-32-NEXT:    add 5, 6, 6
167; CHECK-32-NEXT:    addi 7, 1, -32
168; CHECK-32-NEXT:    stxv 34, -32(1)
169; CHECK-32-NEXT:    rlwinm 6, 5, 2, 28, 29
170; CHECK-32-NEXT:    stwx 3, 7, 6
171; CHECK-32-NEXT:    addi 3, 5, 1
172; CHECK-32-NEXT:    addi 5, 1, -16
173; CHECK-32-NEXT:    lxv 0, -32(1)
174; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
175; CHECK-32-NEXT:    stxv 0, -16(1)
176; CHECK-32-NEXT:    stwx 4, 5, 3
177; CHECK-32-NEXT:    lxv 34, -16(1)
178; CHECK-32-NEXT:    blr
179;
180; CHECK-64-P10-LABEL: testDoubleword:
181; CHECK-64-P10:       # %bb.0: # %entry
182; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
183; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
184; CHECK-64-P10-NEXT:    blr
185;
186; CHECK-32-P10-LABEL: testDoubleword:
187; CHECK-32-P10:       # %bb.0: # %entry
188; CHECK-32-P10-NEXT:    add 5, 6, 6
189; CHECK-32-P10-NEXT:    vinswlx 2, 5, 3
190; CHECK-32-P10-NEXT:    addi 3, 5, 1
191; CHECK-32-P10-NEXT:    vinswlx 2, 3, 4
192; CHECK-32-P10-NEXT:    blr
193entry:
194  %vecins = insertelement <2 x i64> %a, i64 %b, i64 %idx
195  ret <2 x i64> %vecins
196}
197
198; Doubleword immediate
199
200define <2 x i64> @testDoublewordImm(<2 x i64> %a, i64 %b) {
201; CHECK-64-LABEL: testDoublewordImm:
202; CHECK-64:       # %bb.0: # %entry
203; CHECK-64-NEXT:    mtfprd 0, 3
204; CHECK-64-NEXT:    xxmrghd 34, 34, 0
205; CHECK-64-NEXT:    blr
206;
207; CHECK-32-LABEL: testDoublewordImm:
208; CHECK-32:       # %bb.0: # %entry
209; CHECK-32-NEXT:    mtfprwz 0, 3
210; CHECK-32-NEXT:    xxinsertw 34, 0, 8
211; CHECK-32-NEXT:    mtfprwz 0, 4
212; CHECK-32-NEXT:    xxinsertw 34, 0, 12
213; CHECK-32-NEXT:    blr
214;
215; CHECK-64-P10-LABEL: testDoublewordImm:
216; CHECK-64-P10:       # %bb.0: # %entry
217; CHECK-64-P10-NEXT:    vinsd 2, 3, 8
218; CHECK-64-P10-NEXT:    blr
219;
220; CHECK-32-P10-LABEL: testDoublewordImm:
221; CHECK-32-P10:       # %bb.0: # %entry
222; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
223; CHECK-32-P10-NEXT:    vinsw 2, 4, 12
224; CHECK-32-P10-NEXT:    blr
225entry:
226  %vecins = insertelement <2 x i64> %a, i64 %b, i32 1
227  ret <2 x i64> %vecins
228}
229
230define <2 x i64> @testDoublewordImm2(<2 x i64> %a, i64 %b) {
231; CHECK-64-LABEL: testDoublewordImm2:
232; CHECK-64:       # %bb.0: # %entry
233; CHECK-64-NEXT:    mtfprd 0, 3
234; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
235; CHECK-64-NEXT:    blr
236;
237; CHECK-32-LABEL: testDoublewordImm2:
238; CHECK-32:       # %bb.0: # %entry
239; CHECK-32-NEXT:    mtfprwz 0, 3
240; CHECK-32-NEXT:    xxinsertw 34, 0, 0
241; CHECK-32-NEXT:    mtfprwz 0, 4
242; CHECK-32-NEXT:    xxinsertw 34, 0, 4
243; CHECK-32-NEXT:    blr
244;
245; CHECK-64-P10-LABEL: testDoublewordImm2:
246; CHECK-64-P10:       # %bb.0: # %entry
247; CHECK-64-P10-NEXT:    vinsd 2, 3, 0
248; CHECK-64-P10-NEXT:    blr
249;
250; CHECK-32-P10-LABEL: testDoublewordImm2:
251; CHECK-32-P10:       # %bb.0: # %entry
252; CHECK-32-P10-NEXT:    vinsw 2, 3, 0
253; CHECK-32-P10-NEXT:    vinsw 2, 4, 4
254; CHECK-32-P10-NEXT:    blr
255entry:
256  %vecins = insertelement <2 x i64> %a, i64 %b, i32 0
257  ret <2 x i64> %vecins
258}
259
260; Float indexed
261
262define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
263; CHECK-64-LABEL: testFloat1:
264; CHECK-64:       # %bb.0: # %entry
265; CHECK-64-NEXT:    rlwinm 3, 4, 2, 28, 29
266; CHECK-64-NEXT:    addi 4, 1, -16
267; CHECK-64-NEXT:    stxv 34, -16(1)
268; CHECK-64-NEXT:    stfsx 1, 4, 3
269; CHECK-64-NEXT:    lxv 34, -16(1)
270; CHECK-64-NEXT:    blr
271;
272; CHECK-32-LABEL: testFloat1:
273; CHECK-32:       # %bb.0: # %entry
274; CHECK-32-NEXT:    rlwinm 3, 4, 2, 28, 29
275; CHECK-32-NEXT:    addi 4, 1, -16
276; CHECK-32-NEXT:    stxv 34, -16(1)
277; CHECK-32-NEXT:    stfsx 1, 4, 3
278; CHECK-32-NEXT:    lxv 34, -16(1)
279; CHECK-32-NEXT:    blr
280;
281; CHECK-64-P10-LABEL: testFloat1:
282; CHECK-64-P10:       # %bb.0: # %entry
283; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
284; CHECK-64-P10-NEXT:    extsw 3, 4
285; CHECK-64-P10-NEXT:    slwi 3, 3, 2
286; CHECK-64-P10-NEXT:    xxsldwi 0, 0, 0, 3
287; CHECK-64-P10-NEXT:    mffprwz 4, 0
288; CHECK-64-P10-NEXT:    vinswlx 2, 3, 4
289; CHECK-64-P10-NEXT:    blr
290;
291; CHECK-32-P10-LABEL: testFloat1:
292; CHECK-32-P10:       # %bb.0: # %entry
293; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
294; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
295; CHECK-32-P10-NEXT:    mffprwz 3, 0
296; CHECK-32-P10-NEXT:    vinswlx 2, 4, 3
297; CHECK-32-P10-NEXT:    blr
298entry:
299  %vecins = insertelement <4 x float> %a, float %b, i32 %idx1
300  ret <4 x float> %vecins
301}
302
303define <4 x float> @testFloat2(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
304; CHECK-64-LABEL: testFloat2:
305; CHECK-64:       # %bb.0: # %entry
306; CHECK-64-NEXT:    lwz 6, 0(3)
307; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
308; CHECK-64-NEXT:    addi 7, 1, -32
309; CHECK-64-NEXT:    stxv 34, -32(1)
310; CHECK-64-NEXT:    stwx 6, 7, 4
311; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
312; CHECK-64-NEXT:    addi 5, 1, -16
313; CHECK-64-NEXT:    lxv 0, -32(1)
314; CHECK-64-NEXT:    lwz 3, 1(3)
315; CHECK-64-NEXT:    stxv 0, -16(1)
316; CHECK-64-NEXT:    stwx 3, 5, 4
317; CHECK-64-NEXT:    lxv 34, -16(1)
318; CHECK-64-NEXT:    blr
319;
320; CHECK-32-LABEL: testFloat2:
321; CHECK-32:       # %bb.0: # %entry
322; CHECK-32-NEXT:    lwz 6, 0(3)
323; CHECK-32-NEXT:    addi 7, 1, -32
324; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
325; CHECK-32-NEXT:    stxv 34, -32(1)
326; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
327; CHECK-32-NEXT:    stwx 6, 7, 4
328; CHECK-32-NEXT:    addi 4, 1, -16
329; CHECK-32-NEXT:    lxv 0, -32(1)
330; CHECK-32-NEXT:    lwz 3, 1(3)
331; CHECK-32-NEXT:    stxv 0, -16(1)
332; CHECK-32-NEXT:    stwx 3, 4, 5
333; CHECK-32-NEXT:    lxv 34, -16(1)
334; CHECK-32-NEXT:    blr
335;
336; CHECK-64-P10-LABEL: testFloat2:
337; CHECK-64-P10:       # %bb.0: # %entry
338; CHECK-64-P10-NEXT:    lwz 6, 0(3)
339; CHECK-64-P10-NEXT:    extsw 4, 4
340; CHECK-64-P10-NEXT:    lwz 3, 1(3)
341; CHECK-64-P10-NEXT:    slwi 4, 4, 2
342; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
343; CHECK-64-P10-NEXT:    extsw 4, 5
344; CHECK-64-P10-NEXT:    slwi 4, 4, 2
345; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
346; CHECK-64-P10-NEXT:    blr
347;
348; CHECK-32-P10-LABEL: testFloat2:
349; CHECK-32-P10:       # %bb.0: # %entry
350; CHECK-32-P10-NEXT:    lwz 6, 0(3)
351; CHECK-32-P10-NEXT:    lwz 3, 1(3)
352; CHECK-32-P10-NEXT:    vinswlx 2, 4, 6
353; CHECK-32-P10-NEXT:    vinswlx 2, 5, 3
354; CHECK-32-P10-NEXT:    blr
355entry:
356  %0 = bitcast i8* %b to float*
357  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
358  %1 = bitcast i8* %add.ptr1 to float*
359  %2 = load float, float* %0, align 4
360  %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
361  %3 = load float, float* %1, align 4
362  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
363  ret <4 x float> %vecins2
364}
365
366define <4 x float> @testFloat3(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
367; CHECK-64-LABEL: testFloat3:
368; CHECK-64:       # %bb.0: # %entry
369; CHECK-64-NEXT:    lis 6, 1
370; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
371; CHECK-64-NEXT:    addi 7, 1, -32
372; CHECK-64-NEXT:    lwzx 6, 3, 6
373; CHECK-64-NEXT:    stxv 34, -32(1)
374; CHECK-64-NEXT:    stwx 6, 7, 4
375; CHECK-64-NEXT:    li 4, 1
376; CHECK-64-NEXT:    lxv 0, -32(1)
377; CHECK-64-NEXT:    rldic 4, 4, 36, 27
378; CHECK-64-NEXT:    lwzx 3, 3, 4
379; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
380; CHECK-64-NEXT:    addi 5, 1, -16
381; CHECK-64-NEXT:    stxv 0, -16(1)
382; CHECK-64-NEXT:    stwx 3, 5, 4
383; CHECK-64-NEXT:    lxv 34, -16(1)
384; CHECK-64-NEXT:    blr
385;
386; CHECK-32-LABEL: testFloat3:
387; CHECK-32:       # %bb.0: # %entry
388; CHECK-32-NEXT:    lis 6, 1
389; CHECK-32-NEXT:    addi 7, 1, -32
390; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
391; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
392; CHECK-32-NEXT:    lwzx 6, 3, 6
393; CHECK-32-NEXT:    stxv 34, -32(1)
394; CHECK-32-NEXT:    stwx 6, 7, 4
395; CHECK-32-NEXT:    addi 4, 1, -16
396; CHECK-32-NEXT:    lxv 0, -32(1)
397; CHECK-32-NEXT:    lwz 3, 0(3)
398; CHECK-32-NEXT:    stxv 0, -16(1)
399; CHECK-32-NEXT:    stwx 3, 4, 5
400; CHECK-32-NEXT:    lxv 34, -16(1)
401; CHECK-32-NEXT:    blr
402;
403; CHECK-64-P10-LABEL: testFloat3:
404; CHECK-64-P10:       # %bb.0: # %entry
405; CHECK-64-P10-NEXT:    plwz 6, 65536(3), 0
406; CHECK-64-P10-NEXT:    extsw 4, 4
407; CHECK-64-P10-NEXT:    slwi 4, 4, 2
408; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
409; CHECK-64-P10-NEXT:    li 4, 1
410; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
411; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
412; CHECK-64-P10-NEXT:    extsw 4, 5
413; CHECK-64-P10-NEXT:    slwi 4, 4, 2
414; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
415; CHECK-64-P10-NEXT:    blr
416;
417; CHECK-32-P10-LABEL: testFloat3:
418; CHECK-32-P10:       # %bb.0: # %entry
419; CHECK-32-P10-NEXT:    lis 6, 1
420; CHECK-32-P10-NEXT:    lwzx 6, 3, 6
421; CHECK-32-P10-NEXT:    lwz 3, 0(3)
422; CHECK-32-P10-NEXT:    vinswlx 2, 4, 6
423; CHECK-32-P10-NEXT:    vinswlx 2, 5, 3
424; CHECK-32-P10-NEXT:    blr
425entry:
426  %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
427  %0 = bitcast i8* %add.ptr to float*
428  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
429  %1 = bitcast i8* %add.ptr1 to float*
430  %2 = load float, float* %0, align 4
431  %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
432  %3 = load float, float* %1, align 4
433  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
434  ret <4 x float> %vecins2
435}
436
437; Float immediate
438
439define <4 x float> @testFloatImm1(<4 x float> %a, float %b) {
440; CHECK-64-LABEL: testFloatImm1:
441; CHECK-64:       # %bb.0: # %entry
442; CHECK-64-NEXT:    xscvdpspn 0, 1
443; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
444; CHECK-64-NEXT:    xxinsertw 34, 0, 0
445; CHECK-64-NEXT:    xxinsertw 34, 0, 8
446; CHECK-64-NEXT:    blr
447;
448; CHECK-32-LABEL: testFloatImm1:
449; CHECK-32:       # %bb.0: # %entry
450; CHECK-32-NEXT:    xscvdpspn 0, 1
451; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
452; CHECK-32-NEXT:    xxinsertw 34, 0, 0
453; CHECK-32-NEXT:    xxinsertw 34, 0, 8
454; CHECK-32-NEXT:    blr
455;
456; CHECK-64-P10-LABEL: testFloatImm1:
457; CHECK-64-P10:       # %bb.0: # %entry
458; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
459; CHECK-64-P10-NEXT:    xxsldwi 0, 0, 0, 3
460; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 0
461; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 8
462; CHECK-64-P10-NEXT:    blr
463;
464; CHECK-32-P10-LABEL: testFloatImm1:
465; CHECK-32-P10:       # %bb.0: # %entry
466; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
467; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
468; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
469; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
470; CHECK-32-P10-NEXT:    blr
471entry:
472  %vecins = insertelement <4 x float> %a, float %b, i32 0
473  %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2
474  ret <4 x float> %vecins1
475}
476
477define <4 x float> @testFloatImm2(<4 x float> %a, i32* %b) {
478; CHECK-64-LABEL: testFloatImm2:
479; CHECK-64:       # %bb.0: # %entry
480; CHECK-64-NEXT:    lfs 0, 0(3)
481; CHECK-64-NEXT:    xscvdpspn 0, 0
482; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
483; CHECK-64-NEXT:    xxinsertw 34, 0, 0
484; CHECK-64-NEXT:    lfs 0, 4(3)
485; CHECK-64-NEXT:    xscvdpspn 0, 0
486; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
487; CHECK-64-NEXT:    xxinsertw 34, 0, 8
488; CHECK-64-NEXT:    blr
489;
490; CHECK-32-LABEL: testFloatImm2:
491; CHECK-32:       # %bb.0: # %entry
492; CHECK-32-NEXT:    lfs 0, 0(3)
493; CHECK-32-NEXT:    xscvdpspn 0, 0
494; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
495; CHECK-32-NEXT:    xxinsertw 34, 0, 0
496; CHECK-32-NEXT:    lfs 0, 4(3)
497; CHECK-32-NEXT:    xscvdpspn 0, 0
498; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
499; CHECK-32-NEXT:    xxinsertw 34, 0, 8
500; CHECK-32-NEXT:    blr
501;
502; CHECK-64-P10-LABEL: testFloatImm2:
503; CHECK-64-P10:       # %bb.0: # %entry
504; CHECK-64-P10-NEXT:    lwz 4, 0(3)
505; CHECK-64-P10-NEXT:    lwz 3, 4(3)
506; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
507; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
508; CHECK-64-P10-NEXT:    blr
509;
510; CHECK-32-P10-LABEL: testFloatImm2:
511; CHECK-32-P10:       # %bb.0: # %entry
512; CHECK-32-P10-NEXT:    lwz 4, 0(3)
513; CHECK-32-P10-NEXT:    lwz 3, 4(3)
514; CHECK-32-P10-NEXT:    vinsw 2, 4, 0
515; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
516; CHECK-32-P10-NEXT:    blr
517entry:
518  %0 = bitcast i32* %b to float*
519  %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 1
520  %1 = bitcast i32* %add.ptr1 to float*
521  %2 = load float, float* %0, align 4
522  %vecins = insertelement <4 x float> %a, float %2, i32 0
523  %3 = load float, float* %1, align 4
524  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2
525  ret <4 x float> %vecins2
526}
527
528define <4 x float> @testFloatImm3(<4 x float> %a, i32* %b) {
529; CHECK-64-LABEL: testFloatImm3:
530; CHECK-64:       # %bb.0: # %entry
531; CHECK-64-NEXT:    lis 4, 4
532; CHECK-64-NEXT:    lfsx 0, 3, 4
533; CHECK-64-NEXT:    li 4, 1
534; CHECK-64-NEXT:    rldic 4, 4, 38, 25
535; CHECK-64-NEXT:    xscvdpspn 0, 0
536; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
537; CHECK-64-NEXT:    xxinsertw 34, 0, 0
538; CHECK-64-NEXT:    lfsx 0, 3, 4
539; CHECK-64-NEXT:    xscvdpspn 0, 0
540; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
541; CHECK-64-NEXT:    xxinsertw 34, 0, 8
542; CHECK-64-NEXT:    blr
543;
544; CHECK-32-LABEL: testFloatImm3:
545; CHECK-32:       # %bb.0: # %entry
546; CHECK-32-NEXT:    lis 4, 4
547; CHECK-32-NEXT:    lfsx 0, 3, 4
548; CHECK-32-NEXT:    xscvdpspn 0, 0
549; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
550; CHECK-32-NEXT:    xxinsertw 34, 0, 0
551; CHECK-32-NEXT:    lfs 0, 0(3)
552; CHECK-32-NEXT:    xscvdpspn 0, 0
553; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
554; CHECK-32-NEXT:    xxinsertw 34, 0, 8
555; CHECK-32-NEXT:    blr
556;
557; CHECK-64-P10-LABEL: testFloatImm3:
558; CHECK-64-P10:       # %bb.0: # %entry
559; CHECK-64-P10-NEXT:    plwz 4, 262144(3), 0
560; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
561; CHECK-64-P10-NEXT:    li 4, 1
562; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
563; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
564; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
565; CHECK-64-P10-NEXT:    blr
566;
567; CHECK-32-P10-LABEL: testFloatImm3:
568; CHECK-32-P10:       # %bb.0: # %entry
569; CHECK-32-P10-NEXT:    lis 4, 4
570; CHECK-32-P10-NEXT:    lwzx 4, 3, 4
571; CHECK-32-P10-NEXT:    lwz 3, 0(3)
572; CHECK-32-P10-NEXT:    vinsw 2, 4, 0
573; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
574; CHECK-32-P10-NEXT:    blr
575entry:
576  %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
577  %0 = bitcast i32* %add.ptr to float*
578  %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736
579  %1 = bitcast i32* %add.ptr1 to float*
580  %2 = load float, float* %0, align 4
581  %vecins = insertelement <4 x float> %a, float %2, i32 0
582  %3 = load float, float* %1, align 4
583  %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2
584  ret <4 x float> %vecins2
585}
586
587; Double indexed
588
589define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) {
590; CHECK-64-LABEL: testDouble1:
591; CHECK-64:       # %bb.0: # %entry
592; CHECK-64-NEXT:    rlwinm 3, 4, 3, 28, 28
593; CHECK-64-NEXT:    addi 4, 1, -16
594; CHECK-64-NEXT:    stxv 34, -16(1)
595; CHECK-64-NEXT:    stfdx 1, 4, 3
596; CHECK-64-NEXT:    lxv 34, -16(1)
597; CHECK-64-NEXT:    blr
598;
599; CHECK-32-LABEL: testDouble1:
600; CHECK-32:       # %bb.0: # %entry
601; CHECK-32-NEXT:    addi 4, 1, -16
602; CHECK-32-NEXT:    rlwinm 3, 5, 3, 28, 28
603; CHECK-32-NEXT:    stxv 34, -16(1)
604; CHECK-32-NEXT:    stfdx 1, 4, 3
605; CHECK-32-NEXT:    lxv 34, -16(1)
606; CHECK-32-NEXT:    blr
607;
608; CHECK-64-P10-LABEL: testDouble1:
609; CHECK-64-P10:       # %bb.0: # %entry
610; CHECK-64-P10-NEXT:    extsw 4, 4
611; CHECK-64-P10-NEXT:    mffprd 3, 1
612; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
613; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
614; CHECK-64-P10-NEXT:    blr
615;
616; CHECK-32-P10-LABEL: testDouble1:
617; CHECK-32-P10:       # %bb.0: # %entry
618; CHECK-32-P10-NEXT:    addi 4, 1, -16
619; CHECK-32-P10-NEXT:    rlwinm 3, 5, 3, 28, 28
620; CHECK-32-P10-NEXT:    stxv 34, -16(1)
621; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
622; CHECK-32-P10-NEXT:    lxv 34, -16(1)
623; CHECK-32-P10-NEXT:    blr
624entry:
625  %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
626  ret <2 x double> %vecins
627}
628
629define <2 x double> @testDouble2(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
630; CHECK-64-LABEL: testDouble2:
631; CHECK-64:       # %bb.0: # %entry
632; CHECK-64-NEXT:    ld 6, 0(3)
633; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
634; CHECK-64-NEXT:    addi 7, 1, -32
635; CHECK-64-NEXT:    stxv 34, -32(1)
636; CHECK-64-NEXT:    stdx 6, 7, 4
637; CHECK-64-NEXT:    li 4, 1
638; CHECK-64-NEXT:    lxv 0, -32(1)
639; CHECK-64-NEXT:    ldx 3, 3, 4
640; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
641; CHECK-64-NEXT:    addi 5, 1, -16
642; CHECK-64-NEXT:    stxv 0, -16(1)
643; CHECK-64-NEXT:    stdx 3, 5, 4
644; CHECK-64-NEXT:    lxv 34, -16(1)
645; CHECK-64-NEXT:    blr
646;
647; CHECK-32-LABEL: testDouble2:
648; CHECK-32:       # %bb.0: # %entry
649; CHECK-32-NEXT:    lfd 0, 0(3)
650; CHECK-32-NEXT:    addi 6, 1, -32
651; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
652; CHECK-32-NEXT:    stxv 34, -32(1)
653; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
654; CHECK-32-NEXT:    stfdx 0, 6, 4
655; CHECK-32-NEXT:    lxv 0, -32(1)
656; CHECK-32-NEXT:    lfd 1, 1(3)
657; CHECK-32-NEXT:    addi 3, 1, -16
658; CHECK-32-NEXT:    stxv 0, -16(1)
659; CHECK-32-NEXT:    stfdx 1, 3, 5
660; CHECK-32-NEXT:    lxv 34, -16(1)
661; CHECK-32-NEXT:    blr
662;
663; CHECK-64-P10-LABEL: testDouble2:
664; CHECK-64-P10:       # %bb.0: # %entry
665; CHECK-64-P10-NEXT:    ld 6, 0(3)
666; CHECK-64-P10-NEXT:    extsw 4, 4
667; CHECK-64-P10-NEXT:    pld 3, 1(3), 0
668; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
669; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
670; CHECK-64-P10-NEXT:    extsw 4, 5
671; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
672; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
673; CHECK-64-P10-NEXT:    blr
674;
675; CHECK-32-P10-LABEL: testDouble2:
676; CHECK-32-P10:       # %bb.0: # %entry
677; CHECK-32-P10-NEXT:    lfd 0, 0(3)
678; CHECK-32-P10-NEXT:    addi 6, 1, -32
679; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
680; CHECK-32-P10-NEXT:    stxv 34, -32(1)
681; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
682; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
683; CHECK-32-P10-NEXT:    lxv 0, -32(1)
684; CHECK-32-P10-NEXT:    lfd 1, 1(3)
685; CHECK-32-P10-NEXT:    addi 3, 1, -16
686; CHECK-32-P10-NEXT:    stxv 0, -16(1)
687; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
688; CHECK-32-P10-NEXT:    lxv 34, -16(1)
689; CHECK-32-P10-NEXT:    blr
690entry:
691  %0 = bitcast i8* %b to double*
692  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
693  %1 = bitcast i8* %add.ptr1 to double*
694  %2 = load double, double* %0, align 8
695  %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
696  %3 = load double, double* %1, align 8
697  %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
698  ret <2 x double> %vecins2
699}
700
701define <2 x double> @testDouble3(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
702; CHECK-64-LABEL: testDouble3:
703; CHECK-64:       # %bb.0: # %entry
704; CHECK-64-NEXT:    lis 6, 1
705; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
706; CHECK-64-NEXT:    addi 7, 1, -32
707; CHECK-64-NEXT:    ldx 6, 3, 6
708; CHECK-64-NEXT:    stxv 34, -32(1)
709; CHECK-64-NEXT:    stdx 6, 7, 4
710; CHECK-64-NEXT:    li 4, 1
711; CHECK-64-NEXT:    lxv 0, -32(1)
712; CHECK-64-NEXT:    rldic 4, 4, 36, 27
713; CHECK-64-NEXT:    ldx 3, 3, 4
714; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
715; CHECK-64-NEXT:    addi 5, 1, -16
716; CHECK-64-NEXT:    stxv 0, -16(1)
717; CHECK-64-NEXT:    stdx 3, 5, 4
718; CHECK-64-NEXT:    lxv 34, -16(1)
719; CHECK-64-NEXT:    blr
720;
721; CHECK-32-LABEL: testDouble3:
722; CHECK-32:       # %bb.0: # %entry
723; CHECK-32-NEXT:    lis 6, 1
724; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
725; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
726; CHECK-32-NEXT:    lfdx 0, 3, 6
727; CHECK-32-NEXT:    addi 6, 1, -32
728; CHECK-32-NEXT:    stxv 34, -32(1)
729; CHECK-32-NEXT:    stfdx 0, 6, 4
730; CHECK-32-NEXT:    lxv 0, -32(1)
731; CHECK-32-NEXT:    lfd 1, 0(3)
732; CHECK-32-NEXT:    addi 3, 1, -16
733; CHECK-32-NEXT:    stxv 0, -16(1)
734; CHECK-32-NEXT:    stfdx 1, 3, 5
735; CHECK-32-NEXT:    lxv 34, -16(1)
736; CHECK-32-NEXT:    blr
737;
738; CHECK-64-P10-LABEL: testDouble3:
739; CHECK-64-P10:       # %bb.0: # %entry
740; CHECK-64-P10-NEXT:    pld 6, 65536(3), 0
741; CHECK-64-P10-NEXT:    extsw 4, 4
742; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
743; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
744; CHECK-64-P10-NEXT:    li 4, 1
745; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
746; CHECK-64-P10-NEXT:    ldx 3, 3, 4
747; CHECK-64-P10-NEXT:    extsw 4, 5
748; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
749; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
750; CHECK-64-P10-NEXT:    blr
751;
752; CHECK-32-P10-LABEL: testDouble3:
753; CHECK-32-P10:       # %bb.0: # %entry
754; CHECK-32-P10-NEXT:    lis 6, 1
755; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
756; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
757; CHECK-32-P10-NEXT:    lfdx 0, 3, 6
758; CHECK-32-P10-NEXT:    addi 6, 1, -32
759; CHECK-32-P10-NEXT:    stxv 34, -32(1)
760; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
761; CHECK-32-P10-NEXT:    lxv 0, -32(1)
762; CHECK-32-P10-NEXT:    lfd 1, 0(3)
763; CHECK-32-P10-NEXT:    addi 3, 1, -16
764; CHECK-32-P10-NEXT:    stxv 0, -16(1)
765; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
766; CHECK-32-P10-NEXT:    lxv 34, -16(1)
767; CHECK-32-P10-NEXT:    blr
768entry:
769  %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
770  %0 = bitcast i8* %add.ptr to double*
771  %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
772  %1 = bitcast i8* %add.ptr1 to double*
773  %2 = load double, double* %0, align 8
774  %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
775  %3 = load double, double* %1, align 8
776  %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
777  ret <2 x double> %vecins2
778}
779
780; Double immediate
781
782define <2 x double> @testDoubleImm1(<2 x double> %a, double %b) {
783; CHECK-64-LABEL: testDoubleImm1:
784; CHECK-64:       # %bb.0: # %entry
785; CHECK-64-NEXT:    # kill: def $f1 killed $f1 def $vsl1
786; CHECK-64-NEXT:    xxpermdi 34, 1, 34, 1
787; CHECK-64-NEXT:    blr
788;
789; CHECK-32-LABEL: testDoubleImm1:
790; CHECK-32:       # %bb.0: # %entry
791; CHECK-32-NEXT:    # kill: def $f1 killed $f1 def $vsl1
792; CHECK-32-NEXT:    xxpermdi 34, 1, 34, 1
793; CHECK-32-NEXT:    blr
794;
795; CHECK-64-P10-LABEL: testDoubleImm1:
796; CHECK-64-P10:       # %bb.0: # %entry
797; CHECK-64-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
798; CHECK-64-P10-NEXT:    xxpermdi 34, 1, 34, 1
799; CHECK-64-P10-NEXT:    blr
800;
801; CHECK-32-P10-LABEL: testDoubleImm1:
802; CHECK-32-P10:       # %bb.0: # %entry
803; CHECK-32-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
804; CHECK-32-P10-NEXT:    xxpermdi 34, 1, 34, 1
805; CHECK-32-P10-NEXT:    blr
806entry:
807  %vecins = insertelement <2 x double> %a, double %b, i32 0
808  ret <2 x double> %vecins
809}
810
811define <2 x double> @testDoubleImm2(<2 x double> %a, i32* %b) {
812; CHECK-64-LABEL: testDoubleImm2:
813; CHECK-64:       # %bb.0: # %entry
814; CHECK-64-NEXT:    lfd 0, 0(3)
815; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
816; CHECK-64-NEXT:    blr
817;
818; CHECK-32-LABEL: testDoubleImm2:
819; CHECK-32:       # %bb.0: # %entry
820; CHECK-32-NEXT:    lfd 0, 0(3)
821; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
822; CHECK-32-NEXT:    blr
823;
824; CHECK-64-P10-LABEL: testDoubleImm2:
825; CHECK-64-P10:       # %bb.0: # %entry
826; CHECK-64-P10-NEXT:    lfd 0, 0(3)
827; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
828; CHECK-64-P10-NEXT:    blr
829;
830; CHECK-32-P10-LABEL: testDoubleImm2:
831; CHECK-32-P10:       # %bb.0: # %entry
832; CHECK-32-P10-NEXT:    lfd 0, 0(3)
833; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
834; CHECK-32-P10-NEXT:    blr
835entry:
836  %0 = bitcast i32* %b to double*
837  %1 = load double, double* %0, align 8
838  %vecins = insertelement <2 x double> %a, double %1, i32 0
839  ret <2 x double> %vecins
840}
841
842define <2 x double> @testDoubleImm3(<2 x double> %a, i32* %b) {
843; CHECK-64-LABEL: testDoubleImm3:
844; CHECK-64:       # %bb.0: # %entry
845; CHECK-64-NEXT:    lfd 0, 4(3)
846; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
847; CHECK-64-NEXT:    blr
848;
849; CHECK-32-LABEL: testDoubleImm3:
850; CHECK-32:       # %bb.0: # %entry
851; CHECK-32-NEXT:    lfd 0, 4(3)
852; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
853; CHECK-32-NEXT:    blr
854;
855; CHECK-64-P10-LABEL: testDoubleImm3:
856; CHECK-64-P10:       # %bb.0: # %entry
857; CHECK-64-P10-NEXT:    lfd 0, 4(3)
858; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
859; CHECK-64-P10-NEXT:    blr
860;
861; CHECK-32-P10-LABEL: testDoubleImm3:
862; CHECK-32-P10:       # %bb.0: # %entry
863; CHECK-32-P10-NEXT:    lfd 0, 4(3)
864; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
865; CHECK-32-P10-NEXT:    blr
866entry:
867  %add.ptr = getelementptr inbounds i32, i32* %b, i64 1
868  %0 = bitcast i32* %add.ptr to double*
869  %1 = load double, double* %0, align 8
870  %vecins = insertelement <2 x double> %a, double %1, i32 0
871  ret <2 x double> %vecins
872}
873
874define <2 x double> @testDoubleImm4(<2 x double> %a, i32* %b) {
875; CHECK-64-LABEL: testDoubleImm4:
876; CHECK-64:       # %bb.0: # %entry
877; CHECK-64-NEXT:    lis 4, 4
878; CHECK-64-NEXT:    lfdx 0, 3, 4
879; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
880; CHECK-64-NEXT:    blr
881;
882; CHECK-32-LABEL: testDoubleImm4:
883; CHECK-32:       # %bb.0: # %entry
884; CHECK-32-NEXT:    lis 4, 4
885; CHECK-32-NEXT:    lfdx 0, 3, 4
886; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
887; CHECK-32-NEXT:    blr
888;
889; CHECK-64-P10-LABEL: testDoubleImm4:
890; CHECK-64-P10:       # %bb.0: # %entry
891; CHECK-64-P10-NEXT:    lis 4, 4
892; CHECK-64-P10-NEXT:    lfdx 0, 3, 4
893; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
894; CHECK-64-P10-NEXT:    blr
895;
896; CHECK-32-P10-LABEL: testDoubleImm4:
897; CHECK-32-P10:       # %bb.0: # %entry
898; CHECK-32-P10-NEXT:    lis 4, 4
899; CHECK-32-P10-NEXT:    lfdx 0, 3, 4
900; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
901; CHECK-32-P10-NEXT:    blr
902entry:
903  %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
904  %0 = bitcast i32* %add.ptr to double*
905  %1 = load double, double* %0, align 8
906  %vecins = insertelement <2 x double> %a, double %1, i32 0
907  ret <2 x double> %vecins
908}
909
910define <2 x double> @testDoubleImm5(<2 x double> %a, i32* %b) {
911; CHECK-64-LABEL: testDoubleImm5:
912; CHECK-64:       # %bb.0: # %entry
913; CHECK-64-NEXT:    li 4, 1
914; CHECK-64-NEXT:    rldic 4, 4, 38, 25
915; CHECK-64-NEXT:    lfdx 0, 3, 4
916; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
917; CHECK-64-NEXT:    blr
918;
919; CHECK-32-LABEL: testDoubleImm5:
920; CHECK-32:       # %bb.0: # %entry
921; CHECK-32-NEXT:    lfd 0, 0(3)
922; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
923; CHECK-32-NEXT:    blr
924;
925; CHECK-64-P10-LABEL: testDoubleImm5:
926; CHECK-64-P10:       # %bb.0: # %entry
927; CHECK-64-P10-NEXT:    li 4, 1
928; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
929; CHECK-64-P10-NEXT:    lfdx 0, 3, 4
930; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
931; CHECK-64-P10-NEXT:    blr
932;
933; CHECK-32-P10-LABEL: testDoubleImm5:
934; CHECK-32-P10:       # %bb.0: # %entry
935; CHECK-32-P10-NEXT:    lfd 0, 0(3)
936; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
937; CHECK-32-P10-NEXT:    blr
938entry:
939  %add.ptr = getelementptr inbounds i32, i32* %b, i64 68719476736
940  %0 = bitcast i32* %add.ptr to double*
941  %1 = load double, double* %0, align 8
942  %vecins = insertelement <2 x double> %a, double %1, i32 0
943  ret <2 x double> %vecins
944}
945
946