1; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
2; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
3
4; Even though general vector types are not supported in PTX, we can still
5; optimize loads/stores with pseudo-vector instructions of the form:
6;
7; ld.v2.f32 {%f0, %f1}, [%r0]
8;
9; which will load two floats at once into scalar registers.
10
11; CHECK-LABEL: foo
12define void @foo(<2 x float>* %a) {
13; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
14  %t1 = load <2 x float>, <2 x float>* %a
15  %t2 = fmul <2 x float> %t1, %t1
16  store <2 x float> %t2, <2 x float>* %a
17  ret void
18}
19
20; CHECK-LABEL: foo2
21define void @foo2(<4 x float>* %a) {
22; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
23  %t1 = load <4 x float>, <4 x float>* %a
24  %t2 = fmul <4 x float> %t1, %t1
25  store <4 x float> %t2, <4 x float>* %a
26  ret void
27}
28
29; CHECK-LABEL: foo3
30define void @foo3(<8 x float>* %a) {
31; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
32; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
33  %t1 = load <8 x float>, <8 x float>* %a
34  %t2 = fmul <8 x float> %t1, %t1
35  store <8 x float> %t2, <8 x float>* %a
36  ret void
37}
38
39
40
41; CHECK-LABEL: foo4
42define void @foo4(<2 x i32>* %a) {
43; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}}
44  %t1 = load <2 x i32>, <2 x i32>* %a
45  %t2 = mul <2 x i32> %t1, %t1
46  store <2 x i32> %t2, <2 x i32>* %a
47  ret void
48}
49
50; CHECK-LABEL: foo5
51define void @foo5(<4 x i32>* %a) {
52; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
53  %t1 = load <4 x i32>, <4 x i32>* %a
54  %t2 = mul <4 x i32> %t1, %t1
55  store <4 x i32> %t2, <4 x i32>* %a
56  ret void
57}
58
59; CHECK-LABEL: foo6
60define void @foo6(<8 x i32>* %a) {
61; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
62; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
63  %t1 = load <8 x i32>, <8 x i32>* %a
64  %t2 = mul <8 x i32> %t1, %t1
65  store <8 x i32> %t2, <8 x i32>* %a
66  ret void
67}
68
69; The following test wasn't passing previously as the address
70; computation was still too complex when LSV was called.
71declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
72declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
73; CHECK-LABEL: foo_complex
74define void @foo_complex(i8* nocapture readonly align 16 dereferenceable(134217728) %alloc0) {
75  %targ0.1.typed = bitcast i8* %alloc0 to [1024 x [131072 x i8]]*
76  %t0 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !1
77  %t1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
78  %t2 = lshr i32 %t1, 8
79  %t3 = shl nuw nsw i32 %t1, 9
80  %ttile_origin.2 = and i32 %t3, 130560
81  %tstart_offset_x_mul = shl nuw nsw i32 %t0, 1
82  %t4 = or i32 %ttile_origin.2, %tstart_offset_x_mul
83  %t6 = or i32 %t4, 1
84  %t8 = or i32 %t4, 128
85  %t9 = zext i32 %t8 to i64
86  %t10 = or i32 %t4, 129
87  %t11 = zext i32 %t10 to i64
88  %t20 = zext i32 %t2 to i64
89  %t27 = getelementptr inbounds [1024 x [131072 x i8]], [1024 x [131072 x i8]]* %targ0.1.typed, i64 0, i64 %t20, i64 %t9
90; CHECK: ld.v2.u8
91  %t28 = load i8, i8* %t27, align 2
92  %t31 = getelementptr inbounds [1024 x [131072 x i8]], [1024 x [131072 x i8]]* %targ0.1.typed, i64 0, i64 %t20, i64 %t11
93  %t32 = load i8, i8* %t31, align 1
94  %t33 = icmp ult i8 %t28, %t32
95  %t34 = select i1 %t33, i8 %t32, i8 %t28
96  store i8 %t34, i8* %t31
97; CHECK: ret
98  ret void
99}
100
101
102!1 = !{i32 0, i32 64}
103