1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
3# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
4--- |
5
6  define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
7  entry:
8    br i1 %cnd, label %cond.true, label %cond.false
9
10  cond.true:                                        ; preds = %entry
11    br label %cond.end
12
13  cond.false:                                       ; preds = %entry
14    br label %cond.end
15
16  cond.end:                                         ; preds = %cond.false, %cond.true
17    %cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ]
18    ret i32 %cond
19  }
20
21  define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) {
22  entry:
23    br i1 %cnd, label %cond.true, label %cond.false
24
25  cond.true:                                        ; preds = %entry
26    br label %cond.end
27
28  cond.false:                                       ; preds = %entry
29    br label %cond.end
30
31  cond.end:                                         ; preds = %cond.false, %cond.true
32    %cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
33    ret i64 %cond
34  }
35
36  define float @phi_float(i1 %cnd, float %a, float %b) {
37  entry:
38    br i1 %cnd, label %cond.true, label %cond.false
39
40  cond.true:                                        ; preds = %entry
41    br label %cond.end
42
43  cond.false:                                       ; preds = %entry
44    br label %cond.end
45
46  cond.end:                                         ; preds = %cond.false, %cond.true
47    %cond = phi float [ %a, %cond.true ], [ %b, %cond.false ]
48    ret float %cond
49  }
50
51  define double @phi_double(double %a, double %b, i1 %cnd) {
52  entry:
53    br i1 %cnd, label %cond.true, label %cond.false
54
55  cond.true:                                        ; preds = %entry
56    br label %cond.end
57
58  cond.false:                                       ; preds = %entry
59    br label %cond.end
60
61  cond.end:                                         ; preds = %cond.false, %cond.true
62    %cond = phi double [ %a, %cond.true ], [ %b, %cond.false ]
63    ret double %cond
64  }
65
66...
67---
68name:            phi_i32
69alignment:       4
70legalized:       true
71regBankSelected: true
72tracksRegLiveness: true
73body:             |
74  ; MIPS32FP32-LABEL: name: phi_i32
75  ; MIPS32FP32: bb.0.entry:
76  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
77  ; MIPS32FP32:   liveins: $a0, $a1, $a2
78  ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
79  ; MIPS32FP32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
80  ; MIPS32FP32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
81  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
82  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
83  ; MIPS32FP32:   J %bb.2, implicit-def $at
84  ; MIPS32FP32: bb.1.cond.true:
85  ; MIPS32FP32:   successors: %bb.3(0x80000000)
86  ; MIPS32FP32:   J %bb.3, implicit-def $at
87  ; MIPS32FP32: bb.2.cond.false:
88  ; MIPS32FP32:   successors: %bb.3(0x80000000)
89  ; MIPS32FP32: bb.3.cond.end:
90  ; MIPS32FP32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
91  ; MIPS32FP32:   $v0 = COPY [[PHI]]
92  ; MIPS32FP32:   RetRA implicit $v0
93  ; MIPS32FP64-LABEL: name: phi_i32
94  ; MIPS32FP64: bb.0.entry:
95  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
96  ; MIPS32FP64:   liveins: $a0, $a1, $a2
97  ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
98  ; MIPS32FP64:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
99  ; MIPS32FP64:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
100  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
101  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
102  ; MIPS32FP64:   J %bb.2, implicit-def $at
103  ; MIPS32FP64: bb.1.cond.true:
104  ; MIPS32FP64:   successors: %bb.3(0x80000000)
105  ; MIPS32FP64:   J %bb.3, implicit-def $at
106  ; MIPS32FP64: bb.2.cond.false:
107  ; MIPS32FP64:   successors: %bb.3(0x80000000)
108  ; MIPS32FP64: bb.3.cond.end:
109  ; MIPS32FP64:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
110  ; MIPS32FP64:   $v0 = COPY [[PHI]]
111  ; MIPS32FP64:   RetRA implicit $v0
112  bb.1.entry:
113    liveins: $a0, $a1, $a2
114
115    %3:gprb(s32) = COPY $a0
116    %1:gprb(s32) = COPY $a1
117    %2:gprb(s32) = COPY $a2
118    %6:gprb(s32) = G_CONSTANT i32 1
119    %7:gprb(s32) = COPY %3(s32)
120    %5:gprb(s32) = G_AND %7, %6
121    G_BRCOND %5(s32), %bb.2
122    G_BR %bb.3
123
124  bb.2.cond.true:
125    G_BR %bb.4
126
127  bb.3.cond.false:
128
129  bb.4.cond.end:
130    %4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
131    $v0 = COPY %4(s32)
132    RetRA implicit $v0
133
134...
135---
136name:            phi_i64
137alignment:       4
138legalized:       true
139regBankSelected: true
140tracksRegLiveness: true
141fixedStack:
142  - { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true }
143  - { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
144body:             |
145  ; MIPS32FP32-LABEL: name: phi_i64
146  ; MIPS32FP32: bb.0.entry:
147  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
148  ; MIPS32FP32:   liveins: $a0, $a2, $a3
149  ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
150  ; MIPS32FP32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
151  ; MIPS32FP32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
152  ; MIPS32FP32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
153  ; MIPS32FP32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
154  ; MIPS32FP32:   [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
155  ; MIPS32FP32:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1)
156  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
157  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
158  ; MIPS32FP32:   J %bb.2, implicit-def $at
159  ; MIPS32FP32: bb.1.cond.true:
160  ; MIPS32FP32:   successors: %bb.3(0x80000000)
161  ; MIPS32FP32:   J %bb.3, implicit-def $at
162  ; MIPS32FP32: bb.2.cond.false:
163  ; MIPS32FP32:   successors: %bb.3(0x80000000)
164  ; MIPS32FP32: bb.3.cond.end:
165  ; MIPS32FP32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
166  ; MIPS32FP32:   [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
167  ; MIPS32FP32:   $v0 = COPY [[PHI]]
168  ; MIPS32FP32:   $v1 = COPY [[PHI1]]
169  ; MIPS32FP32:   RetRA implicit $v0, implicit $v1
170  ; MIPS32FP64-LABEL: name: phi_i64
171  ; MIPS32FP64: bb.0.entry:
172  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
173  ; MIPS32FP64:   liveins: $a0, $a2, $a3
174  ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
175  ; MIPS32FP64:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
176  ; MIPS32FP64:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
177  ; MIPS32FP64:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
178  ; MIPS32FP64:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
179  ; MIPS32FP64:   [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
180  ; MIPS32FP64:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1)
181  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
182  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
183  ; MIPS32FP64:   J %bb.2, implicit-def $at
184  ; MIPS32FP64: bb.1.cond.true:
185  ; MIPS32FP64:   successors: %bb.3(0x80000000)
186  ; MIPS32FP64:   J %bb.3, implicit-def $at
187  ; MIPS32FP64: bb.2.cond.false:
188  ; MIPS32FP64:   successors: %bb.3(0x80000000)
189  ; MIPS32FP64: bb.3.cond.end:
190  ; MIPS32FP64:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
191  ; MIPS32FP64:   [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
192  ; MIPS32FP64:   $v0 = COPY [[PHI]]
193  ; MIPS32FP64:   $v1 = COPY [[PHI1]]
194  ; MIPS32FP64:   RetRA implicit $v0, implicit $v1
195  bb.1.entry:
196    liveins: $a0, $a2, $a3
197
198    %3:gprb(s32) = COPY $a0
199    %4:gprb(s32) = COPY $a2
200    %5:gprb(s32) = COPY $a3
201    %8:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
202    %6:gprb(s32) = G_LOAD %8(p0) :: (load (s32) from %fixed-stack.1, align 8)
203    %9:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
204    %7:gprb(s32) = G_LOAD %9(p0) :: (load (s32) from %fixed-stack.0)
205    %14:gprb(s32) = G_CONSTANT i32 1
206    %15:gprb(s32) = COPY %3(s32)
207    %13:gprb(s32) = G_AND %15, %14
208    G_BRCOND %13(s32), %bb.2
209    G_BR %bb.3
210
211  bb.2.cond.true:
212    G_BR %bb.4
213
214  bb.3.cond.false:
215
216  bb.4.cond.end:
217    %20:gprb(s32) = G_PHI %4(s32), %bb.2, %6(s32), %bb.3
218    %21:gprb(s32) = G_PHI %5(s32), %bb.2, %7(s32), %bb.3
219    $v0 = COPY %20(s32)
220    $v1 = COPY %21(s32)
221    RetRA implicit $v0, implicit $v1
222
223...
224---
225name:            phi_float
226alignment:       4
227legalized:       true
228regBankSelected: true
229tracksRegLiveness: true
230body:             |
231  ; MIPS32FP32-LABEL: name: phi_float
232  ; MIPS32FP32: bb.0.entry:
233  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
234  ; MIPS32FP32:   liveins: $a0, $a1, $a2
235  ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
236  ; MIPS32FP32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
237  ; MIPS32FP32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
238  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
239  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
240  ; MIPS32FP32:   J %bb.2, implicit-def $at
241  ; MIPS32FP32: bb.1.cond.true:
242  ; MIPS32FP32:   successors: %bb.3(0x80000000)
243  ; MIPS32FP32:   J %bb.3, implicit-def $at
244  ; MIPS32FP32: bb.2.cond.false:
245  ; MIPS32FP32:   successors: %bb.3(0x80000000)
246  ; MIPS32FP32: bb.3.cond.end:
247  ; MIPS32FP32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
248  ; MIPS32FP32:   $f0 = COPY [[PHI]]
249  ; MIPS32FP32:   RetRA implicit $f0
250  ; MIPS32FP64-LABEL: name: phi_float
251  ; MIPS32FP64: bb.0.entry:
252  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
253  ; MIPS32FP64:   liveins: $a0, $a1, $a2
254  ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
255  ; MIPS32FP64:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
256  ; MIPS32FP64:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
257  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
258  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
259  ; MIPS32FP64:   J %bb.2, implicit-def $at
260  ; MIPS32FP64: bb.1.cond.true:
261  ; MIPS32FP64:   successors: %bb.3(0x80000000)
262  ; MIPS32FP64:   J %bb.3, implicit-def $at
263  ; MIPS32FP64: bb.2.cond.false:
264  ; MIPS32FP64:   successors: %bb.3(0x80000000)
265  ; MIPS32FP64: bb.3.cond.end:
266  ; MIPS32FP64:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
267  ; MIPS32FP64:   $f0 = COPY [[PHI]]
268  ; MIPS32FP64:   RetRA implicit $f0
269  bb.1.entry:
270    liveins: $a0, $a1, $a2
271
272    %3:gprb(s32) = COPY $a0
273    %1:gprb(s32) = COPY $a1
274    %2:gprb(s32) = COPY $a2
275    %6:gprb(s32) = G_CONSTANT i32 1
276    %7:gprb(s32) = COPY %3(s32)
277    %5:gprb(s32) = G_AND %7, %6
278    G_BRCOND %5(s32), %bb.2
279    G_BR %bb.3
280
281  bb.2.cond.true:
282    G_BR %bb.4
283
284  bb.3.cond.false:
285
286  bb.4.cond.end:
287    %4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
288    $f0 = COPY %4(s32)
289    RetRA implicit $f0
290
291...
292---
293name:            phi_double
294alignment:       4
295legalized:       true
296regBankSelected: true
297tracksRegLiveness: true
298fixedStack:
299  - { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
300body:             |
301  ; MIPS32FP32-LABEL: name: phi_double
302  ; MIPS32FP32: bb.0.entry:
303  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
304  ; MIPS32FP32:   liveins: $d6, $d7
305  ; MIPS32FP32:   [[COPY:%[0-9]+]]:afgr64 = COPY $d6
306  ; MIPS32FP32:   [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
307  ; MIPS32FP32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
308  ; MIPS32FP32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
309  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
310  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
311  ; MIPS32FP32:   J %bb.2, implicit-def $at
312  ; MIPS32FP32: bb.1.cond.true:
313  ; MIPS32FP32:   successors: %bb.3(0x80000000)
314  ; MIPS32FP32:   J %bb.3, implicit-def $at
315  ; MIPS32FP32: bb.2.cond.false:
316  ; MIPS32FP32:   successors: %bb.3(0x80000000)
317  ; MIPS32FP32: bb.3.cond.end:
318  ; MIPS32FP32:   [[PHI:%[0-9]+]]:afgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
319  ; MIPS32FP32:   $d0 = COPY [[PHI]]
320  ; MIPS32FP32:   RetRA implicit $d0
321  ; MIPS32FP64-LABEL: name: phi_double
322  ; MIPS32FP64: bb.0.entry:
323  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
324  ; MIPS32FP64:   liveins: $d6, $d7
325  ; MIPS32FP64:   [[COPY:%[0-9]+]]:fgr64 = COPY $d6
326  ; MIPS32FP64:   [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
327  ; MIPS32FP64:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
328  ; MIPS32FP64:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
329  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
330  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
331  ; MIPS32FP64:   J %bb.2, implicit-def $at
332  ; MIPS32FP64: bb.1.cond.true:
333  ; MIPS32FP64:   successors: %bb.3(0x80000000)
334  ; MIPS32FP64:   J %bb.3, implicit-def $at
335  ; MIPS32FP64: bb.2.cond.false:
336  ; MIPS32FP64:   successors: %bb.3(0x80000000)
337  ; MIPS32FP64: bb.3.cond.end:
338  ; MIPS32FP64:   [[PHI:%[0-9]+]]:fgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
339  ; MIPS32FP64:   $d0 = COPY [[PHI]]
340  ; MIPS32FP64:   RetRA implicit $d0
341  bb.1.entry:
342    liveins: $d6, $d7
343
344    %0:fprb(s64) = COPY $d6
345    %1:fprb(s64) = COPY $d7
346    %4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
347    %3:gprb(s32) = G_LOAD %4(p0) :: (load (s32) from %fixed-stack.0, align 8)
348    %7:gprb(s32) = G_CONSTANT i32 1
349    %8:gprb(s32) = COPY %3(s32)
350    %6:gprb(s32) = G_AND %8, %7
351    G_BRCOND %6(s32), %bb.2
352    G_BR %bb.3
353
354  bb.2.cond.true:
355    G_BR %bb.4
356
357  bb.3.cond.false:
358
359  bb.4.cond.end:
360    %5:fprb(s64) = G_PHI %0(s64), %bb.2, %1(s64), %bb.3
361    $d0 = COPY %5(s64)
362    RetRA implicit $d0
363
364...
365