1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s 2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s 3 4; Test that SIMachineFunctionInfo can be round trip serialized through 5; MIR. 6 7@lds = addrspace(3) global [512 x float] undef, align 4 8 9; CHECK-LABEL: {{^}}name: kernel 10; CHECK: machineFunctionInfo: 11; CHECK-NEXT: explicitKernArgSize: 128 12; CHECK-NEXT: maxKernArgAlign: 64 13; CHECK-NEXT: ldsSize: 0 14; CHECK-NEXT: isEntryFunction: true 15; CHECK-NEXT: noSignedZerosFPMath: false 16; CHECK-NEXT: memoryBound: false 17; CHECK-NEXT: waveLimiter: false 18; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 19; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' 20; CHECK-NEXT: frameOffsetReg: '$sgpr101' 21; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' 22; CHECK-NEXT: argumentInfo: 23; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 24; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } 25; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } 26; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } 27; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } 28; CHECK-NEXT: mode: 29; CHECK-NEXT: ieee: true 30; CHECK-NEXT: dx10-clamp: true 31; CHECK-NEXT: fp32-input-denormals: false 32; CHECK-NEXT: fp32-output-denormals: false 33; CHECK-NEXT: fp64-fp16-input-denormals: true 34; CHECK-NEXT: fp64-fp16-output-denormals: true 35; CHECK-NEXT: highBitsOf32BitAddress: 0 36; CHECK-NEXT: body: 37define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { 38 %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0 39 store float 0.0, float addrspace(3)* %gep, align 4 40 ret void 41} 42 43; CHECK-LABEL: {{^}}name: ps_shader 44; CHECK: machineFunctionInfo: 45; CHECK-NEXT: explicitKernArgSize: 0 46; CHECK-NEXT: maxKernArgAlign: 1 47; CHECK-NEXT: ldsSize: 0 48; CHECK-NEXT: isEntryFunction: true 49; CHECK-NEXT: noSignedZerosFPMath: false 50; CHECK-NEXT: memoryBound: false 51; CHECK-NEXT: waveLimiter: false 52; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 53; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' 54; CHECK-NEXT: frameOffsetReg: '$sgpr101' 55; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' 56; CHECK-NEXT: argumentInfo: 57; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' } 58; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } 59; CHECK-NEXT: mode: 60; CHECK-NEXT: ieee: false 61; CHECK-NEXT: dx10-clamp: true 62; CHECK-NEXT: fp32-input-denormals: false 63; CHECK-NEXT: fp32-output-denormals: false 64; CHECK-NEXT: fp64-fp16-input-denormals: true 65; CHECK-NEXT: fp64-fp16-output-denormals: true 66; CHECK-NEXT: highBitsOf32BitAddress: 0 67; CHECK-NEXT: body: 68define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { 69 ret void 70} 71 72; CHECK-LABEL: {{^}}name: function 73; CHECK: machineFunctionInfo: 74; CHECK-NEXT: explicitKernArgSize: 0 75; CHECK-NEXT: maxKernArgAlign: 1 76; CHECK-NEXT: ldsSize: 0 77; CHECK-NEXT: isEntryFunction: false 78; CHECK-NEXT: noSignedZerosFPMath: false 79; CHECK-NEXT: memoryBound: false 80; CHECK-NEXT: waveLimiter: false 81; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 82; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' 83; CHECK-NEXT: frameOffsetReg: '$sgpr34' 84; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 85; CHECK-NEXT: argumentInfo: 86; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 87; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' } 88; CHECK-NEXT: mode: 89; CHECK-NEXT: ieee: true 90; CHECK-NEXT: dx10-clamp: true 91; CHECK-NEXT: fp32-input-denormals: false 92; CHECK-NEXT: fp32-output-denormals: false 93; CHECK-NEXT: fp64-fp16-input-denormals: true 94; CHECK-NEXT: fp64-fp16-output-denormals: true 95; CHECK-NEXT: highBitsOf32BitAddress: 0 96; CHECK-NEXT: body: 97define void @function() { 98 ret void 99} 100 101; CHECK-LABEL: {{^}}name: function_nsz 102; CHECK: machineFunctionInfo: 103; CHECK-NEXT: explicitKernArgSize: 0 104; CHECK-NEXT: maxKernArgAlign: 1 105; CHECK-NEXT: ldsSize: 0 106; CHECK-NEXT: isEntryFunction: false 107; CHECK-NEXT: noSignedZerosFPMath: true 108; CHECK-NEXT: memoryBound: false 109; CHECK-NEXT: waveLimiter: false 110; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 111; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' 112; CHECK-NEXT: frameOffsetReg: '$sgpr34' 113; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 114; CHECK-NEXT: argumentInfo: 115; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 116; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' } 117; CHECK-NEXT: mode: 118; CHECK-NEXT: ieee: true 119; CHECK-NEXT: dx10-clamp: true 120; CHECK-NEXT: fp32-input-denormals: false 121; CHECK-NEXT: fp32-output-denormals: false 122; CHECK-NEXT: fp64-fp16-input-denormals: true 123; CHECK-NEXT: fp64-fp16-output-denormals: true 124; CHECK-NEXT: highBitsOf32BitAddress: 0 125; CHECK-NEXT: body: 126define void @function_nsz() #0 { 127 ret void 128} 129 130; CHECK-LABEL: {{^}}name: function_dx10_clamp_off 131; CHECK: mode: 132; CHECK-NEXT: ieee: true 133; CHECK-NEXT: dx10-clamp: false 134; CHECK-NEXT: fp32-input-denormals: false 135; CHECK-NEXT: fp32-output-denormals: false 136; CHECK-NEXT: fp64-fp16-input-denormals: true 137; CHECK-NEXT: fp64-fp16-output-denormals: true 138define void @function_dx10_clamp_off() #1 { 139 ret void 140} 141 142; CHECK-LABEL: {{^}}name: function_ieee_off 143; CHECK: mode: 144; CHECK-NEXT: ieee: false 145; CHECK-NEXT: dx10-clamp: true 146; CHECK-NEXT: fp32-input-denormals: false 147; CHECK-NEXT: fp32-output-denormals: false 148; CHECK-NEXT: fp64-fp16-input-denormals: true 149; CHECK-NEXT: fp64-fp16-output-denormals: true 150define void @function_ieee_off() #2 { 151 ret void 152} 153 154; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off 155; CHECK: mode: 156; CHECK-NEXT: ieee: false 157; CHECK-NEXT: dx10-clamp: false 158; CHECK-NEXT: fp32-input-denormals: false 159; CHECK-NEXT: fp32-output-denormals: false 160; CHECK-NEXT: fp64-fp16-input-denormals: true 161; CHECK-NEXT: fp64-fp16-output-denormals: true 162define void @function_ieee_off_dx10_clamp_off() #3 { 163 ret void 164} 165 166; CHECK-LABEL: {{^}}name: high_address_bits 167; CHECK: machineFunctionInfo: 168; CHECK: highBitsOf32BitAddress: 4294934528 169define amdgpu_ps void @high_address_bits() #4 { 170 ret void 171} 172 173attributes #0 = { "no-signed-zeros-fp-math" = "true" } 174attributes #1 = { "amdgpu-dx10-clamp" = "false" } 175attributes #2 = { "amdgpu-ieee" = "false" } 176attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" } 177attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" } 178