1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=si-pre-allocate-wwm-regs -o %t.mir %s 2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s 3 4; Test that SIMachineFunctionInfo can be round trip serialized through 5; MIR. 6 7@lds = addrspace(3) global [512 x float] undef, align 4 8 9; CHECK-LABEL: {{^}}name: kernel 10; CHECK: machineFunctionInfo: 11; CHECK-NEXT: explicitKernArgSize: 128 12; CHECK-NEXT: maxKernArgAlign: 64 13; CHECK-NEXT: ldsSize: 2048 14; CHECK-NEXT: gdsSize: 0 15; CHECK-NEXT: dynLDSAlign: 1 16; CHECK-NEXT: isEntryFunction: true 17; CHECK-NEXT: noSignedZerosFPMath: false 18; CHECK-NEXT: memoryBound: false 19; CHECK-NEXT: waveLimiter: false 20; CHECK-NEXT: hasSpilledSGPRs: false 21; CHECK-NEXT: hasSpilledVGPRs: false 22; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 23; CHECK-NEXT: frameOffsetReg: '$fp_reg' 24; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 25; CHECK-NEXT: bytesInStackArgArea: 0 26; CHECK-NEXT: returnsVoid: true 27; CHECK-NEXT: argumentInfo: 28; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 29; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } 30; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } 31; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } 32; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } 33; CHECK-NEXT: mode: 34; CHECK-NEXT: ieee: true 35; CHECK-NEXT: dx10-clamp: true 36; CHECK-NEXT: fp32-input-denormals: true 37; CHECK-NEXT: fp32-output-denormals: true 38; CHECK-NEXT: fp64-fp16-input-denormals: true 39; CHECK-NEXT: fp64-fp16-output-denormals: true 40; CHECK-NEXT: highBitsOf32BitAddress: 0 41; CHECK-NEXT: occupancy: 10 42; CHECK-NEXT: vgprForAGPRCopy: '' 43; CHECK-NEXT: body: 44define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { 45 %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0 46 store float 0.0, float addrspace(3)* %gep, align 4 47 ret void 48} 49 50@gds = addrspace(2) global [128 x i32] undef, align 4 51 52; CHECK-LABEL: {{^}}name: ps_shader 53; CHECK: machineFunctionInfo: 54; CHECK-NEXT: explicitKernArgSize: 0 55; CHECK-NEXT: maxKernArgAlign: 4 56; CHECK-NEXT: ldsSize: 0 57; CHECK-NEXT: gdsSize: 512 58; CHECK-NEXT: dynLDSAlign: 1 59; CHECK-NEXT: isEntryFunction: true 60; CHECK-NEXT: noSignedZerosFPMath: false 61; CHECK-NEXT: memoryBound: false 62; CHECK-NEXT: waveLimiter: false 63; CHECK-NEXT: hasSpilledSGPRs: false 64; CHECK-NEXT: hasSpilledVGPRs: false 65; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 66; CHECK-NEXT: frameOffsetReg: '$fp_reg' 67; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 68; CHECK-NEXT: bytesInStackArgArea: 0 69; CHECK-NEXT: returnsVoid: true 70; CHECK-NEXT: argumentInfo: 71; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' } 72; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } 73; CHECK-NEXT: mode: 74; CHECK-NEXT: ieee: false 75; CHECK-NEXT: dx10-clamp: true 76; CHECK-NEXT: fp32-input-denormals: true 77; CHECK-NEXT: fp32-output-denormals: true 78; CHECK-NEXT: fp64-fp16-input-denormals: true 79; CHECK-NEXT: fp64-fp16-output-denormals: true 80; CHECK-NEXT: highBitsOf32BitAddress: 0 81; CHECK-NEXT: occupancy: 10 82; CHECK-NEXT: vgprForAGPRCopy: '' 83; CHECK-NEXT: body: 84define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { 85 %gep = getelementptr inbounds [128 x i32], [128 x i32] addrspace(2)* @gds, i32 0, i32 %arg0 86 atomicrmw add i32 addrspace(2)* %gep, i32 8 seq_cst 87 ret void 88} 89 90; CHECK-LABEL: {{^}}name: gds_size_shader 91; CHECK: gdsSize: 4096 92define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 { 93 ret void 94} 95 96; CHECK-LABEL: {{^}}name: function 97; CHECK: machineFunctionInfo: 98; CHECK-NEXT: explicitKernArgSize: 0 99; CHECK-NEXT: maxKernArgAlign: 1 100; CHECK-NEXT: ldsSize: 0 101; CHECK-NEXT: gdsSize: 0 102; CHECK-NEXT: dynLDSAlign: 1 103; CHECK-NEXT: isEntryFunction: false 104; CHECK-NEXT: noSignedZerosFPMath: false 105; CHECK-NEXT: memoryBound: false 106; CHECK-NEXT: waveLimiter: false 107; CHECK-NEXT: hasSpilledSGPRs: false 108; CHECK-NEXT: hasSpilledVGPRs: false 109; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 110; CHECK-NEXT: frameOffsetReg: '$sgpr33' 111; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 112; CHECK-NEXT: bytesInStackArgArea: 0 113; CHECK-NEXT: returnsVoid: true 114; CHECK-NEXT: argumentInfo: 115; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 116; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } 117; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' } 118; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' } 119; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' } 120; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' } 121; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' } 122; CHECK-NEXT: LDSKernelId: { reg: '$sgpr15' } 123; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' } 124; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } 125; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } 126; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 127; CHECK-NEXT: mode: 128; CHECK-NEXT: ieee: true 129; CHECK-NEXT: dx10-clamp: true 130; CHECK-NEXT: fp32-input-denormals: true 131; CHECK-NEXT: fp32-output-denormals: true 132; CHECK-NEXT: fp64-fp16-input-denormals: true 133; CHECK-NEXT: fp64-fp16-output-denormals: true 134; CHECK-NEXT: highBitsOf32BitAddress: 0 135; CHECK-NEXT: occupancy: 10 136; CHECK-NEXT: vgprForAGPRCopy: '' 137; CHECK-NEXT: body: 138define void @function() { 139 ret void 140} 141 142; CHECK-LABEL: {{^}}name: function_nsz 143; CHECK: machineFunctionInfo: 144; CHECK-NEXT: explicitKernArgSize: 0 145; CHECK-NEXT: maxKernArgAlign: 1 146; CHECK-NEXT: ldsSize: 0 147; CHECK-NEXT: gdsSize: 0 148; CHECK-NEXT: dynLDSAlign: 1 149; CHECK-NEXT: isEntryFunction: false 150; CHECK-NEXT: noSignedZerosFPMath: true 151; CHECK-NEXT: memoryBound: false 152; CHECK-NEXT: waveLimiter: false 153; CHECK-NEXT: hasSpilledSGPRs: false 154; CHECK-NEXT: hasSpilledVGPRs: false 155; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 156; CHECK-NEXT: frameOffsetReg: '$sgpr33' 157; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 158; CHECK-NEXT: bytesInStackArgArea: 0 159; CHECK-NEXT: returnsVoid: true 160; CHECK-NEXT: argumentInfo: 161; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 162; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } 163; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' } 164; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' } 165; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' } 166; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' } 167; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' } 168; CHECK-NEXT: LDSKernelId: { reg: '$sgpr15' } 169; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' } 170; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } 171; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } 172; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 173; CHECK-NEXT: mode: 174; CHECK-NEXT: ieee: true 175; CHECK-NEXT: dx10-clamp: true 176; CHECK-NEXT: fp32-input-denormals: true 177; CHECK-NEXT: fp32-output-denormals: true 178; CHECK-NEXT: fp64-fp16-input-denormals: true 179; CHECK-NEXT: fp64-fp16-output-denormals: true 180; CHECK-NEXT: highBitsOf32BitAddress: 0 181; CHECK-NEXT: occupancy: 10 182; CHECK-NEXT: vgprForAGPRCopy: '' 183; CHECK-NEXT: body: 184define void @function_nsz() #0 { 185 ret void 186} 187 188; CHECK-LABEL: {{^}}name: function_dx10_clamp_off 189; CHECK: mode: 190; CHECK-NEXT: ieee: true 191; CHECK-NEXT: dx10-clamp: false 192; CHECK-NEXT: fp32-input-denormals: true 193; CHECK-NEXT: fp32-output-denormals: true 194; CHECK-NEXT: fp64-fp16-input-denormals: true 195; CHECK-NEXT: fp64-fp16-output-denormals: true 196define void @function_dx10_clamp_off() #1 { 197 ret void 198} 199 200; CHECK-LABEL: {{^}}name: function_ieee_off 201; CHECK: mode: 202; CHECK-NEXT: ieee: false 203; CHECK-NEXT: dx10-clamp: true 204; CHECK-NEXT: fp32-input-denormals: true 205; CHECK-NEXT: fp32-output-denormals: true 206; CHECK-NEXT: fp64-fp16-input-denormals: true 207; CHECK-NEXT: fp64-fp16-output-denormals: true 208define void @function_ieee_off() #2 { 209 ret void 210} 211 212; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off 213; CHECK: mode: 214; CHECK-NEXT: ieee: false 215; CHECK-NEXT: dx10-clamp: false 216; CHECK-NEXT: fp32-input-denormals: true 217; CHECK-NEXT: fp32-output-denormals: true 218; CHECK-NEXT: fp64-fp16-input-denormals: true 219; CHECK-NEXT: fp64-fp16-output-denormals: true 220define void @function_ieee_off_dx10_clamp_off() #3 { 221 ret void 222} 223 224; CHECK-LABEL: {{^}}name: high_address_bits 225; CHECK: machineFunctionInfo: 226; CHECK: highBitsOf32BitAddress: 4294934528 227define amdgpu_ps void @high_address_bits() #4 { 228 ret void 229} 230 231; CHECK-LABEL: {{^}}name: wwm_reserved_regs 232; CHECK: wwmReservedRegs: 233; CHECK-NEXT: - '$vgpr2' 234; CHECK-NEXT: - '$vgpr3' 235define amdgpu_cs void @wwm_reserved_regs(i32 addrspace(1)* %ptr, <4 x i32> inreg %tmp14) { 236 %ld0 = load volatile i32, i32 addrspace(1)* %ptr 237 %ld1 = load volatile i32, i32 addrspace(1)* %ptr 238 %inactive0 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld1, i32 0) 239 %inactive1 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld0, i32 0) 240 store volatile i32 %inactive0, i32 addrspace(1)* %ptr 241 store volatile i32 %inactive1, i32 addrspace(1)* %ptr 242 ret void 243} 244 245declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #6 246 247attributes #0 = { "no-signed-zeros-fp-math" = "true" } 248attributes #1 = { "amdgpu-dx10-clamp" = "false" } 249attributes #2 = { "amdgpu-ieee" = "false" } 250attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" } 251attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" } 252attributes #5 = { "amdgpu-gds-size"="4096" } 253attributes #6 = { convergent nounwind readnone willreturn } 254