1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
3
4; Test that SIMachineFunctionInfo can be round trip serialized through
5; MIR.
6
7@lds = addrspace(3) global [512 x float] undef, align 4
8
9; CHECK-LABEL: {{^}}name: kernel
10; CHECK: machineFunctionInfo:
11; CHECK-NEXT: explicitKernArgSize: 128
12; CHECK-NEXT: maxKernArgAlign: 64
13; CHECK-NEXT: ldsSize: 0
14; CHECK-NEXT: isEntryFunction: true
15; CHECK-NEXT: noSignedZerosFPMath: false
16; CHECK-NEXT: memoryBound: false
17; CHECK-NEXT: waveLimiter: false
18; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
19; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
20; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
21; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
22; CHECK-NEXT: argumentInfo:
23; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
24; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
25; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
26; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
27; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
28; CHECK-NEXT: mode:
29; CHECK-NEXT: ieee: true
30; CHECK-NEXT: dx10-clamp: true
31; CHECK-NEXT: fp32-denormals: false
32; CHECK-NEXT: fp64-fp16-denormals: true
33; CHECK-NEXT: highBitsOf32BitAddress: 0
34; CHECK-NEXT: body:
35define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
36  %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
37  store float 0.0, float addrspace(3)* %gep, align 4
38  ret void
39}
40
41; CHECK-LABEL: {{^}}name: ps_shader
42; CHECK: machineFunctionInfo:
43; CHECK-NEXT: explicitKernArgSize: 0
44; CHECK-NEXT: maxKernArgAlign: 1
45; CHECK-NEXT: ldsSize: 0
46; CHECK-NEXT: isEntryFunction: true
47; CHECK-NEXT: noSignedZerosFPMath: false
48; CHECK-NEXT: memoryBound: false
49; CHECK-NEXT: waveLimiter: false
50; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
51; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
52; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
53; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
54; CHECK-NEXT: argumentInfo:
55; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
56; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
57; CHECK-NEXT: mode:
58; CHECK-NEXT: ieee: false
59; CHECK-NEXT: dx10-clamp: true
60; CHECK-NEXT: fp32-denormals: false
61; CHECK-NEXT: fp64-fp16-denormals: true
62; CHECK-NEXT: highBitsOf32BitAddress: 0
63; CHECK-NEXT: body:
64define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
65  ret void
66}
67
68; CHECK-LABEL: {{^}}name: function
69; CHECK: machineFunctionInfo:
70; CHECK-NEXT: explicitKernArgSize: 0
71; CHECK-NEXT: maxKernArgAlign: 1
72; CHECK-NEXT: ldsSize: 0
73; CHECK-NEXT: isEntryFunction: false
74; CHECK-NEXT: noSignedZerosFPMath: false
75; CHECK-NEXT: memoryBound: false
76; CHECK-NEXT: waveLimiter: false
77; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
78; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
79; CHECK-NEXT: frameOffsetReg: '$sgpr34'
80; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
81; CHECK-NEXT: argumentInfo:
82; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
83; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
84; CHECK-NEXT: mode:
85; CHECK-NEXT: ieee: true
86; CHECK-NEXT: dx10-clamp: true
87; CHECK-NEXT: fp32-denormals: false
88; CHECK-NEXT: fp64-fp16-denormals: true
89; CHECK-NEXT: highBitsOf32BitAddress: 0
90; CHECK-NEXT: body:
91define void @function() {
92  ret void
93}
94
95; CHECK-LABEL: {{^}}name: function_nsz
96; CHECK: machineFunctionInfo:
97; CHECK-NEXT: explicitKernArgSize: 0
98; CHECK-NEXT: maxKernArgAlign: 1
99; CHECK-NEXT: ldsSize: 0
100; CHECK-NEXT: isEntryFunction: false
101; CHECK-NEXT: noSignedZerosFPMath: true
102; CHECK-NEXT: memoryBound: false
103; CHECK-NEXT: waveLimiter: false
104; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
105; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
106; CHECK-NEXT: frameOffsetReg: '$sgpr34'
107; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
108; CHECK-NEXT: argumentInfo:
109; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
110; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
111; CHECK-NEXT: mode:
112; CHECK-NEXT: ieee: true
113; CHECK-NEXT: dx10-clamp: true
114; CHECK-NEXT: fp32-denormals: false
115; CHECK-NEXT: fp64-fp16-denormals: true
116; CHECK-NEXT: highBitsOf32BitAddress: 0
117; CHECK-NEXT: body:
118define void @function_nsz() #0 {
119  ret void
120}
121
122; CHECK-LABEL: {{^}}name: function_dx10_clamp_off
123; CHECK: mode:
124; CHECK-NEXT: ieee: true
125; CHECK-NEXT: dx10-clamp: false
126; CHECK-NEXT: fp32-denormals: false
127; CHECK-NEXT: fp64-fp16-denormals: true
128define void @function_dx10_clamp_off() #1 {
129  ret void
130}
131
132; CHECK-LABEL: {{^}}name: function_ieee_off
133; CHECK: mode:
134; CHECK-NEXT: ieee: false
135; CHECK-NEXT: dx10-clamp: true
136; CHECK-NEXT: fp32-denormals: false
137; CHECK-NEXT: fp64-fp16-denormals: true
138define void @function_ieee_off() #2 {
139  ret void
140}
141
142; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off
143; CHECK: mode:
144; CHECK-NEXT: ieee: false
145; CHECK-NEXT: dx10-clamp: false
146; CHECK-NEXT: fp32-denormals: false
147; CHECK-NEXT: fp64-fp16-denormals: true
148define void @function_ieee_off_dx10_clamp_off() #3 {
149  ret void
150}
151
152; CHECK-LABEL: {{^}}name: high_address_bits
153; CHECK: machineFunctionInfo:
154; CHECK: highBitsOf32BitAddress: 4294934528
155define amdgpu_ps void @high_address_bits() #4 {
156  ret void
157}
158
159attributes #0 = { "no-signed-zeros-fp-math" = "true" }
160attributes #1 = { "amdgpu-dx10-clamp" = "false" }
161attributes #2 = { "amdgpu-ieee" = "false" }
162attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
163attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
164