1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s 2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s 3 4; Test that SIMachineFunctionInfo can be round trip serialized through 5; MIR. 6 7@lds = addrspace(3) global [512 x float] undef, align 4 8 9; CHECK-LABEL: {{^}}name: kernel 10; CHECK: machineFunctionInfo: 11; CHECK-NEXT: explicitKernArgSize: 128 12; CHECK-NEXT: maxKernArgAlign: 64 13; CHECK-NEXT: ldsSize: 2048 14; CHECK-NEXT: dynLDSAlign: 1 15; CHECK-NEXT: isEntryFunction: true 16; CHECK-NEXT: noSignedZerosFPMath: false 17; CHECK-NEXT: memoryBound: false 18; CHECK-NEXT: waveLimiter: false 19; CHECK-NEXT: hasSpilledSGPRs: false 20; CHECK-NEXT: hasSpilledVGPRs: false 21; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 22; CHECK-NEXT: frameOffsetReg: '$fp_reg' 23; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 24; CHECK-NEXT: argumentInfo: 25; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 26; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } 27; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } 28; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } 29; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } 30; CHECK-NEXT: mode: 31; CHECK-NEXT: ieee: true 32; CHECK-NEXT: dx10-clamp: true 33; CHECK-NEXT: fp32-input-denormals: true 34; CHECK-NEXT: fp32-output-denormals: true 35; CHECK-NEXT: fp64-fp16-input-denormals: true 36; CHECK-NEXT: fp64-fp16-output-denormals: true 37; CHECK-NEXT: highBitsOf32BitAddress: 0 38; CHECK-NEXT: occupancy: 10 39; CHECK-NEXT: body: 40define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { 41 %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0 42 store float 0.0, float addrspace(3)* %gep, align 4 43 ret void 44} 45 46; CHECK-LABEL: {{^}}name: ps_shader 47; CHECK: machineFunctionInfo: 48; CHECK-NEXT: explicitKernArgSize: 0 49; CHECK-NEXT: maxKernArgAlign: 4 50; CHECK-NEXT: ldsSize: 0 51; CHECK-NEXT: dynLDSAlign: 1 52; CHECK-NEXT: isEntryFunction: true 53; CHECK-NEXT: noSignedZerosFPMath: false 54; CHECK-NEXT: memoryBound: false 55; CHECK-NEXT: waveLimiter: false 56; CHECK-NEXT: hasSpilledSGPRs: false 57; CHECK-NEXT: hasSpilledVGPRs: false 58; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 59; CHECK-NEXT: frameOffsetReg: '$fp_reg' 60; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 61; CHECK-NEXT: argumentInfo: 62; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' } 63; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } 64; CHECK-NEXT: mode: 65; CHECK-NEXT: ieee: false 66; CHECK-NEXT: dx10-clamp: true 67; CHECK-NEXT: fp32-input-denormals: true 68; CHECK-NEXT: fp32-output-denormals: true 69; CHECK-NEXT: fp64-fp16-input-denormals: true 70; CHECK-NEXT: fp64-fp16-output-denormals: true 71; CHECK-NEXT: highBitsOf32BitAddress: 0 72; CHECK-NEXT: occupancy: 10 73; CHECK-NEXT: body: 74define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { 75 ret void 76} 77 78; CHECK-LABEL: {{^}}name: function 79; CHECK: machineFunctionInfo: 80; CHECK-NEXT: explicitKernArgSize: 0 81; CHECK-NEXT: maxKernArgAlign: 1 82; CHECK-NEXT: ldsSize: 0 83; CHECK-NEXT: dynLDSAlign: 1 84; CHECK-NEXT: isEntryFunction: false 85; CHECK-NEXT: noSignedZerosFPMath: false 86; CHECK-NEXT: memoryBound: false 87; CHECK-NEXT: waveLimiter: false 88; CHECK-NEXT: hasSpilledSGPRs: false 89; CHECK-NEXT: hasSpilledVGPRs: false 90; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 91; CHECK-NEXT: frameOffsetReg: '$sgpr33' 92; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 93; CHECK-NEXT: argumentInfo: 94; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 95; CHECK-NEXT: mode: 96; CHECK-NEXT: ieee: true 97; CHECK-NEXT: dx10-clamp: true 98; CHECK-NEXT: fp32-input-denormals: true 99; CHECK-NEXT: fp32-output-denormals: true 100; CHECK-NEXT: fp64-fp16-input-denormals: true 101; CHECK-NEXT: fp64-fp16-output-denormals: true 102; CHECK-NEXT: highBitsOf32BitAddress: 0 103; CHECK-NEXT: occupancy: 10 104; CHECK-NEXT: body: 105define void @function() { 106 ret void 107} 108 109; CHECK-LABEL: {{^}}name: function_nsz 110; CHECK: machineFunctionInfo: 111; CHECK-NEXT: explicitKernArgSize: 0 112; CHECK-NEXT: maxKernArgAlign: 1 113; CHECK-NEXT: ldsSize: 0 114; CHECK-NEXT: dynLDSAlign: 1 115; CHECK-NEXT: isEntryFunction: false 116; CHECK-NEXT: noSignedZerosFPMath: true 117; CHECK-NEXT: memoryBound: false 118; CHECK-NEXT: waveLimiter: false 119; CHECK-NEXT: hasSpilledSGPRs: false 120; CHECK-NEXT: hasSpilledVGPRs: false 121; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 122; CHECK-NEXT: frameOffsetReg: '$sgpr33' 123; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 124; CHECK-NEXT: argumentInfo: 125; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 126; CHECK-NEXT: mode: 127; CHECK-NEXT: ieee: true 128; CHECK-NEXT: dx10-clamp: true 129; CHECK-NEXT: fp32-input-denormals: true 130; CHECK-NEXT: fp32-output-denormals: true 131; CHECK-NEXT: fp64-fp16-input-denormals: true 132; CHECK-NEXT: fp64-fp16-output-denormals: true 133; CHECK-NEXT: highBitsOf32BitAddress: 0 134; CHECK-NEXT: occupancy: 10 135; CHECK-NEXT: body: 136define void @function_nsz() #0 { 137 ret void 138} 139 140; CHECK-LABEL: {{^}}name: function_dx10_clamp_off 141; CHECK: mode: 142; CHECK-NEXT: ieee: true 143; CHECK-NEXT: dx10-clamp: false 144; CHECK-NEXT: fp32-input-denormals: true 145; CHECK-NEXT: fp32-output-denormals: true 146; CHECK-NEXT: fp64-fp16-input-denormals: true 147; CHECK-NEXT: fp64-fp16-output-denormals: true 148define void @function_dx10_clamp_off() #1 { 149 ret void 150} 151 152; CHECK-LABEL: {{^}}name: function_ieee_off 153; CHECK: mode: 154; CHECK-NEXT: ieee: false 155; CHECK-NEXT: dx10-clamp: true 156; CHECK-NEXT: fp32-input-denormals: true 157; CHECK-NEXT: fp32-output-denormals: true 158; CHECK-NEXT: fp64-fp16-input-denormals: true 159; CHECK-NEXT: fp64-fp16-output-denormals: true 160define void @function_ieee_off() #2 { 161 ret void 162} 163 164; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off 165; CHECK: mode: 166; CHECK-NEXT: ieee: false 167; CHECK-NEXT: dx10-clamp: false 168; CHECK-NEXT: fp32-input-denormals: true 169; CHECK-NEXT: fp32-output-denormals: true 170; CHECK-NEXT: fp64-fp16-input-denormals: true 171; CHECK-NEXT: fp64-fp16-output-denormals: true 172define void @function_ieee_off_dx10_clamp_off() #3 { 173 ret void 174} 175 176; CHECK-LABEL: {{^}}name: high_address_bits 177; CHECK: machineFunctionInfo: 178; CHECK: highBitsOf32BitAddress: 4294934528 179define amdgpu_ps void @high_address_bits() #4 { 180 ret void 181} 182 183attributes #0 = { "no-signed-zeros-fp-math" = "true" } 184attributes #1 = { "amdgpu-dx10-clamp" = "false" } 185attributes #2 = { "amdgpu-ieee" = "false" } 186attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" } 187attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" } 188