1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
3
4; Test that SIMachineFunctionInfo can be round trip serialized through
5; MIR.
6
7@lds = addrspace(3) global [512 x float] undef, align 4
8
9; CHECK-LABEL: {{^}}name: kernel
10; CHECK: machineFunctionInfo:
11; CHECK-NEXT: explicitKernArgSize: 128
12; CHECK-NEXT: maxKernArgAlign: 64
13; CHECK-NEXT: ldsSize: 0
14; CHECK-NEXT: isEntryFunction: true
15; CHECK-NEXT: noSignedZerosFPMath: false
16; CHECK-NEXT: memoryBound: false
17; CHECK-NEXT: waveLimiter: false
18; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
19; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
20; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
21; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
22; CHECK-NEXT: argumentInfo:
23; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
24; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
25; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
26; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
27; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
28; CHECK-NEXT: mode:
29; CHECK-NEXT: ieee: true
30; CHECK-NEXT: dx10-clamp: true
31; CHECK-NEXT: body:
32define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
33  %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
34  store float 0.0, float addrspace(3)* %gep, align 4
35  ret void
36}
37
38; CHECK-LABEL: {{^}}name: ps_shader
39; CHECK: machineFunctionInfo:
40; CHECK-NEXT: explicitKernArgSize: 0
41; CHECK-NEXT: maxKernArgAlign: 0
42; CHECK-NEXT: ldsSize: 0
43; CHECK-NEXT: isEntryFunction: true
44; CHECK-NEXT: noSignedZerosFPMath: false
45; CHECK-NEXT: memoryBound: false
46; CHECK-NEXT: waveLimiter: false
47; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
48; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
49; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
50; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
51; CHECK-NEXT: argumentInfo:
52; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
53; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
54; CHECK-NEXT: mode:
55; CHECK-NEXT: ieee: false
56; CHECK-NEXT: dx10-clamp: true
57; CHECK-NEXT: body:
58define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
59  ret void
60}
61
62; CHECK-LABEL: {{^}}name: function
63; CHECK: machineFunctionInfo:
64; CHECK-NEXT: explicitKernArgSize: 0
65; CHECK-NEXT: maxKernArgAlign: 0
66; CHECK-NEXT: ldsSize: 0
67; CHECK-NEXT: isEntryFunction: false
68; CHECK-NEXT: noSignedZerosFPMath: false
69; CHECK-NEXT: memoryBound: false
70; CHECK-NEXT: waveLimiter: false
71; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
72; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
73; CHECK-NEXT: frameOffsetReg: '$sgpr34'
74; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
75; CHECK-NEXT: argumentInfo:
76; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
77; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
78; CHECK-NEXT: mode:
79; CHECK-NEXT: ieee: true
80; CHECK-NEXT: dx10-clamp: true
81; CHECK-NEXT: body:
82define void @function() {
83  ret void
84}
85
86; CHECK-LABEL: {{^}}name: function_nsz
87; CHECK: machineFunctionInfo:
88; CHECK-NEXT: explicitKernArgSize: 0
89; CHECK-NEXT: maxKernArgAlign: 0
90; CHECK-NEXT: ldsSize: 0
91; CHECK-NEXT: isEntryFunction: false
92; CHECK-NEXT: noSignedZerosFPMath: true
93; CHECK-NEXT: memoryBound: false
94; CHECK-NEXT: waveLimiter: false
95; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
96; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
97; CHECK-NEXT: frameOffsetReg: '$sgpr34'
98; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
99; CHECK-NEXT: argumentInfo:
100; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
101; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
102; CHECK-NEXT: mode:
103; CHECK-NEXT: ieee: true
104; CHECK-NEXT: dx10-clamp: true
105; CHECK-NEXT: body:
106define void @function_nsz() #0 {
107  ret void
108}
109
110; CHECK-LABEL: {{^}}name: function_dx10_clamp_off
111; CHECK: mode:
112; CHECK-NEXT: ieee: true
113; CHECK-NEXT: dx10-clamp: false
114define void @function_dx10_clamp_off() #1 {
115  ret void
116}
117
118; CHECK-LABEL: {{^}}name: function_ieee_off
119; CHECK: mode:
120; CHECK-NEXT: ieee: false
121; CHECK-NEXT: dx10-clamp: true
122define void @function_ieee_off() #2 {
123  ret void
124}
125
126; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off
127; CHECK: mode:
128; CHECK-NEXT: ieee: false
129; CHECK-NEXT: dx10-clamp: false
130define void @function_ieee_off_dx10_clamp_off() #3 {
131  ret void
132}
133
134attributes #0 = { "no-signed-zeros-fp-math" = "true" }
135
136attributes #1 = { "amdgpu-dx10-clamp" = "false" }
137attributes #2 = { "amdgpu-ieee" = "false" }
138attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
139