1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s 2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s 3 4; Test that SIMachineFunctionInfo can be round trip serialized through 5; MIR. 6 7@lds = addrspace(3) global [512 x float] undef, align 4 8 9; CHECK-LABEL: {{^}}name: kernel 10; CHECK: machineFunctionInfo: 11; CHECK-NEXT: explicitKernArgSize: 128 12; CHECK-NEXT: maxKernArgAlign: 64 13; CHECK-NEXT: ldsSize: 2048 14; CHECK-NEXT: dynLDSAlign: 1 15; CHECK-NEXT: isEntryFunction: true 16; CHECK-NEXT: noSignedZerosFPMath: false 17; CHECK-NEXT: memoryBound: false 18; CHECK-NEXT: waveLimiter: false 19; CHECK-NEXT: hasSpilledSGPRs: false 20; CHECK-NEXT: hasSpilledVGPRs: false 21; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 22; CHECK-NEXT: frameOffsetReg: '$fp_reg' 23; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 24; CHECK-NEXT: argumentInfo: 25; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 26; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } 27; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } 28; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } 29; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } 30; CHECK-NEXT: mode: 31; CHECK-NEXT: ieee: true 32; CHECK-NEXT: dx10-clamp: true 33; CHECK-NEXT: fp32-input-denormals: true 34; CHECK-NEXT: fp32-output-denormals: true 35; CHECK-NEXT: fp64-fp16-input-denormals: true 36; CHECK-NEXT: fp64-fp16-output-denormals: true 37; CHECK-NEXT: highBitsOf32BitAddress: 0 38; CHECK-NEXT: occupancy: 10 39; CHECK-NEXT: body: 40define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { 41 %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0 42 store float 0.0, float addrspace(3)* %gep, align 4 43 ret void 44} 45 46; CHECK-LABEL: {{^}}name: ps_shader 47; CHECK: machineFunctionInfo: 48; CHECK-NEXT: explicitKernArgSize: 0 49; CHECK-NEXT: maxKernArgAlign: 4 50; CHECK-NEXT: ldsSize: 0 51; CHECK-NEXT: dynLDSAlign: 1 52; CHECK-NEXT: isEntryFunction: true 53; CHECK-NEXT: noSignedZerosFPMath: false 54; CHECK-NEXT: memoryBound: false 55; CHECK-NEXT: waveLimiter: false 56; CHECK-NEXT: hasSpilledSGPRs: false 57; CHECK-NEXT: hasSpilledVGPRs: false 58; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 59; CHECK-NEXT: frameOffsetReg: '$fp_reg' 60; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 61; CHECK-NEXT: argumentInfo: 62; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' } 63; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } 64; CHECK-NEXT: mode: 65; CHECK-NEXT: ieee: false 66; CHECK-NEXT: dx10-clamp: true 67; CHECK-NEXT: fp32-input-denormals: true 68; CHECK-NEXT: fp32-output-denormals: true 69; CHECK-NEXT: fp64-fp16-input-denormals: true 70; CHECK-NEXT: fp64-fp16-output-denormals: true 71; CHECK-NEXT: highBitsOf32BitAddress: 0 72; CHECK-NEXT: occupancy: 10 73; CHECK-NEXT: body: 74define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { 75 ret void 76} 77 78; CHECK-LABEL: {{^}}name: function 79; CHECK: machineFunctionInfo: 80; CHECK-NEXT: explicitKernArgSize: 0 81; CHECK-NEXT: maxKernArgAlign: 1 82; CHECK-NEXT: ldsSize: 0 83; CHECK-NEXT: dynLDSAlign: 1 84; CHECK-NEXT: isEntryFunction: false 85; CHECK-NEXT: noSignedZerosFPMath: false 86; CHECK-NEXT: memoryBound: false 87; CHECK-NEXT: waveLimiter: false 88; CHECK-NEXT: hasSpilledSGPRs: false 89; CHECK-NEXT: hasSpilledVGPRs: false 90; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 91; CHECK-NEXT: frameOffsetReg: '$sgpr33' 92; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 93; CHECK-NEXT: argumentInfo: 94; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 95; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } 96; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' } 97; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' } 98; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' } 99; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' } 100; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' } 101; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' } 102; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } 103; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } 104; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 105; CHECK-NEXT: mode: 106; CHECK-NEXT: ieee: true 107; CHECK-NEXT: dx10-clamp: true 108; CHECK-NEXT: fp32-input-denormals: true 109; CHECK-NEXT: fp32-output-denormals: true 110; CHECK-NEXT: fp64-fp16-input-denormals: true 111; CHECK-NEXT: fp64-fp16-output-denormals: true 112; CHECK-NEXT: highBitsOf32BitAddress: 0 113; CHECK-NEXT: occupancy: 10 114; CHECK-NEXT: body: 115define void @function() { 116 ret void 117} 118 119; CHECK-LABEL: {{^}}name: function_nsz 120; CHECK: machineFunctionInfo: 121; CHECK-NEXT: explicitKernArgSize: 0 122; CHECK-NEXT: maxKernArgAlign: 1 123; CHECK-NEXT: ldsSize: 0 124; CHECK-NEXT: dynLDSAlign: 1 125; CHECK-NEXT: isEntryFunction: false 126; CHECK-NEXT: noSignedZerosFPMath: true 127; CHECK-NEXT: memoryBound: false 128; CHECK-NEXT: waveLimiter: false 129; CHECK-NEXT: hasSpilledSGPRs: false 130; CHECK-NEXT: hasSpilledVGPRs: false 131; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 132; CHECK-NEXT: frameOffsetReg: '$sgpr33' 133; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 134; CHECK-NEXT: argumentInfo: 135; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 136; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } 137; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' } 138; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' } 139; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' } 140; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' } 141; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' } 142; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' } 143; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 } 144; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 } 145; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 146; CHECK-NEXT: mode: 147; CHECK-NEXT: ieee: true 148; CHECK-NEXT: dx10-clamp: true 149; CHECK-NEXT: fp32-input-denormals: true 150; CHECK-NEXT: fp32-output-denormals: true 151; CHECK-NEXT: fp64-fp16-input-denormals: true 152; CHECK-NEXT: fp64-fp16-output-denormals: true 153; CHECK-NEXT: highBitsOf32BitAddress: 0 154; CHECK-NEXT: occupancy: 10 155; CHECK-NEXT: body: 156define void @function_nsz() #0 { 157 ret void 158} 159 160; CHECK-LABEL: {{^}}name: function_dx10_clamp_off 161; CHECK: mode: 162; CHECK-NEXT: ieee: true 163; CHECK-NEXT: dx10-clamp: false 164; CHECK-NEXT: fp32-input-denormals: true 165; CHECK-NEXT: fp32-output-denormals: true 166; CHECK-NEXT: fp64-fp16-input-denormals: true 167; CHECK-NEXT: fp64-fp16-output-denormals: true 168define void @function_dx10_clamp_off() #1 { 169 ret void 170} 171 172; CHECK-LABEL: {{^}}name: function_ieee_off 173; CHECK: mode: 174; CHECK-NEXT: ieee: false 175; CHECK-NEXT: dx10-clamp: true 176; CHECK-NEXT: fp32-input-denormals: true 177; CHECK-NEXT: fp32-output-denormals: true 178; CHECK-NEXT: fp64-fp16-input-denormals: true 179; CHECK-NEXT: fp64-fp16-output-denormals: true 180define void @function_ieee_off() #2 { 181 ret void 182} 183 184; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off 185; CHECK: mode: 186; CHECK-NEXT: ieee: false 187; CHECK-NEXT: dx10-clamp: false 188; CHECK-NEXT: fp32-input-denormals: true 189; CHECK-NEXT: fp32-output-denormals: true 190; CHECK-NEXT: fp64-fp16-input-denormals: true 191; CHECK-NEXT: fp64-fp16-output-denormals: true 192define void @function_ieee_off_dx10_clamp_off() #3 { 193 ret void 194} 195 196; CHECK-LABEL: {{^}}name: high_address_bits 197; CHECK: machineFunctionInfo: 198; CHECK: highBitsOf32BitAddress: 4294934528 199define amdgpu_ps void @high_address_bits() #4 { 200 ret void 201} 202 203attributes #0 = { "no-signed-zeros-fp-math" = "true" } 204attributes #1 = { "amdgpu-dx10-clamp" = "false" } 205attributes #2 = { "amdgpu-ieee" = "false" } 206attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" } 207attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" } 208