1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
3
4; Test that SIMachineFunctionInfo can be round trip serialized through
5; MIR.
6
7@lds = addrspace(3) global [512 x float] undef, align 4
8
9; CHECK-LABEL: {{^}}name: kernel
10; CHECK: machineFunctionInfo:
11; CHECK-NEXT: explicitKernArgSize: 128
12; CHECK-NEXT: maxKernArgAlign: 64
13; CHECK-NEXT: ldsSize: 0
14; CHECK-NEXT: isEntryFunction: true
15; CHECK-NEXT: noSignedZerosFPMath: false
16; CHECK-NEXT: memoryBound: false
17; CHECK-NEXT: waveLimiter: false
18; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
19; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
20; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
21; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
22; CHECK-NEXT: argumentInfo:
23; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
24; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
25; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
26; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
27; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
28; CHECK-NEXT: body:
29define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
30  %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
31  store float 0.0, float addrspace(3)* %gep, align 4
32  ret void
33}
34
35; CHECK-LABEL: {{^}}name: ps_shader
36; CHECK: machineFunctionInfo:
37; CHECK-NEXT: explicitKernArgSize: 0
38; CHECK-NEXT: maxKernArgAlign: 0
39; CHECK-NEXT: ldsSize: 0
40; CHECK-NEXT: isEntryFunction: true
41; CHECK-NEXT: noSignedZerosFPMath: false
42; CHECK-NEXT: memoryBound: false
43; CHECK-NEXT: waveLimiter: false
44; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
45; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
46; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
47; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
48; CHECK-NEXT: argumentInfo:
49; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
50; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
51; CHECK-NEXT: body:
52define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
53  ret void
54}
55
56; CHECK-LABEL: {{^}}name: function
57; CHECK: machineFunctionInfo:
58; CHECK-NEXT: explicitKernArgSize: 0
59; CHECK-NEXT: maxKernArgAlign: 0
60; CHECK-NEXT: ldsSize: 0
61; CHECK-NEXT: isEntryFunction: false
62; CHECK-NEXT: noSignedZerosFPMath: false
63; CHECK-NEXT: memoryBound: false
64; CHECK-NEXT: waveLimiter: false
65; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
66; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
67; CHECK-NEXT: frameOffsetReg: '$sgpr5'
68; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
69; CHECK-NEXT: argumentInfo:
70; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
71; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
72; CHECK-NEXT: body:
73define void @function() {
74  ret void
75}
76
77; CHECK-LABEL: {{^}}name: function_nsz
78; CHECK: machineFunctionInfo:
79; CHECK-NEXT: explicitKernArgSize: 0
80; CHECK-NEXT: maxKernArgAlign: 0
81; CHECK-NEXT: ldsSize: 0
82; CHECK-NEXT: isEntryFunction: false
83; CHECK-NEXT: noSignedZerosFPMath: true
84; CHECK-NEXT: memoryBound: false
85; CHECK-NEXT: waveLimiter: false
86; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
87; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
88; CHECK-NEXT: frameOffsetReg: '$sgpr5'
89; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
90; CHECK-NEXT: argumentInfo:
91; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
92; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
93; CHECK-NEXT: body:
94define void @function_nsz() #0 {
95  ret void
96}
97
98attributes #0 = { "no-signed-zeros-fp-math" = "true" }
99